JPH01160108A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by adding two passive signal processing circuits without adding an active element to a delay equalizing circuit so as to realize a circuit equivalent to the cascade connection of two filters to a delay equalizer by one circuit. CONSTITUTION:An impedance circuit 14 is provided between a collector of a transistor(TR) 2 and a power supply terminal 12 to form a passive filter. The other passive filter is formed by connecting one terminal of an impedance circuit 8 to the emitter of the TR 1, connecting one terminal of an impedance circuit 9 with equal characteristic and one terminal of an impedance circuit 10 to the other terminal of the impedance circuit 8, connecting the other terminal of the impedance circuit 9 to the emitter of the TR 2, connecting the other terminal or the impedance circuit 10 to ground to provide the impedance circuit if equal characteristic to each of the resistors 5, 6. Thus, two independent passive signal processing circuits are added to the delay equalizing circuit to reduce the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing circuit used to configure a delay equalizer or a passive filter.

[Summary of the invention]

The present invention provides a signal processing circuit that is used when configuring a delay equalizer or a passive filter for improving the image quality of a playback screen of a VTR, for example, in which a first transistor, a second transistor, and an emitter of the first transistor are used. a second resistor connected between the emitter of the first transistor and the emitter of the second transistor, and a third resistor connected to the collector of the first transistor. and a reactance circuit connected between the collector of the first transistor and the emitter of the second transistor,
A first passive signal processing circuit having a first impedance circuit connected to the collector of the second transistor; a second passive signal processing circuit having a second impedance circuit connected to the first resistor;
By adding two passive signal processing circuits, a second passive signal processing circuit formed by connecting a second impedance circuit and a third impedance circuit having the same characteristics to the resistor, the circuit scale can be reduced. It was designed to be measured.

The present invention also provides a signal processing circuit that is used when configuring a delay equalizer or a passive filter for improving the image quality of a playback screen of a VTR, for example. a first resistor connected to the emitter of the second transistor; a second resistor connected between the emitter of the first transistor and the emitter of the second transistor; and a third resistor connected to the base of the second transistor. A first impedance circuit is connected to the collector of the second transistor to a delay equalization circuit consisting of a resistor and a reactance circuit connected between the emitter of the first transistor and the base of the second transistor. a first passive signal processing circuit having the same characteristics as the second impedance circuit, and a second impedance circuit connected to the first resistor;
By adding two passive signal processing circuits, a second passive signal processing circuit formed by connecting impedance circuits, the circuit scale can be reduced.

[Prior Art] For example, a VTR playback system includes a circuit that moves the phase of a demodulated luminance signal to improve edge noise and a circuit that corrects nonlinear waveform characteristics in order to improve the image quality of the VTR playback screen. Various signal processing circuits that change the phase and amplitude are provided, such as circuits that perform linear waveform characteristic correction.

In this way, when various signal processing circuits are required, conventionally, a circuit is formed for each circuit that performs one signal processing, and these circuits are connected in cascade to perform the desired signal processing.

[Problems to be solved by the invention] In this way, if a circuit is formed for each circuit that performs one signal processing, if the number of signal processing stages is large, the circuit scale will increase accordingly. A problem arises. For example, in order to improve the image quality of a VTR playback screen, a circuit that moves the phase of the demodulated luminance signal, a circuit that performs nonlinear waveform characteristic correction, and a circuit that performs linear waveform characteristic correction are provided. requires a delay equalizer with constant amplitude characteristics, a filter with non-linear amplitude characteristics, and a filter with linear amplitude characteristics.

If processing equivalent to these processes can be performed in one circuit, the circuit scale can be significantly reduced. Therefore, it is an object of the present invention to provide a signal processing circuit that can add two independent passive signal processing circuits to a delay equalization circuit, thereby reducing the circuit scale.

[Means for solving problems]

This invention includes a first transistor 1 and a second transistor, a first resistor 6 connected to the emitter of the first transistor, and a first transistor 1 and a second transistor connected to the emitter of the first transistor 1 and the second transistor.
a second resistor 5 connected between the emitter of the transistor 2, a third resistor 11 connected to the collector of the first transistor 1, and a third resistor 11 connected between the collector of the first transistor 1 and the second transistor 2; A first passive signal processing circuit is formed by connecting a first impedance circuit 14 to the collector of the second transistor 2, and a delay equalization circuit comprising a reactance circuit 13 connected between the emitter of the second transistor 2 and a reactance circuit 13 connected to the emitter of the second transistor 2. , the second impedance circuit 8.1 for the first resistor 6
0 and a third impedance circuit 8.9 having the same characteristics as the second impedance circuit 8.10 is connected to the second resistor 5, and a second passive signal processing circuit is added. This is a signal processing circuit designed as follows.

The present invention includes a first transistor 31 and a second transistor 32, a first resistor 36 connected to the emitter of the second transistor 32, and a resistor 36 connected to the emitter of the first transistor 31 and the emitter of the second transistor 32. a second resistor 35 connected between the second resistor 35, a third resistor 41 connected to the base of the second transistor, and a third resistor 41 connected between the emitter of the first transistor 31 and the base of the second transistor 32. A first passive signal processing circuit including a first impedance circuit 44 connected to the collector of the second transistor 32; second impedance circuit 38
．． 40 is connected to the second resistor 35, and a third impedance circuit 38.39 having the same characteristics as the second impedance circuit 38.40 is connected to the second resistor 35. This is an additional signal processing circuit.

[Effect]

Two passive signal processing circuits can be added to the delay equalization circuit of the transfer function expressed by the following formula.

vout= r　z　　　R+　J　X However, rz=r.

That is, by providing an impedance circuit for the resistance value RL of the delay equalization circuit represented by such a transfer function, the first passive signal processing circuit can be added.

Furthermore, an impedance circuit is provided for the resistance value r2,
A second passive signal processing circuit can be added by providing an impedance circuit with the same characteristics as the impedance for the resistance value r2 for the resistance value r1.

In this way, two passive signal processing circuits can be added without adding active elements to the delay equalization path, so for example, V
A circuit equivalent to a delay equalizer used for improving the image quality of the TR reproduction system in which two filters are connected in cascade can be realized with one circuit, and the circuit scale can be reduced.

〔Example〕

Embodiments of the present invention will be described in the following order.

a. Structure of one embodiment, explanation of operation of one embodiment C6. Other embodiments d. Example used in a signal processing circuit of a VTR a. Structure of one embodiment FIG. 1 shows one embodiment of the present invention This shows that. This embodiment can obtain characteristics equivalent to a circuit in which two passive filters are connected in cascade to a delay equalizer.

In Figure 1, input terminal 3 is connected to the base of transistor 1.
is connected to the base of the transistor 2, and a DC power source 4 is connected to the base of the transistor 2. Emitter of transistor 1 and transistor 2
A resistor 5 is connected between the emitter of the transistor 1, a resistor 6 is connected between the emitter of the transistor 1 and the ground, and a resistor 7 is connected between the emitter of the transistor 2 and the ground.

Further, one end of an impedance circuit 8 is connected to the emitter of the transistor 1. The other end of the impedance circuit 8 is connected to one end of the impedance circuit 9 and also to one end of the impedance circuit 10 . The impedance circuit 9 and the impedance circuit 10 have the same characteristics. The other end of impedance circuit 9 is connected to the emitter of transistor 2. The other end of impedance circuit 10 is grounded.

The collector of transistor 1 is connected to power supply terminal 12 via resistor 11, and a reactance circuit 13 is connected between the collector of transistor 1 and the emitter of transistor 2. The collector of transistor 2 is connected to one end of impedance circuit 14, and output terminal 15 is led out from the collector of transistor 2. The other end of impedance circuit 14 is connected to power supply terminal 12 .

b. Description of operation of one embodiment It will be explained that when configured as shown in FIG. 1, characteristics are equivalent to a circuit in which a delay equalizer is connected in cascade with two passive filters.

The embodiment shown in FIG. 1 is based on a delay equalizer configured as shown in FIG. 2, and has a configuration in which two passive filters are combined with this delay equalizer. Each passive filter can then be characterized independently. In explaining the operation of the above-mentioned embodiment, first, the operation of the delay equalizer that is the basis of this will be explained.

In the delay equalizer shown in FIG. 2, components corresponding to those in the embodiment shown in FIG. 1 are given the same reference numerals. Let us find the transfer function of this delay equalizer.

In FIG. 2, it is assumed that an input signal Vi is supplied to the input terminal 3. At this time, the voltage at the emitter of transistor 1 becomes vifi in terms of alternating current. On the other hand, the voltage at the emitter of transistor 2 is 0 in terms of alternating current.

From this, if the resistance value of the resistor 6 is r, then the resistor 6
The current il flowing through is 1I=vi/rl (1). Also, if the resistance value of the resistor 5 is r2, then the resistor 5
The current 12 flowing through is iz = V tyt/r z (2).

If the current flowing through the resistor 11 is i, and the current flowing through the reactance circuit 13 is i4, then there is the following relationship: i3+14=iI+it (3).

The voltage vc appearing at the collector of transistor 1 is resistor 11
If the resistance value of is R, then Vc = i 3R...=(4). Therefore, if the current flowing through the reactance circuit 13 is i4 and the reactance of the reactance circuit 13 is jx, then i 4 = i 3 R/ j x =.=(5). From equations (1), (2), (3), and (5),
...(6) ...(7) Output current i. ut is 1out""il t4...(8), so 1 out"" (vin/r I)---...
・(9) ...(10) Therefore, the output voltage V. When the resistance value of the resistor 20 is Rt, ut is V out = RL ·l. ut! R.L.
(rz /r+)R+jx... (11) It becomes. From equation (11), it can be seen that if rl=rz, then the following equation is obtained (12), and a delay equalizer characteristic can be obtained.

Now, consider adding one passive filter to this delay equalizer. From equation (11), it is conceivable to provide an impedance circuit in the portion of the resistance value RL. That is, as shown in FIG. 3, an impedance circuit 14 is provided for the resistor 20 in FIG. 2.

For the resistor 20 in FIG. 2, the transfer function is F(jω
) When the impedance circuit 14 is provided, the transfer function of this circuit becomes: (13) It can be seen that characteristics equivalent to adding one passive filter to the delay equalizer can be obtained.

Now consider adding another passive filter.

From equation (13), it is possible to provide an impedance circuit for the resistance value r2. However, equation (13) is the characteristic when r, = r in equation (11),
If the resistance value r2 has an impedance characteristic whose amplitude changes, the amplitude characteristic of the delay equalizer section will not be constant.

To make the amplitude characteristics of the delay equalizer part constant,
From equation (11), the ratio of rl and r2 must be constant.

Therefore, in order to add yet another passive filter to this delay equalizer, an impedance circuit is provided for the resistance value r2, and the characteristics of the impedance circuit provided for the resistance value r2 are It is necessary to provide an impedance circuit with similar characteristics.

From the above, when combining two passive filters into the delay equalizer shown in FIG. 2, as shown in FIG. 3, an impedance circuit 14 is provided for the resistor 20 in FIG. Along with adding a filter,
Impedance circuit 21 for resistor 5 in FIG.
It is conceivable to provide a second passive signal processing circuit by providing an impedance circuit 22 having the same characteristics as the impedance circuit 21 for the resistor 6.

However, when two passive filters are added in this way, the impedance circuit 21 and the impedance circuit 22 must have completely equal characteristics. However, it is difficult to add impedance circuits with completely equal characteristics to each of the resistors 5 and 6.

Therefore, in this embodiment, as shown in FIG. 1, an impedance circuit 14 is provided between the collector of the transistor 2 and the power supply terminal 12 to form one passive filter. In the other passive filter, one end of an impedance circuit 8 is connected to the emitter of the transistor 1, and one end of an impedance circuit 9 and an impedance circuit 10 having the same characteristics are connected to the other end of the impedance circuit 8.
one end of the impedance circuit 9 is connected, the other end of the impedance circuit 9 is connected to the emitter of the transistor 2, and the impedance circuit 10 is
The other end is grounded, and an impedance circuit having the same characteristics is provided for each of the resistors 5 and 6.

In this case, as shown in FIG.
Impedance circuits 9 and 1 are provided with desired amplitude characteristics to impedance circuits 8 which are commonly arranged for impedance circuits 9 and 6.
As zero, resistors having the same resistance value can be used. If it is a resistor, it is easy to make the characteristics the same. Note that the capacitor 23 is provided for DC cut.

As shown in FIG. 4, the transfer function when two passive filters are added to the delay equivalent circuit is as follows.

In FIG. 4, if input signal Vifi is supplied to input terminal 3, the emitter voltage of transistor 1 is set to Vifi.
If the resistance values of R1 resistor 5 and resistor 6 are r, the current i++ flowing through resistor 5 is: 1 + r = V t n/ r ””...(
21). Current i+ flowing through impedance circuit 8
z is the impedance of the impedance circuit 8 as Z(j
ω), and the resistance values of the impedance circuits 9 and 10 are represented by r'. The current i+3 flowing through the impedance circuit 9 is as follows. The current i+a flowing through the reactance circuit 13 is
The reactance of the reactance circuit 13 is jx, and the resistance 11 is
If the resistance value of is R, then...(24) Therefore, the output voltage V. 6t is the impedance circuit 14
If the transfer function of is F(jω), then...(25
) becomes. From the above equation, it can be seen that two passive signal filters can be added to the delay equalizer.

Other Examples of C0 In addition to the configuration shown in FIG. 2, there is a configuration OL shown in FIG. 5 as a delay equalization circuit whose transfer function is obtained in the same way as equation (11).

In FIG. 5, an input terminal 33 is connected to the base of a transistor 31. The base of transistor 32 is resistor 4
1, and the other end of the resistor 41 is connected to the DC power supply 34.

A resistor 35 is connected between the emitter of the transistor 31 and the emitter of the transistor 32, a resistor 36 is connected between the emitter of the transistor 32 and ground, and a resistor 37 is connected between the emitter of the transistor 31 and ground.

A collector of transistor 31 is connected to power supply terminal 42 . Emitter of transistor 31 and transistor 320
A reactance circuit 43 is connected between the base and the base. A collector of the transistor 32 is connected to a power supply terminal 42 via a resistor 50, and an output terminal 45 is led out from the collector of the transistor 32.

The transfer function of the delay equalization circuit configured in this way is such that the resistance value of the resistor 36 is rI, the resistance value of the resistor 35 is rZ, and the resistor 4 is
If the resistance value of R1 is R1, the resistance value of resistor 50 is RL, and the reactance of reactance circuit 43 is jx, then the above-mentioned second
Similar to the delay equalization circuit shown in the figure, its transfer function is (1
1) It is obtained as shown in the formula. From this, as shown in FIG. 6, if an impedance circuit 44 is provided for the resistor 50 in FIG.
Filters can be added. Further, one end of an impedance circuit 38 is connected to the emitter of the transistor 32, the other end of the impedance circuit 38 is connected to one end of an impedance circuit 39, and one end of an impedance circuit 40 having the same characteristics as the impedance circuit 39 is connected. One more passive filter can be added by connecting the other end of the impedance circuit 39 to the emitter of the transistor 31 and grounding the other end of the impedance circuit 40.

d. An example of use in a VTR signal processing circuit The present invention is suitable for use in a circuit for improving the image quality of a VTR playback screen.

FIG. 7 shows an example of the configuration of a VTR image quality improvement circuit to which the present invention can be applied. In FIG. 7, 51 is an FM demodulation circuit for FM demodulating the reproduced luminance signal of the VTR;
is a de-emphasis circuit. The image quality improvement circuit 53 to which the present invention is applicable is inserted between the FM demodulation circuit 51 and the de-emphasis circuit 52. This image quality improvement circuit 5
3 includes an equalizer circuit 54 that manipulates the phase in order to improve edge noise, a hard clip return circuit 55 that nonlinearly corrects hard clips, and a low frequency circuit that replenishes low frequency components and performs linear waveform correction. Area peak key circuit 5
It consists of 6. These circuits improve image quality.

This image quality improvement circuit 53 can be configured as shown in FIG. 8 by applying the present invention.

That is, in FIG. 8, the input terminal 63 is connected to the base of the transistor 61, and the DC power supply 64 is connected to the base of the transistor 62. A resistor 65 is connected between the emitter of the transistor 61 and the emitter of the transistor 62, a resistor 66 is connected between the emitter of the transistor 61 and ground, and a resistor 67 is connected between the emitter of the transistor 62 and ground. The resistance value of the resistor 65 and the resistance value of the resistor 66 are set to be equal to each other.

Further, one end of an impedance circuit 68 is connected to the emitter of the transistor 61. The other end of the impedance circuit 68 is connected to one end of a resistor 69, and the resistor 70
connected to one end of the The impedance circuit 68 includes a diode 91, a capacitor 92, and a resistor 93, and has nonlinear characteristics. The resistor 69 and the resistor 70 have the same characteristics. The other end of the resistor 69 is connected to the emitter of the transistor 62 via a DC cut capacitor 83. The other end of resistor 70 is grounded.

A collector of the transistor 61 is connected to a power supply terminal 72 via a resistor 71, and a reactance circuit 73 is connected between the collector of the transistor 61 and the emitter of the transistor 62.

The reactance circuit 73 includes a coil 94 and a capacitor 95.
It consists of The collector of the transistor 62 is connected to one end of an impedance circuit 74 via a resistor 80, and an output terminal 75 is led out from the collector of the transistor 62. The other end of impedance circuit 74 is connected to power supply terminal 72 .

Equalizer circuit 5 in the part including reactance circuit 73
4, a hard tap return circuit 55 for correcting non-linear characteristics is formed in a portion including an impedance circuit 68, a resistor 69, and a resistor 70, and a low-frequency peaking circuit for correcting linear characteristics in a portion including an impedance circuit 74. 56 are configured.

If a circuit that performs such processing is formed for each circuit, at least two active circuits will be required, one consisting of transistors 101 and 102 and the other consisting of transistors 111 and 112, as shown in FIG. Become. That is, in FIG. 9, transistors 101 and 102, a capacitor 103, a diode 104, and resistors 105 to
An impedance circuit consisting of 107 and resistors 108 to 1
A hard clip return circuit 55 is constituted by a circuit consisting of 11. Transistors 111 and 112 and coil 11
3 and a capacitor 114, and a circuit consisting of resistors 115 to 118.
4 is composed. A low frequency peaking circuit 56 is constituted by a circuit including a capacitor 121, a resistor 122, and a coil 123.

Note that 131 is an input terminal, 132 is an output terminal, and 133 is a power supply terminal.

In the image quality improvement circuit 53 to which the present invention is applied, one active circuit consisting of transistors 61 and 62 can perform processing equivalent to cascading the equalizer circuit 54, hard clip return circuit 55, and low frequency peaking circuit 56. , the circuit scale can be significantly reduced compared to the case where each circuit is formed separately as shown in FIG.

〔Effect of the invention〕

According to this invention, two passive signal processing circuits can be added to the delay equalization circuit without adding any active elements. For this reason,
For example, a circuit equivalent to a delay equalizer with two filters connected in cascade can be realized with one circuit, and the circuit scale can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a connection diagram of one embodiment of this invention, Figs. 2 to 5 are connection diagrams used to explain one embodiment of this invention, and Fig. 5 is used to explain another embodiment of this invention. 6 is a connection diagram of another embodiment of the present invention, FIG. 7 is a block diagram of an example of a VTR image quality improvement circuit to which this invention can be applied, and FIG. 8 is a VTR image quality improvement circuit to which this invention can be applied. FIG. 9 is a connection diagram of an example in which the image quality improvement circuit of a VTR is constituted by an independent circuit. Explanation of main symbols in the drawings 1.2, 31.32:) transistor, 8, 9.10.3
8, 39.40: Impedance circuit, 13.43: Reactance circuit. X+V*Intermediate 1 Fig. 1 Fig. 51r colliner stop '1 Fig. 2 y

Claims (2)

[Claims] (1) a first transistor and a second transistor;
a first resistor connected to the emitter of the first transistor; a first resistor connected to the emitter of the first transistor; and a first resistor connected to the emitter of the first transistor;
a second resistor connected between the emitter of the transistor; a third resistor connected to the collector of the first transistor; and a third resistor connected between the collector of the first transistor and the emitter of the second transistor. a first passive signal processing circuit formed by connecting a first impedance circuit to the collector of the second transistor; a second passive signal processing circuit in which a second impedance circuit is connected to the resistor, and a third impedance circuit having the same characteristics as the second impedance circuit is connected to the second resistor; A signal processing circuit that adds (2) a first transistor and a second transistor;
a first resistor connected to the emitter of the second transistor; and a first resistor connected to the emitter of the first transistor;
a second resistor connected between the emitter of the transistor, a third resistor connected to the base of the second transistor, and the emitter of the first transistor and the base of the second transistor. a first passive signal processing circuit including a first impedance circuit connected to the collector of the second transistor; and a first passive signal processing circuit including a first impedance circuit connected to the collector of the second transistor; a second passive signal processing circuit, in which a second impedance circuit is connected to the resistor, and a third impedance circuit having the same characteristics as the second impedance circuit is connected to the second resistor; A signal processing circuit designed to