JPH0441526B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a limiter circuit used in an FM demodulation circuit or the like, and particularly relates to an improvement in the limiter balance of the limiter circuit.

Conventional configuration and its problems FM modulation is a known method for transmitting and recording signals. A characteristic of FM modulated signals is that the FM signal that is transmitted or reproduced from a recording medium is passed through an amplitude limiting circuit, that is, a limiter circuit, and then demodulated. It is known that it is possible to eliminate the influence of amplitude fluctuations in signals during reproduction. An FM demodulation circuit having such a limiter circuit is used, for example, to demodulate FM broadcasts, demodulate VTR video signals, and demodulate video and audio signals from video discs.
Performance requirements for limiter circuits used in these devices include high gain (for example, 70 dB or more) and a well-balanced limiter.

FIG. 1 shows an example of a commonly used limiter circuit using a differential amplifier circuit. The transistors 2 and 3 constitute a differential amplifier circuit with their emitters coupled, through which a current determined by a current source 4 flows. A signal source 1 is connected to the base of the transistor 2, and a load resistor 5 is connected to the collector of the transistor 3. Terminals 6 and 8 are
Connected to positive and negative power supplies, respectively. The relationship between the input voltage V _IN of this circuit and the collector current I _CQ3 of the transistor 3 is expressed by equation (1) assuming that h _FE of the transistor is sufficiently large.

I _CQ3 = I _O・exp(V _IN /V _T )/1+exp(V _IN /V _T )...
(1) Here, I _O is the current of the current source 4, and V _T is a constant expressed by equation (2).

V _T =k _T /q (2) where k is the Holtzmann constant, T is the absolute temperature, and q is the amount of charge of the electron.

V _T is generally called the thermovoltage and is approximately
It is known that the voltage is 26mV.

FIG. 2 illustrates equation (1).

From Figure 2, the input voltage is ±4V _T (±100mV)
When the voltage exceeds 0, the collector current I _CQ3 becomes approximately _IO or 0, and remains a constant value regardless of the input voltage. Therefore, the differential amplifier circuit shown in FIG. 1 has a gain of 0 when the input voltage amplitude is ±100 mV or more. This means that the output amplitude is limited for input amplitudes above a certain value, and the circuit operates as a limiter circuit. On the other hand, the gain A ₀ of the differential amplifier circuit shown in Figure 1 when a small signal is input is expressed as A ₀ = I _O /2V _T・_{RL (3), where R L is} the resistance value of resistor 5. It will be done. Here, for example, R _L = 1KΩ, I _O =
Substituting 1mA to find the gain A ₀ is A ₀ 19.2 times 25.7dB. By the way, a single-stage differential amplifier circuit as shown in Figure 1 is rarely used as a limiter circuit because the gain is low and the input voltage to which the amplitude is limited is as large as ±100 mV. , it is common to connect several stages of differential amplifier circuits and use it as a limiter circuit. Since such multi-stage connected differential amplifier circuits have a large number of components, they are generally configured as integrated circuits.

In integrated circuits, differential amplifier circuits are usually directly coupled to form a multistage amplifier circuit.
The operating point may become unstable due to factors such as variations in parts. The situation at this time is shown in Figure 3.

In FIG. 3, a indicates the input waveform of the limiter circuit. Here, the dash-dotted line indicates the AC center of the input signal, and in the case of an ideal limiter circuit, the amplitude is limited after passing through a high gain circuit so that it is vertically symmetrical with respect to this AC center. Due to the limiter operation, the output waveform becomes a vertically symmetrical square wave as shown in b. On the other hand, c and d are
This shows a case where the operating point of the limiter circuit shifts and undesirable operation occurs. In c, the input waveform of the limiter circuit is shown. If the operating point shifts from the AC center indicated by the dashed-dotted line to the position indicated by the solid line, the limiter operation will be performed around this point, and the limiter circuit at this time will be The output waveform is a waveform with a shifted duty ratio, as shown in d.
In such a state, the limiter is unbalanced, and the limiter may not operate properly when the input is small, or undesirable distortion components or unnecessary signal components may be mixed into the output of the FM demodulation circuit. , which causes deterioration in the performance of the FM demodulation circuit.

Therefore, a generally known method is to apply DC feedback to the limiter circuit to prevent such deterioration of the limiter balance.

FIG. 4 shows an example of a limiter circuit having a DC feedback circuit and using differential amplifier circuits connected in multiple stages. The circuit in the figure shows an integrated circuit state, and the inside of the thick solid line shows the inside of the integrated circuit. Transistors 20 and 21, 22 and 2
3, 24 and 25 each constitute a differential amplifier circuit. Transistor 26, 27, 28, 2
Reference numeral 9 constitutes an emitter follower circuit, which directly couples the differential amplifier circuits. transistor 3
0, 31, 32, 33, 34, 35, 36 and resistance 45, 46, 47, 48, 49, 50, 51
constitute a constant current source, and the operating currents of the differential amplifier circuit or the emitter follower circuit are determined to be equal to each other. resistance 52
is the resistance that determines the input impedance of the limiter circuit. The capacitor 70 is connected to the input terminal 10 of the integrated limiter circuit, and serves to cut off DC components between the capacitor 70 and the terminal 12 to which the signal source is connected. Terminal 13
is an output terminal of the limiter circuit, terminal 14 is an input terminal of a power supply, terminal 9 is a grounding terminal, and constant voltage source 15 generates a reference voltage for operating the above-mentioned constant current source. The DC feedback circuit includes a resistor 60 and an external capacitor 71. The first differential amplifier circuit composed of the transistors 20 and 21 is connected through the resistor 52 so that their base potentials are equal, so that its operating point is determined by the DC feedback voltage V _f appearing at the terminal 11. will not change. Now, assuming that the collector current of transistor 30 is I _Q30C and h _FE is sufficiently large, collector currents I _Q20C and I _Q21C of transistors 20 and 21 are as follows.

I _Q20C = I _Q21C = 1/2・I _Q30C (4) Therefore, if the resistance value of the resistor 40 is R ₄₀ , the base-emitter voltage of the transistor 26 is V _BEQ26 , and the power supply voltage is Vc.c. The base voltage V _Q22B of No. 22 is expressed as V _Q22B = Vc.c.-1/2 ・I _Q30C・R ₄₀ −V _BEQ26 (5). This voltage is
It remains a constant value without being affected by the value of V _f .

Now, let us consider a case where the duty ratio of the waveform output to the terminal 13 deviates for some reason.
If the period of the positive half-wave becomes larger than the period of the negative half-wave, the resistor 60 and capacitor 7
The DC feedback voltage V _f that passes through the low-pass filter configured with 1:1 and is output to the terminal 11 is higher than V _f when the duty ratio is 1:1. This means that the input voltage on the transistor 23 side of the second differential amplifier circuit composed of the transistors 22 and 23 becomes higher. At this time, the output waveform of the collector of the transistor 23 changes in a direction in which the period of the positive half-wave becomes smaller than the period of the negative half-wave. The collector output waveform of the transistor 23 is amplified with positive polarity by a third differential amplifier circuit composed of transistors 24 and 25, and then outputted to the terminal 13. At this time, terminal 1
The output waveform of No. 3 changes in the direction in which the period of the positive half wave becomes smaller. This means that feedback is performed in the direction where the duty ratio becomes 1:1. Even if the period of the positive half wave of the waveform output to the terminal 13 deviates in the direction of becoming smaller than the period of the negative half wave, the duty ratio is similarly fed back to 1:1.

By the way, in the above operation, it is assumed that there is no variation in the transistor and resistance, and that h _FE of the transistor is infinitely large. Among these assumptions, variations between components can be made substantially negligible by integrating the circuit and arranging elements close to each other. However, since h _FE cannot be made extremely large, this effect occurs. Therefore, the influence of h _FE on the DC feedback circuit will be explained with reference to FIG.
In FIG. 4, the DC feedback circuit composed of the resistor 60 and the capacitor 71 is connected to the terminal 1 as described above.
It functions to take out only the DC component of the terminal 13 and equalize the DC voltage of the terminal 13 and the base voltage of the transistors 20, 21, and 23. However, since the h _FE of the transistor is finite, a base current flows through the base of each transistor, and as a result,
A voltage drop will occur across resistor 60, creating an error in the DC feedback path described above. In other words, the base current of transistors 20, 21, 23 is
Assuming that I _BQ20 , I _BQ21 , I _BQ23 and the resistance value of the resistor 60 are R ₆₀ , there is a voltage drop across the resistor 60 due to the base current, that is, an error voltage V _err in the DC feedback path, V _err = R ₆₀ ( I _BQ20 + I _BQ21 + I _BQ23 ) ...(6) occurs.

Even if this voltage drop V _err is relatively small, the gain of the limiter circuit is large, so it cannot be ignored and causes deterioration of the balance of the limiter circuit. Therefore, the use of a limiter circuit having a DC feedback circuit of the type shown in FIG. 4 has been limited to limiter circuits with relatively small gains or circuits that do not require very high precision. On the other hand, high gain,
For limiter circuits that require high precision, a configuration with two DC feedback circuits as shown in FIG. 5 has been used. In Figure 5, 10
0 is the input terminal, 101 is the input capacitor, 10
2 is a resistor, 103 and 104 are external capacitors for DC feedback, 105 is a signal input terminal, 106 and 1
07 is a terminal for DC feedback, 108 is a power supply terminal, 1
65 is the ground terminal, 109 is the limiter output terminal,
110 to 115 are load resistances of transistors, transistors 130 to 135 are transistors forming a differential amplifier circuit, and transistor 1
50 to 158, resistors 116 to 124, and voltage source 1
60 constitutes a constant current source. The first DC feedback path includes a resistor 125 and capacitors 103 and 10.
4, and a feedback voltage is input to the base of the transistor 131. The second DC feedback path includes a resistor 126 and a capacitor 104, and a feedback voltage is input to the base of a transistor 130. A voltage drop occurs in these DC feedback paths due to the base current of each transistor and the feedback resistance, but since the DC feedback paths are almost symmetrical, this voltage drop is reduced by the transistors 130 and 13.
1, and does not cause deterioration of the balance of the limiter. However, as shown in FIG. 5, two terminals for DC feedback must be provided.

Purpose of the Invention The present invention improves the limiter balance in a limiter circuit with a single DC feedback circuit, which has conventionally been used only when the gain is relatively low or when high precision is not required. The aim is to realize a high-gain, high-precision limiter circuit.

Arrangements of the Invention The arrangements of the invention flow in the input circuit of the feedback voltage into a single DC return path of the limiter circuit.

By providing a circuit that adds current equivalent to the input current in the opposite direction, it compensates for errors that occur in the DC feedback path, thereby improving the limiter balance of limiter circuits with a single DC feedback circuit. This achieves high gain and high precision.

DESCRIPTION OF THE EMBODIMENT FIG. 6 shows a block diagram of an embodiment of the present invention. In the same figure, 170 is the limiter section at the front stage, and 170 is the limiter section at the front stage.
Reference numeral 1 indicates a limiter section at the latter stage, 172 a DC feedback circuit, 173 a compensation current generation circuit, and 174 an adder circuit. The compensation current generation circuit of 173 is
A current corresponding to the input current flowing in the compensation voltage input circuit of the limiter circuit 170 at the previous stage is generated as a compensation current.

FIG. 7 shows a specific embodiment of the present invention. This figure shows an application of the embodiment of the present invention to the conventional example of FIG. 4, so parts with the same functions are given the same numbers.

including first and second differential amplifier circuits configured with transistors 20 and 21 and 22 and 23;
The block 200 is the limiter section 1 at the front stage in FIG.
Corresponds to 70. A block 201 including third and fourth differential amplifier circuits constituted by transistors 24 and 25 and 122 and 123 corresponds to the limiter section 171 at the latter stage in FIG. Here, a fourth differential amplifier circuit was added to increase the limiter gain. Resistor 60 and capacitor 71
A block 202 consisting of the following functions as a low-pass filter for removing high frequencies, and corresponds to the DC feedback circuit 172 in FIG. transistor 80~8
3. The block 203 composed of the resistor 84 corresponds to the compensation current generation circuit 173 in FIG.
Contact 204 corresponds to adder circuit 174 in FIG.

Next, the operation of the compensation current generation circuit 203 will be explained. Collector current of transistor 83
I _CQ83 is determined as follows by appropriately selecting the resistor 84.

0I _CQ83 = I _CQ30 + 1/2 I _CQ32 (7) Here, I _CQ30 and I _CQ32 represent collector currents of transistors 30 and 32, respectively.

Transistors 80 and 81 constitute a current mirror circuit, and h _FE of each transistor is 1.
If it is sufficiently larger than , the following formula holds true.

I _CQ80 I _CQ81 = I _BQ82 = I _EQ82 /h _FE −1 = I _CQ83 /h _FE −1 ...(8) Here, I _CQ80 and I _CQ81 are transistors 80 and 81
, I _CQ82 and I _EQ82 represent the collector current and emitter current of transistor 82.

On the other hand, from the contact 204, the transistor 20,
Current flowing out as base current of 21, 23 I _BO
is expressed as I _BO =I _BQ20 +I _BQ21 +I _BQ23 (9), where the base currents of transistors 20, ₂₁ , and ₂₃ are respectively I _BQ20 , I BQ21 , and I BQ23 . Here, h _FE of each transistor
If it is assumed that the emitter currents of the transistors 20 and 21 and the emitter currents of the transistors 23 and 23 that constitute the differential amplifier circuit are equal, then equation (10) holds true.

I _BO = 1/h _FE −1・I _EQ20 +1/h _FE −1 ・I _EQ21 +1/h _FE −1・I _EQ23 = 1/h _FE −1 (I _EQ20 + I _EQ21 + I _EQ23 ) = 1/h _FE −1(I _CQ30 +1/2I _CQ32 ) (10) Here, I _EQ20 , I _EQ21 , and I _EQ23 represent the emitter currents of the transistors 20, 21, and 23, respectively. Therefore, from equations (7), (8), and (10), I _BO = I _CQ83 /h _FE −1 = I _CQ80 ... (11) holds true.

At this time, in Fig. 7, if the error voltage V _err1 in the DC feedback path, that is, the voltage across the resistor 60, is found, V _err1 = R ₆₀ (I _BO − I _CQ80 ) = 0 (12), and the resistance No voltage will be generated across 60.

This means that the DC voltage at terminal 13 is accurately transmitted to the base of transistor 23. This eliminates the error caused by the DC feedback circuit that occurred in the circuit of FIG. 4, and therefore improves the balance of the limiter, making it possible to realize a limiter with higher precision and higher gain.

FIGS. 8 and 9 show an embodiment of the invention in which the circuit for generating the compensation current has increased accuracy. In the example of FIG. 8, the accuracy of the current source can be improved by making the resistor 92 equal to the resistor 45 and selecting the resistor 93 to an appropriate value such that the collector current of the transistor 91 is half the collector current of the transistor 32. is increasing. In the example of FIG. 9, transistors 94, 95, and 96 are replaced by transistors 20 and 20, respectively.
By making them the same as 21 and 23, the accuracy of the compensation current generation circuit is improved.

Effects of the Invention As described above, in the present invention, a high-gain, high-precision limiter circuit, which could conventionally only be realized with a limiter circuit having two DC feedback circuits, can be realized by using a single DC feedback circuit. This can be achieved by providing a limiter circuit with a means to compensate for the error voltage generated in the DC feedback path. This not only improves the performance of limiter circuits with a single DC feedback circuit, but also In order to realize a high-gain, high-precision limiter circuit in a circuit, what used to require three terminals for external components can now be realized by providing only two terminals for external components, and the high-performance integrated circuit This enables integration and reduction of external parts.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional differential amplifier circuit, Figure 2 is a diagram showing the input/output characteristics of the same differential amplifier circuit, Figure 3 is a diagram showing input/output waveforms of a limiter circuit, 4 and 5 are circuit diagrams of conventional limiter circuits, FIG. 6 is a block diagram of an embodiment of the limiter circuit of the present invention, and FIG. 7 is a circuit diagram of the same embodiment.
8 and 9 are circuit diagrams of other embodiments of the present invention. 170...Previous stage limiter section, 171...Late stage limiter section, 172...DC feedback circuit, 1
73...compensation current generation circuit, 174...addition circuit.

Claims (1)

[Claims] 1. Limiter sections 200 and 201 in which differential amplifier circuits are connected in series in multiple stages so as to be non-inverted, and a DC feedback circuit 202 that serves as a low-pass filter for removing high frequencies and is composed of a resistor 60 and a capacitor 71.
and a compensation current generation circuit 203 that generates a current, and the output 13 of the limiter section 200, 201 is passed through the resistor 60 of the DC feedback circuit 202 to the transistor of the input stage differential amplifier circuit consisting of transistors 20, 21. 21 and the inverting input of the transistor 23 of the next-stage differential amplifier circuit consisting of transistors 22 and 23 are connected to a DC feedback point 204, and the DC feedback point 2
04 is grounded via the capacitor 71, and the DC feedback circuit 202 is connected to the DC feedback point 20.
4 is connected to the non-inverting input of the transistor 20 of the input stage differential amplifier circuit and the input 10 of the limiter section 200, 201, and the output of the compensation current generating circuit 203 is connected to the DC feedback point. 204, the current generated by the compensation current generating circuit 203 is made substantially equal to the sum of the base currents of the transistors 20 and 21 and the base current of the transistor 23, so as to cancel out the three base currents; Reverse limiter circuit.