JPH01149132U

JPH01149132U -

Info

Publication number: JPH01149132U
Application number: JP4491288U
Authority: JP
Priority date: 1988-04-01
Filing date: 1988-04-01
Publication date: 1989-10-16

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例によるバイポーラ
論理回路を示す回路図、第２図は第１図の実施例
のタイムチヤート、第３図は従来のバイポーラ論
理回路を示す回路図である。図において、１は入力端子、２は外部出力端子
、３は高電位電源用端子、４は低電位電源用端子
、５は入力ＳＢＤ、６は第１のトランジスタ、７
はダーリントン回路前段のＳＢＤＴｒ、８はダ
ーリントン回路後段のｎｐｎＴｒ、９は第２の
トランジスタ、１０はプルダウン用ＳＢＤＴｒ
、１１は入力保護ＳＢＤ、１２〜１７は抵抗器、
但し、１５は第１の抵抗器、１８は容量性負荷、
１９は第３のトランジスタ、２０は第２の抵抗器
を示す。なお、図中、同一符号は同一、又は相当
部分を示す。 FIG. 1 is a circuit diagram showing a bipolar logic circuit according to an embodiment of this invention, FIG. 2 is a time chart of the embodiment of FIG. 1, and FIG. 3 is a circuit diagram showing a conventional bipolar logic circuit. In the figure, 1 is an input terminal, 2 is an external output terminal, 3 is a high-potential power supply terminal, 4 is a low-potential power supply terminal, 5 is an input SBD, 6 is a first transistor, and 7
is the SBD Tr before the Darlington circuit, 8 is the NPN Tr after the Darlington circuit, 9 is the second transistor, and 10 is the SBD Tr for pull-down.
, 11 is an input protection SBD, 12 to 17 are resistors,
However, 15 is the first resistor, 18 is the capacitive load,
19 is a third transistor, and 20 is a second resistor. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

Bipolar logic in which the emitter of a first transistor that receives a level-shifted input signal at its base is connected to the base of a second transistor whose collector is connected to an external output terminal and whose emitter is connected to a low-potential power supply terminal. In the circuit, the base is connected to the collector of the second transistor via the first resistor, the collector is connected to the high potential power supply terminal via the second resistor, and the emitter is connected to the collector of the second transistor. A bipolar logic circuit comprising a third transistor connected to the collector of the bipolar logic circuit.