JPH01147982A - Video signal processor - Google Patents

Abstract

PURPOSE:To record a video signal with scrambling and to apply descramble at the reproduction system by constituting the video signal processing unit by an A/D converter, a separator means, a delay means, a multiplex means and a D/A converter. CONSTITUTION:A data of a picture information part of a color video signal to an input terminal 15 is extracted by a picture information part separator circuit 20 via an A/D converter 16. Only a synchronizing signal part is extracted from a synchronizing signal separator circuit 21. The picture part of the video information is fed to shift register circuits 221-227. A switch circuit 23 outputs selectively an output data of the picture information part separator circuit 20 and an output data with different delay time from each shift register for each 1H. The picture information part and the delay synchronizing signal signal part of the output data (picture information part) of the switch circuit are superimposed via switches 25, 29 and the high frequency component is eliminated via a D/A converter 30 and a low pass filter 31 and the result is given to an output terminal 32.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal processing device, and in particular, in a VTR, a video signal is scrambled by digital signal processing and then converted to an analog signal for recording. The present invention relates to a video signal processing device that performs the opposite confidence processing to perform descrambling.

In wireless and wired communications where it is not possible to restrict the number of recipients, the same problem arises in maintaining the confidentiality of communications, and encryption and secret communication devices are used as countermeasures. Similarly, V
In TR, when confidential television signals (video signals and audio signals) are recorded on magnetic tape, it is necessary to ensure that they can only be played back normally by a specific person, and if the signals are not confidential. However, there are cases where it is desired that only a specific person, such as a person who has paid money, be able to obtain a good reproduced television signal.

In such a case, there is a particular need to realize a video signal processing device that can scramble and record a video signal and descramble it in a playback system.

2. Description of the Related Art Conventionally, as a scrambling method that prevents a good reproduced image from being obtained unless descrambling is performed on the receiver side, there have been methods as shown in FIGS. 11 to 13.

As an example of a conventional video signal scrambling method, the first
As shown in FIG. 1, there is a method in which a predetermined portion of the horizontal synchronizing signal HD of the video signal is removed for a period indicated by T. The video signal shown in FIG. 11 scrambled by this conventional scrambling method will not be properly horizontally synchronized unless descrambling processing (additional processing of missing horizontal synchronization signals) is performed on the receiver side, so the displayed image will be distorted. This can make it difficult to identify what kind of image content it is.

Another example of a conventional video signal scrambling method is a method of inverting the horizontal synchronizing signal of a video signal to create HD' as shown in FIG. According to this conventional scrambling method, a normal image can be received by extracting the horizontal synchronizing signal HD' at the sampling level shown by the dashed line in FIG. However, normal television receivers that do not perform this descrambling process do not have normal horizontal synchronization, making it difficult to identify the displayed image.

As yet another example of a conventional video signal scrambling method, there is one in which the phase of the carrier color signal is changed using a configuration as shown in FIG. Publication No. 58-20088). In FIG. 13, 1 is a luminance signal (Y) input terminal, 2 is a carrier color signal (C) input terminal, 3a, 3b, 3c
4 is a phase shifter, 4 is a switch, 5 is an adder, and 6 is a synchronization signal generation circuit. The phases of the color subcarriers are phase-shifted by 360°/n by the phase shifts W3a, 3b, 3G, . The signals are sequentially switched and output every period or every n vertical scanning periods.

The adder 5 adds the synchronizing signal from the synchronizing signal generating circuit 6 and the luminance signal from the input terminal 1 to the output carrier color signal of the switch 4, respectively, and sends the added composite signal through the AM modulator 7. Send to transmission line 8.

The above transmission signal is received by the receiving system, and its AM demodulator 9
After AM demodulation, only the carrier color signal is sent to phase shifters 10a, 10b, and 10c.

The phase of the color subcarrier is shifted by 360°/n in the opposite direction to the phase shifters 3a, 3b, 3c, . . . and then supplied to the switch 11. switch 1
1 is configured to be switched in synchronization with the switch 4, and outputs the carrier color signal returned to the original phase to the output terminal 12. Incidentally, the luminance signal in the output demodulated signal of the AM demodulator 9 is separated by a discrimination means and outputted through a separate route.

If the thus obtained carrier color signal from the output terminal 12 and the luminance signal from another route are supplied to the receiver, a displayed color image can be normally obtained.

On the other hand, if the transmission signal from the transmission path 8 is directly supplied to a normal receiver, the phase of the carrier color signal will be different from the normal state, so that normal colors cannot be reproduced.

Problems to be Solved by the Invention However, all of the above-mentioned conventional scrambling methods are aimed at transmitting scrambled video signals wirelessly or by wire; for example, by recording them on a magnetic tape using a conventional VTR, V
When playing back with a TR, a predetermined signal is generated in the carrier color signal reproducing system of the VTR based on the playback horizontal synchronization signal, and the frequency of the playback low-pass converted carrier color signal is changed to the original phase of the playback carrier color signal. Since there is a conversion circuit and an AFC circuit that uses the reproduced horizontal synchronization signal to remove time axis fluctuations, the horizontal synchronization signal shown in Figures 11 and 12 may be dropped or reversed. Conventional scrambling methods have the problem that a reproduced carrier color signal cannot be obtained normally, and even if descrambling processing is applied to a reproduced video signal reproduced by an existing VTR, a normal reproduced color image cannot be obtained. .

In addition, in a VTR that separates a luminance signal and a carrier color signal from a composite color video signal, performs predetermined signal processing on both signals separately, and records them on a magnetic tape, a comb filter is used as the separation means. In the conventional scrambling method shown in FIG. 13, the scrambled video signal sent to the transmission line 8 cannot be recorded because the carrier color signal cannot be separated by the comb filter, and the Y/C Even if a VTR does not use a comb filter for separation, a VTR that uses a comb filter in the color signal reproduction system in order to remove the low frequency converted carrier color signal reproduced as crosstalk from adjacent tracks has a comb filter. 13
With respect to the reproduced carrier color signal scrambled using the conventional scrambling method shown in the figure, there is a problem in that the phase of the color subcarriers differs by 360°/n, making it impossible to remove the O stalk.

The present invention has been made in view of the above points, and is
It is an object of the present invention to provide a video signal processing device capable of recording and reproducing scrambled video signals even on an existing VTR without making any changes to R.

Means for Solving the Problems The video signal processing apparatus of the present invention comprises an A/D converter, a separating means, a delay means, a multiplexing means and a D/A converter. A/
The D converter repeats the input analog video signal at a frequency nX
A/D conversion is performed using a sampling clock of fsc (where fsc is a color subcarrier frequency and n is a natural number) and a first digital video signal is output.

The separating means separates the first digital video signal into an image information portion in a preset section and a synchronization signal portion in other sections. Further, the delay means delays the image information portions of at least two adjacent horizontal scanning periods so that the period boundary is m times the period τ of the color subcarrier of the input video signal (where m is O or a positive integer).

The multiplexing means multiplexes the output signals of the separating means and the delaying means to output a second digital video signal, and the D/A converter converts this into an analog video signal.

A second digital video signal obtained by multiplexing the image information portion delayed by the action delaying means and the synchronization signal portion taken out from the separating means by the multiplexing means,
Compared to the first digital video signal, the relative multiplexing position of the image information portion to the synchronization signal portion is different, whereas the synchronization signal portion is the same.

Therefore, the output video signal of the D/A converter can be recorded and played back using the existing VTR that records and plays back the input analog video signal. Furthermore, when the recorded video signal is reproduced and supplied to an existing television receiver, the horizontal position of the image shifts line by line, causing the picture to become distorted and displaying an image that is unsuitable for normal viewing.

Further, by supplying the output video signal of the D/A converter as an input video signal to the video signal processing device of the present invention, and causing the delay means to delay the input video signal in a direction that cancels out the delay time. , it is possible to obtain a descrambled normal video signal.

Example FIG. 1 shows a block diagram of a first embodiment of the present invention.

In this embodiment, the periods in which the color burst signals CB+ and CB2 are not present among the front porch and back porch of the horizontal synchronizing signals H8+ and H82 in the color video signal shown in FIG. 2 are unrelated to image display, and the front porch Considering that the slight video signal sections immediately before the camera and immediately after the back porch do not contribute to the actual image display of the television reception area, or are hardly noticeable at the left and right edges of the screen, one horizontal scanning period ( 1st) Color burst information @ CB in the image information section and pattern section).

A margin of approximately 4 μsec in total, including approximately 3 μsec from the next point A and approximately 1 μsec immediately before the horizontal synchronizing signal H8z, is provided, and the image information portion is shifted by a predetermined cycle within this range.

That is, in FIG. 1, the color video signal input to the input terminal 15 is supplied to the AD converter 16, where the 4×fsc (however, fsc
is the color subcarrier frequency, which is 3.57 for the NTSC system.
9545 MH2) is converted into a digital color video signal based on a clock pulse selected at a repetition frequency of 0.9545 MH2). This digital color video signal is, for example, a digital signal with a matrix bit number of 8 bits and a sampling frequency of 4 fsc, and is substantially the same as the input color video signal as shown in FIG. 3a. However, although this digital color video signal is a digital signal, for ease of understanding, it is shown as an analog signal waveform in FIG.

The input color video signal is also separated into a horizontal synchronization signal by a horizontal synchronization signal separation circuit 18 and sent to a timing generation circuit 19.
is supplied to Based on the horizontal synchronization signal and the clock pulse from the clock pulse generation circuit 17, the timing generation circuit 19 generates a period including the video period within 1H of the digital color video signal a, as shown by b in FIG. A pulse is generated which is at a high level during a period excluding the period of the synchronization signal and the color burst signal, and is at a low level during the other period within 1H, and a pulse as shown by e in FIG. 3 is generated.

The image information partial separation circuit 20 is configured to pass the digital color video signal a as is during the high level period of the pulse b, and output digital data corresponding to the pedestal level during the low level period of the pulse b. There is. Therefore, only the data of the image information part for each 1H is taken out from the image information part separation circuit 20, and the data of the signal part consisting of the color burst signal and the horizontal synchronization signal is taken out as a signal replaced with pedestal level data. It will be done.

On the other hand, the synchronizing signal partial separation circuit 21 is configured to output data corresponding to the pedestal level during the high level period of the pulse b, and to pass through and output the digital color video signal a as is during the low level period of the pulse b. There is. Therefore, from the synchronization signal separation circuit 21, as shown by C in FIG. Instead of the information part, a signal switched to the pedestal level is taken out.

In this way, the digital color video signal a is separated into image information portion data and synchronization signal portion data, of which the image information portion data is supplied to seven shift registers 221 to 227 connected in series. On the other hand, it is directly supplied to the switch circuit 23. Each of the shift registers 221 to 227 is composed of four stages having an 8-bit parallel input/output section, and by applying the 4 fsc clock pulse as a shift pulse, each of the shift registers 221 to 227 has one period τ (NTSC 0 for method
．． A delay time of 279 μsec) is added to the input data with precise accuracy and output.

The switch circuit 23 receives a total of 8 types of output data from the image information partial separation circuit 20 and each output data from the shift registers 221 to 227 in response to a 3-bit control signal from a delay amount switching control signal generation circuit 24, which will be described later. Output data with different delay times are sequentially selected and output every 1H.

Here, the switch circuit 23 always selects and outputs data that has a delay time different by ±τ or the same delay time as the data that was selected and outputted 1H ago.

The output data (image information portion) of the switch circuit 23 is supplied to one terminal of the switch circuit 25, and is supplied to the other terminal of the switch circuit 25 through a shift register 26 having a delay time τ×. The shift register 26 described above has 8-bit parallel input/output, is supplied with a clock pulse, and is configured with, for example, 22 stages so as to obtain a delay time τx of an odd multiple of 1/2 of one period of the color a1 carrier wave. has been done.

The switch circuit 25 outputs each output data of the switch circuit 23 and the shift register 26 ( image information portion) are alternately selectively output and supplied to one input terminal of the switch circuit 29.

On the other hand, the synchronization signal portion C is converted into a color burst signal C of the digital color video signal a by the shift register 28.
After the signal d is delayed by a predetermined time so that the position approximately 3 μsec ahead from the point immediately after B+, CBz substantially coincides with the end position of the color burst signals CB+', CB2', the other side of the switch circuit 29 is Supplied to the input terminal.

During the high level period of the pulse e, the switch circuit 29
The output signal of the shift register 28 is selectively outputted, and the pulse e
During the low level period, switching control is performed so that the output signal of the switch circuit 25 is selectively output. Therefore, as described above, the delay time is switched from the switch circuit 29 in increments of one period τ of the color subcarrier every 1H, and the delay time is switched by the above delay time τ x every field, so that the horizontal A digital signal in which the image information portion from the switch circuit 25 and the delayed synchronization signal portion d are multiplexed is a digital signal whose relative multiplexing position with respect to the synchronization signal is shifted by τχ every day and every field. taken out. This digital signal is converted into an analog video signal by the D/A converter 30, and then passed through a low-pass filter (LP
F) After unnecessary high frequency components are removed by 31, the signal is outputted via output terminal 32.

In the above output video signal, the starting position of the image information part within one day is 2.235 minutes from the position immediately after the color burst signal in one of the odd and even fields.
μSeC (= 0.279μ5ecX8) Within the range to a position far away on the video period side, the difference between two adjacent lines is an integral multiple of 0.279μsec, and in the other field, the above The starting position is 1.5365 from immediately after the color burst signal.
3.772μs from immediately after the color burst signal from a position μ5ec (= 0.279μ5ecx 5.5) away
It is moved in the same way as above within a range up to a position ec away.

Next, the configuration of the clock pulse generation circuit 17 will be explained. The clock pulse generation circuit 17 is configured to generate clock pulses locked to the color burst signal as shown in FIG. 4, or to generate clock pulses not locked to the color burst signal as shown in FIG. Configure it as follows.

In FIG. 4, the analog color video signal input to the input terminal 34 is passed through a band pass filter (BPF) 35 to pass a carrier color signal, and then a burst gate circuit 36 extracts a color burst signal, and then a phase comparison is made. Vessel 37
is supplied to The phase comparator 37 is a well-known PL along with a voltage controlled crystal oscillator (VXO) 38 and a 1/n frequency divider 39.
A clock pulse having a repetition frequency n-fSc (in this embodiment, n=4) is output from the VXO 38 to the output terminal 40 in phase synchronization with the color burst signal.

In addition, in the clock pulse generation circuit shown in FIG. 5, the repetition frequency n-fsc is
(in this embodiment, n=4) clock pulses are taken out and output to the output terminal 43.

Since the clock pulse generation circuit shown in FIG. 4 is phase-synchronized with the color burst signal, a stable amount of delay can be obtained in the shift registers 221 to 227, 26, and 28, but the clock pulse generation circuit shown in FIG. Even a pulse generation circuit is practical because its oscillation frequency is extremely stable, there is little error in delay amount, and it is inexpensive.

Next, the configuration of one embodiment of the delay 1 switching control signal generation circuit 24 will be described in more detail with reference to FIGS. 6 to 8. FIG. 6 is a block system diagram of one embodiment of the delay claw switching control signal generation circuit 24, in which 45a to 45d are counters, respectively, and 45a to 45d are counters, and 45a to 45d are inputted from an operation section (not shown).
The numerical value of each digit of the digit PIN number is given as preset data. Each time the counters 45a to 45d count clock pulses equal to the value of this preset data, they output a pulse to start the operation of the next stage counter.

As an example, if the password is "2735", the counters 45a, 45b, 45C, and 45d each have "l 2
Preset data of values Jj, "A", "3" and "5" are given. Next, when the reset button 46 is pressed, the counters 45a, 45b, 45C.

45d, 48, flip 70 knob 52, up/down counter 53, etc. are reset, and the switch circuit 50
A pulse is applied to the control terminal X+ of the counter 45a via the resistor R2 and the switch circuit 50 by a switching pulse applied by an integrating circuit consisting of the resistor R+ and the capacitor C1 with a slight delay from the time when the reset button 46 is pressed. This counter 45a is controlled to be in a countable state.

The output signal of the oscillator 47 is applied to a counter 48, a flip-flop 49, and a gate circuit 59. When the reset button 46 is pressed, the flip 70 knob 49 is set and the output signal of the oscillator 47 is gated from the gate circuit 59 as a clock pulse. The output begins. When this clock pulse is taken out for the number of lines of approximately one field or approximately one frame, the flip 70 knob 49 is reset by the output signal of the counter 48, and no clock pulse is taken out from the gate circuit 59 thereafter.

The above clock pulse is applied to the counters 45a to 45d, etc., but initially the counter 45a is in the operating state;
When the same number of clock pulses as the preset data "2" is counted by the counter 45a, a four-number output of a predetermined level (logic W "1") is taken out from the counter 45a, making the counter 45b ready for operation. . Therefore, the clock pulse is now counted by the counter 45b by the same number as the preset data "7°".Similarly to the above, the counter 45C counts the following three clock pulses, and the counter 45d counts the following three clock pulses. The next five pieces are counted, and the next two pieces are counted by the counter 45a]
counted.

In this way, the counters 45a to 45d sequentially and cyclically perform counting operations, and the counting outputs are supplied to the counters 45a to 45d.
From the human OR circuit 51, a signal whose logical value changes in a pattern of "2", "7", "3", and "5" is approximately 1 field or approximately 1.
It is extracted repeatedly for the number of lines (bits) in the frame.

The output signal of the OR circuit 51 is applied to the up/down switching terminal U/D of the up/down counter 53 through the flip-flop 52, and the output of the OR circuit 51 becomes "1".
The addition 81 number and the subtraction count are switched each time . This up/down counter 53 counts clock pulses from the flip-flop 49 and generates a 4-bit count signal, which is stored in a read-only memory (RO).
M) Applied as a 54 head address signal.

The ROM 54 reads out 3-bit data at the address designated by this address signal, and applies this to a 55km random access memory (RAM) for pattern storage. Each 7F address of the ROM 54 (7) is loaded in advance with data contents whose delay time (delay m) changes as shown in FIG. 7, for example, when the data is applied to the switch circuit 23. . At this time, the difference in delay amount between adjacent addresses is set to +τ, -τ, or O.

In this embodiment, when the reset button 46 is pressed, the write control t[I signal from the terminal 56 causes a delay in the RAM 55 for pattern storage, which is set to be in a write-enabled state.
As shown in the figure, changing information is stored every time one clock pulse is output. Therefore, information indicating the delay R is stored in the RAM 55 for a total of the number of clock pulses (that is, the number of lines of approximately one field or approximately one frame). Note that in FIG. 8, the numerical values indicate the counts of the up/down counter 53. Also, RAM5
5 is applied with a clock pulse through a switch circuit 57.

In this way, when the delay amount pattern is stored in the RAM 55, the control signal from the terminal 56 is used to store the delay amount in the RAM 55.
M55 is controlled to be in a readable state, and the switch circuit 57 is switched to input the horizontal synchronizing signal (HD) coming from the terminal 58 to the RAM 55. As a result, the stored information is sequentially read out from the RAM 55 in the order in which it was stored in synchronization with the horizontal synchronizing signal, and is supplied to the control terminal of the delay amount switching switch circuit 23, which is switched every 1H, as shown in FIG. The variation pattern of the delay amount as shown in is given.

In this case, if the number of data stored in the RAM 55 matches the number of lines in one frame, or by always resetting the readout location at a certain point within one field (or one frame), one field (or one frame) The image information portion always shifts in the same pattern. However, the number of data above should not be the number of lines in one frame,
If data at addresses in the RAM 55 are sequentially read out without performing the above-mentioned reset, the position of the pattern in the vertical direction on the screen changes every moment, which has a greater scrambling effect. However, in this case, it is impossible for the receiving side to determine the start timing of reading from the RAM.

Therefore, for example, during 18111 within the vertical blanking period,
This can be done on the transmitting side by storing data specifying the read address of the RAM 55, reproducing this read address specifying data every time at a predetermined location during the vertical period, and starting reading the RAM 55 based on that address. The shifting pattern can be reproduced on the receiving side, and a good reproduced image can be restored.

Inserting such data for each field ensures that even if the horizontal synchronization signal is lost at some point and the receiving side is unable to reproduce the shift pattern, the above data will be reproduced correctly from the next field. By doing so, it is possible to correct this and restore a good reproduced image again.

Next, a second embodiment of the present invention will be described with reference to the block system diagram shown in FIG. In FIG. 9, the same components as those in FIG. 1 are given the same symbols, and their explanations will be omitted. In this embodiment, the memory 6 applies the amount of delay to the image information part and switches it.
It is configured to be carried out using the 1st grade.

The memory 61 has a clock frequency of 4 fsc, and there are eight types of required delay amounts in steps of τ32 (=4X
8) step is required, and in addition to this, the delay time τ
It is sufficient to have a capacity sufficient to obtain ×. The timing generation circuit 60 generates the pulse b.

e respectively, and also supplies a write/read control signal to the memory 61. The memory 61 performs a write operation on the rising edge (or falling edge) of this control signal, and performs a reading operation on the falling edge (or rising edge) of this control signal. A write address generator 62 cyclically generates a write address for the memory 61 and supplies it to the memory 61.

On the other hand, the delay amount selector 63 selects a different delay amount for each day and each field based on the control signal from the delay Φ switching control signal generation circuit 24 and the discrimination signal from the field discrimination circuit 27. It is set and supplied to the read address generator 64. The read address generator 64 is a circuit that supplies a read address to the memory 61, and the data of adjacent 2H image information portions are delayed for a period m times the period τ, and the data of the adjacent 2H image information portions are delayed by m times the period τ, and Read addresses with different delay amounts are generated.

As an example, 1, the capacity of the memory 61 is 64 steps,
The write address generator 62 is configured with a 6-pit counter, and 6 bits from 00 to 3F are generated using the 1632 method.
Assuming that the write address is generated repeatedly and cyclically for four steps, the data of the image information portion is written into the memory 61 within, for example, a half cycle from the rise of the control signal R/W.

Next, when obtaining, for example, a delay time of 2τ within a half cycle from the fall of the control signal R/W, the stored data is read out using an address obtained by subtracting 2×4 from the write address AD as a read address. Therefore, when obtaining the delay time 2τ, the above write address AD is “
10'', the read address is “08” and A
When D is "o o", it becomes "38".

The above read address value is given by AD-(2x4)-(4xk+2) when obtaining a delay time corresponding to τx. Here, k is a natural number, and (4xk+2) is 1 of τ
Indicates a delay time that is an odd multiple of /2, for example l' 22 J
selected.

Note that the timing of the data in the image information portion read from the memory 61 is shifted from the time of writing by half a rotation m of Otsuk, so in order to match the output timing of the data in the synchronization signal portion from the shift register 28,
The clock pulse to 8 is inverted by inverter 65.

For example, the video signal processing device having the above configuration is shown in FIG.
6.69, it is used on the recording input side of an existing recording VTR 67 and the reproduction output side of an existing reproduction VTR 68.

As mentioned above, in the video signal processing devices 66 and 69, the synchronization signal part is not scrambled at all, and only the image information part is scrambled so that the horizontal position is shifted for each line, but the amount of shift is In the two lines, the period τ of the color subcarrier is m times (in the example, m is O and 1), so even if the recording VTR 67 has a Y/C separation filter, the Y/C separation can be performed normally. The scrambled video signal can be recorded on the magnetic tape in the tape cassette.

In addition, this tape cassette can be used on an existing playback VTR (VTR).
In the case of reproduction using the reproduction system) 68, a normally scrambled reproduction video signal can be similarly reproduced. If this reproduced video signal is supplied to a normal television receiver, the horizontal position of the image information part is shifted line by line as described above, so the picture is distorted and the reproduced image becomes unwatchable. be done. Furthermore, in this embodiment, the range of shifting of the image information part changes from field to field, and the difference in the amount of shifting between fields is selected to be an odd multiple of τ/2, so the phase of the color subcarrier is reversed for each field. As a result, the hue is inverted, making it possible to reproduce a reproduced video signal that is even more unsightly.

On the other hand, the above reproduced video signal is supplied to the video signal processing device 69 of this embodiment as an input video signal, and the receiver inputs the same password as the password input in the video signal processing device 66. As a result, a normal reproduced video signal with the deviation of the image information portion canceled can be outputted to the output terminal 70. However, the switch circuit 23 of the video signal processing device 69 is set so that the delay amount is switched in the opposite direction compared to that of the video signal processing device 66.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and the amount of deviation between adjacent 2Hs is not limited to within τ, and the contents of the ROM 54 shown in FIG. You can easily change the scramble pattern even if the password is the same by changing the password after the password has passed. Furthermore, the above scrambling process may be performed only on the luminance signal or only on the carrier color signal.

Effects of the Invention As described above, according to the present invention, the difference in the amount of delay for the image information portion between two adjacent lines is made m times the period of the color subcarrier (where m is 0 or a positive integer). Therefore, it is possible to record and reproduce scrambled video signals without changing the configuration of an existing VTR that has a Y/C separation port type filter or a comb filter for crosstalk removal in the reproduced carrier color signal, etc. In addition, even in VTRs that have an AFC loop that obtains a continuous wave from the color burst signal and returns the reproduced low-frequency conversion carrier color signal to its original band, at the same time removing time axis fluctuations, the synchronization signal part must be scrambled. This allows the AFC loop to operate normally, and only a specific person who knows the password can obtain a normal playback image through the video signal processing device that performs the descrambling process. Since the means and the delay means are constructed with digital circuits, the delay m
It is easy to set up, and it is possible to separate the image information part and the synchronization signal part extremely stably and accurately, and to give the required delay time to the image information part, and it is possible to scramble or descramble the video signal with a configuration that is easy to integrate into an IC and is inexpensive. It has features such as being able to perform

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of the first embodiment of the present invention, FIGS. 2 and 3 are signal waveform diagrams for explaining the operation of FIG. 1, and FIG.
5 and 5 are block system diagrams showing each of the main parts in FIG. 1, FIG. 6 is a block system diagram showing an embodiment of other main parts in FIG. 1, and FIG. 6 is an explanatory diagram of the storage data of the ROM in FIG. 6, FIG. 8 is an explanatory diagram of the storage data of the RAM in FIG. 6, and FIG. 9 is a 70-trick system diagram of the second embodiment of the present invention.
FIG. 10 is a block system diagram showing an example of use of the device of the present invention;
11 and 12 are waveform diagrams of video signals showing respective conventional scrambling methods, and FIG. 13 is a block system diagram showing another example of the conventional scrambling method. 15...Color video signal iJ terminal, 16...A/
D converter, 17... Clock pulse generation circuit, 20.
...Image information partial separation circuit, 21...Synchronization signal partial separation circuit, 221-227.26.28...Shift register, 23.25.29...Switch circuit, 24...
・Delayed signal switching control signal generation circuit, 30...D
/A converter, 32...color video signal output terminal, 61
...Memory, 62...Write address generator, 63
...Delay 8 selector, 64...Read address generator. ' Patent applicant: Victor Company of Japan, Ltd. Figure 2 Figure 3 - One hour Figure 4 Figure 5 Prisoner ROM address (decimal) Figure 8 Figure 10 Figure 11 Figure 12 Figure 13

Claims (3)

[Claims] (1) Repeat input analog video signal at frequency n×fs
c (where fsc is the color subcarrier frequency and n is a natural number)
an A/D converter that performs A/D conversion with a sampling clock and outputs a first digital video signal; and an A/D converter that outputs a first digital video signal by performing A/D conversion using a sampling clock of separation means for separating the image information portion into an image information portion of the interval and a synchronization signal portion of other intervals; m times the period τ of the color subcarrier of the input analog video signal (where m is 0
and a positive integer), and multiplexes the synchronization signal portion separated by the separation means onto the delayed image information portion from the delay means and outputs the resultant signal as a second digital video signal. A video signal processing device comprising: multiplexing means; and a D/A converter that converts the second digital video signal from the multiplexing means into an analog video signal. (2) The delay means cycles through a plurality of shift registers connected in series, input data of a first-stage shift register among the plurality of shift registers, and output data of each of the plurality of shift registers. 2. The video signal processing device according to claim 1, further comprising a switching means for switching the output every horizontal scanning period. (3) The delay means includes a memory, a write address generator that cyclically generates and outputs a write address of the image information portion to the memory, and a write address generator that cyclically generates and outputs a write address of the image information portion to the memory; 2. The video signal processing apparatus according to claim 1, further comprising a reading means for reading data with a delay of m times the period τ with respect to data read before the horizontal scanning period.