JPH01147981A - Video signal processor - Google Patents

Abstract

PURPOSE:To record a video signal with scrambling and to apply descramble at the reproduction system by using the video signal being the result of multiplexing by a multiplexing means for a picture information part delayed by a delay means and a synchronizing signal part extracted by a separator means. CONSTITUTION:A color video signal coming to an input terminal 15 is subject to horizontal synchronizing signal separation by a horizontal synchronizing signal separator circuit 21 via a clamp circuit 16, switch circuits 17, 18 and the result is fed respectively to a monostable multivibrator 22 and a field discrimination circuit 23. The picture part of the video signal from the switch 18 and fed to delay circuits 251-257 being 7 stages of cascade connection. The output signal of the switch 20 (picture information part) is fed to an adder 30 via the switch circuit 28 and multiplexed onto a signal comprising a color burst signal from a delay line 24 and a horizontal synchronizing signal and the result is outputted via an output terminal 31.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device, and more particularly to a video signal processing device capable of scrambling and recording a video signal in a VTR and descrambling it with a playback thread.

Wireless communication and wired communication in which recipients cannot be restricted have problems in maintaining the confidentiality of communication, and encryption and secret communication devices are used as countermeasures. Similarly, V
In TR, when confidential television signals (video signals and audio signals) are recorded on magnetic tape, it is necessary to ensure that they can only be played back normally by a specific person, and if the signals are not confidential. However, there are cases where it is desired that only a specific person, such as a person who has paid money, be able to obtain a good reproduced television signal.

In such a case, there is a particular need to realize a video signal processing device that can scramble and record a video signal and descramble it in a playback system.

2. Description of the Related Art Conventionally, there have been methods of scrambling processing as shown in FIGS. 8 to 10, which prevent a good reproduced image from being obtained unless descrambling processing is performed on the receiver side.

As an example of a conventional video signal scrambling method, the eighth
As shown in the figure, there is a method of removing a predetermined portion of the horizontal synchronizing signal 1-ID of the video signal for a period indicated by a square. The video signal shown in FIG. 8 scrambled by this conventional scrambling method will not be properly horizontally synchronized unless the receiver performs descrambling processing (additional processing of the missing horizontal synchronization signal), so the displayed image will not be displayed. This can make it difficult to identify what kind of image content it is.

Another example of the conventional method of scrambling a video signal is a method of inverting the horizontal synchronizing signal of the video signal to create HD' as shown in FIG. According to this conventional scrambling method, a normal image can be obtained by extracting the horizontal synchronizing signal HD' at the handling level shown by the dashed line in FIG. 9 and performing descrambling processing to replace it with a regular horizontal synchronizing signal. Although the images can be displayed on a television receiver, normal television receivers that do not perform this descrambling process do not have normal horizontal synchronization, making it difficult to identify the displayed image.

Another example of a conventional video signal scrambling method is the one shown in FIG. 10, in which the phase of the carrier color signal is changed by a single signal so that no color appears on a normal television receiver. For example, JP-A-58-20088
Publication No.). In FIG. 10, 1 is a luminance signal (Y) input terminal, 2 is a conveyance color @ (C) input terminal, 3a, 3b, 3
c is a phase shifter, 4 is a switch, 5 is an adder, and 6 is a synchronization signal generation circuit. The phases of the color subcarriers are shifted by 360'/n by the phase shifters 3a, 3b, 3c, . The output is sequentially switched and output every scanning period or every n vertical scanning periods.

The adder 5 adds a synchronizing signal from the synchronizing signal generating circuit 6 and a luminance signal from the input terminal 1 to the output carrier color signal of the switch 4, respectively, and transmits the added composite signal through the AM modulator 7. Send to Route 8.

The above transmission signal is received by the receiving system, and its AM demodulator 9
After AM demodulation, only the carrier color signal is sent to phase shifters 10a, 10b, and 10c.

. . , the phase of the color subcarrier is shifted by 360°/n in the opposite direction to the phase shifters 3a, 3b, 3c, . . . and then supplied to the switch 11.

The switch 11 is configured to switch in synchronization with the switch 4, and outputs the carrier color signal returned to its original phase to the output terminal 12. Incidentally, the luminance signal in the output demodulated signal of the AM demodulator 9 is separated by a discrimination means and outputted through a separate route.

If the thus obtained carrier color signal from the output terminal 12 and the luminance signal from another route are supplied to the receiver, a displayed color image can be normally obtained.

On the other hand, if the transmission signal from the transmission path 8 is directly supplied to a normal receiver, the phase of the carrier color signal will be different from the normal state, so that normal colors cannot be reproduced.

Problems to be Solved by the Invention However, all of the above-mentioned conventional scrambling methods are aimed at transmitting scrambled video signals wirelessly or by wire; for example, by recording them on a magnetic tape using a conventional VTR, The recording current magnetic tape is V
When playing back with a TR, a predetermined signal is generated in the carrier color signal reproducing system of the VTR based on the playback horizontal synchronization signal, and the frequency of the playback low-pass converted carrier color signal is changed to the original phase of the playback carrier color signal. Since there is a conversion circuit and an AFC circuit that uses the reproduced horizontal synchronization signal to remove time axis fluctuations, the horizontal synchronization signal shown in Figures 8 and 9 may be dropped or inverted. In the traditional scrambling method,
There is a problem in that a reproduced carrier color signal cannot be obtained normally, and even if a descrambling process is applied to a reproduced video signal reproduced by an existing VTR, a normal reproduced color image cannot be obtained.

In addition, in a VTR that separates a luminance signal and a carrier color signal from a composite color video signal, performs predetermined signal processing on both signals separately, and records them on a magnetic tape, a comb filter is used as the separation means. In the conventional scrambling method shown in FIG. 10, the scrambled video signal sent to the transmission line 8 cannot be recorded because the carrier color signal cannot be separated by the comb filter, and the Y/C Even if a VTR does not use a comb filter for separation, a VTR that uses a comb filter in the color signal reproduction system in order to remove the low frequency converted carrier color signal reproduced as crosstalk from adjacent tracks has a comb filter. 10
With respect to the reproduced carrier color signal scrambled using the conventional scrambling method shown in the figure, there is a problem in that crosstalk cannot be removed because the phases of the color subcarriers differ by 360°/n.

The present invention has been made in view of the above points, and is
It is an object of the present invention to provide a video signal processing device capable of recording and reproducing scrambled video signals even on an existing VTR without making any changes to R.

Means for Solving the Problems The video signal processing apparatus of the present invention comprises a separating means, a delay means, and a multiplexing means. The separating means separates the input video signal into an image information portion in a preset section and a synchronization signal portion in other sections every horizontal scanning period based on the horizontal synchronization signal of the input video signal.

The delay means is configured so that the image information portion of two adjacent horizontal scanning periods is m times the period τ of the color subcarrier of the input video signal (where m is O
and a positive integer). Alternatively, the delay means may be configured so that the image information portions of two adjacent fields are equal to 1 of τ.
are delayed differently by odd multiples of /2.

The multiplexing means multiplexes the output signals of the separating means and the delaying means.

The video signal obtained by multiplexing the image information portion delayed by the action delaying means and the synchronization signal portion taken out from the separation means by the multiplexing means has a high synchronization of the image information portion when compared with the input video signal. The relative multiplexing positions for the signal portions are different, whereas the synchronization signal portions are the same.

Therefore, the existing VTR that records and reproduces the input video signal
Accordingly, the output video signal of the multiplexing means can be recorded and reproduced. Furthermore, when the recorded video signal is reproduced and supplied to an existing television receiver, the horizontal position of the image shifts line by line, causing the picture to become distorted and displaying an image that is unsuitable for normal viewing.

Further, the output video signal of the multiplexing means is supplied as an input video signal to the video signal processing device of the present invention, and the delay means delays the input video signal in a direction that cancels out the delay time, thereby descrambling. It is possible to obtain a normal video signal.

Embodiment FIG. 1 shows a block system diagram of an embodiment of the present invention. In this embodiment, the periods in which the color burst signals CB+ and CB2 of the front border and back border of the horizontal synchronizing signals H8+ and H32 in the color video signal shown in FIG. Considering that the few video signal sections immediately before and after the backboard do not contribute to the screen display of the actual television receiver, or are hardly noticeable at the left and right edges of the screen, one horizontal scanning period (11 -1") image information part (picture part) color burst signal CB + A immediately after
A margin of approximately 4 μsec in total, including approximately 3 μsec from the horizontal synchronizing signal HS2 and approximately 1 μsec immediately before the horizontal synchronizing signal HS2, is provided, and the image information portion is shifted by a predetermined cycle unit within this range.

That is, in FIG. 1, the color video signal a as shown in FIG. 3, which has entered the input terminal 15, is clamped to, for example, the pedestal level by the clamp circuit 16, and then sent to the respective terminals 17b and 18a of the switch circuits 17 and 18. supplied respectively. The other terminal 17a of this switch circuit 17.18
, 18b are applied with a voltage of a predetermined level from a voltage source 19.20. Further, the above input color video signal a is supplied to a horizontal synchronization signal separation circuit 21, where the horizontal synchronization signal is separated and extracted, and then supplied to an instep stable multivibrator (mono multi) 22 and a field discrimination circuit 23, respectively. Ru.

As shown by b in FIG. 3, the monomulti 22 is at high level during the period including the video period within 1H of the color video signal a and excluding the synchronization signal and color burst signal periods, and is at high level during the period within 1H of the color video signal a. Then, a low level pulse is generated and used as a switching pulse to switch circuits 17 and 1.
8 respectively.

The switch circuits 17 and 18 are configured to selectively output the GT signal input to the terminals 17b and 18b during the period when the pulse b is at a low level, and to selectively output the input signal from the terminals 17a and 18a during the period when the pulse b is at a high level. , switch circuit 17
From there, as shown by C in FIG. 3, horizontal synchronizing signals H8+,
A signal consisting of H82 etc. and color burst signals CB+, CB2 etc. is extracted. This signal C is connected to the delay line 24, as shown in FIG.
B+' and CB2' are delayed by a time that coincides with the end position of CB2'.

On the other hand, from the switch circuit 18, the image information portion of the video period corresponding to the high level period of the switching pulse C shown in FIG. The subcarrier frequency is 3.
Since it is 579545 MHz, its period is 0.2
79 μsec) and is supplied to delay circuits 251 to 257 connected in cascade in seven stages, and directly to the switch circuit 26.

The switch circuit 26 switches between the output signal of the switch circuit 18 and the delay circuit 2 every 1H by a 3-bit control signal from a delay amount switching control signal generation circuit 27, which will be described later.
A total of eight types of output signals having different delay times among output signals 51 to 257 are sequentially selected and output. Here, the switch circuit 26 always selects and outputs a signal that has a delay time different by .tau. or the same delay time as the signal that was selected and outputted 1H before.

The output signal (image information part) of the switch circuit 26 is supplied to the terminal 28a of the switch circuit 28, while the delay time τ
The terminal 28 of the switch circuit 28 is passed through the two delay circuits of ×.
b. The delay time τ× is selected to be an odd multiple of 1/2 of one period of the color subcarrier.

The switch circuit 28 selects the input signals (image information portion) of the terminals 28a and 28b for each field based on the odd field and even field discrimination signals determined by the field discrimination circuit 23 by a known means based on the phase of the equalization pulse. Alternately select and output. In this way, the delay time is switched in increments of one period τ of the color subcarrier every day,
By switching the delay time by the above delay time τ x every field, the relative multiplexing position with respect to the horizontal synchronizing signal is changed by τ every 1H, and by x every field.
The shifted image information portion is multiplexed with the signal d consisting of the color burst signal and horizontal synchronization signal from the delay line 24 in the adder 30, and then sent to the output terminal 3.
The output is output via 1.

In the above output video signal, the starting position of the image information part within one day is 2.235 minutes from the position immediately after the color burst signal in one of the odd and even fields.
Within the range of μ5ec (= 0.279μsec x 8) to a position away from the video period side, the difference between two adjacent lines is an integral multiple of 00.279Sec, and in the other field The above starting position is 1.76 from immediately after the color burst signal.
It is moved in the same manner as above within the range from a position 5μ5ec (=4-2.235μsec) away to a position 4μsec @ immediately after the color burst signal.

Next, the configuration of one embodiment of the delay amount switching control signal generation circuit 27 will be described in more detail with reference to FIGS. 4 to 6. FIG. 4 is a block system diagram of one embodiment of the delay amount switching control signal generation circuit 27, in which 35a to 35d are counters, respectively, and 4 inputs from an operation section (not shown) are shown.
The numerical value of each digit of the digit PIN number is given as preset data. Each time the counters 35a to 35d count clock pulses equal to the value of this preset data, they output a pulse to start the operation of the next stage counter.

As an example, if the password is "2735", the counters 35a, 35b, 35c and 35d each have "2 I".
! , 11719. Preset data of values "3" and "5" is given.Next, when the reset button 36 is pressed, the counters 35a, 35b, 35c are reset.

35d, 38.7 rip 70 lub 42. The up/down counter 43 etc. are reset, and the switch circuit 40
A pulse is applied to the control terminal X+ of the counter 35a via the resistor R2 and the switch circuit 40 by a switching pulse applied by an integrating circuit consisting of the resistor R1 and the capacitor C+ with a slight delay from the time when the reset button 36 is pressed. This counter 35a is controlled to be in a countable state.

The output signal of the oscillator rA 37 is applied to the counter 38, flip-flop 39 and gate circuit 49, and when the reset button 36 is pressed, the 7 flip-flop 39 is set and the output signal of the oscillator 37 is gated from the gate circuit 49 as a clock pulse. The output begins. When this clock pulse is taken out for the number of lines of approximately one field or approximately one frame, the 7 lip-flop 39 is reset by the output signal of the counter 38, and the gate circuit 49 is reset.
No further clock pulses are taken from .

The above clock pulse is applied to the counters 35a to 35d, etc., but initially the counter 35a is in the operating state,
When the counter 35a counts the same number of clock pulses as the preset data "2", four outputs of a predetermined level (logic "1") are taken out from the counter 35a and the counter 35b is enabled to operate. Therefore, the clock pulse is now incremented by J1 by the counter 35b by the same number as the preset data "7". Thereafter, in the same manner as above, the counter 35C counts the next three clock pulses, the counter 35d counts the next five clock pulses, and the counter 35a counts the next two clock pulses by 81.

In this way, the counters 35a to 35d sequentially and cyclically perform 81 number operations, and the four-man OR circuit 41 to which the counting outputs are supplied outputs a logical value of 11211.
A signal that changes in a pattern of 7 patterns "3"5°' is repeatedly extracted by the number of lines (bits) of approximately one field or approximately one frame.

The output signal of the OR circuit 41 is applied to the up/down switching terminal U/D of the up/down counter 43 through the flip 70 knob 42, and the output of the OR circuit 41 becomes "1".
The number of added words and the dimming count are switched each time . This up/down counter 43 counts the clock pulses to generate a 4-bit count signal, which is applied as an address signal to a read only memory (ROM>44).

The ROM 44 reads 3-bit data at the address specified by this address signal and applies it to a random access memory (RAM>45) for pattern storage. 26, the delay time (delay amount) is written in advance with data contents that change as shown in Figure 5. At this time, the difference in delay nodes at adjacent addresses is +τ, -τ or Set it to 0.

In this embodiment, when the reset button 36 is pressed, the write control from the terminal 46 (the RAM 45 for pattern storage, which is enabled for writing by No. Each time one clock pulse is output, it is stored.Therefore, the RAM 45 stores information indicating the amount of delay for a total of the number of clock pulses (that is, the number of lines of approximately one field or approximately one frame). In addition, in FIG. 6, the numerical values indicate the numerical values of the up/down counter 43.
A clock pulse is applied to through the switch circuit 47.

When the delay amount pattern is stored in the RAM 45 in this way, the control signal from the terminal 46 is used to store the delay amount in the RAM 45.
M45 is controlled to be readable, and the switch circuit 47 is switched to input the horizontal synchronizing signal (HD) coming from the terminal 48 to the RAM 45. As a result, the stored information is sequentially read out from the RAM 45 in the order in which it was stored in synchronization with the horizontal synchronizing signal, and is supplied to the control terminal of the delay amount switching switch circuit 26, which is switched every 1H, as shown in FIG. Give the variation pattern of the delay ① as shown in .

In this case, if the number of data stored in the RAM 45 matches the number of lines in one frame, or by always resetting the readout location at a certain point within one field (or one frame), one field (or one frame) The image information portion always shifts in the same pattern. However, the number of data above should not be the number of lines in one frame,
If data at addresses in the RAM 45 are sequentially read out without performing the above reset, the position of the pattern in the vertical direction on the screen changes every moment, and this has a greater scrambling effect. However, in this case, it is impossible for the receiving side to determine the start timing of reading from the RAM.

Therefore, for example, during the 1H period within the vertical blanking period, the RA
Input data that specifies the read address of M45, reproduce this read address designation data every time at a predetermined location during the vertical period, and read R based on that address.
By starting AM45 reading, the shifting pattern performed on the transmitting side can be reproduced on the receiving side, and a good reproduced image can be restored.

Inserting such data for each field ensures that even if the horizontal synchronization signal is lost at some point and the receiving side is unable to reproduce the shift pattern, the above data will be reproduced correctly from the next field. By doing so, it is possible to correct this and restore a good reproduced image again.

For example, the video signal processing with the above configuration is shown in FIG.
As shown in 3, the recording input side of the recording VTR 51 and the playback VTR
It is used on the reproduction output side of 52.

As mentioned above, in the video signal processing devices 50 and 52, the synchronization signal part is not scrambled at all, and only the image information part is scrambled so that the horizontal position is shifted line by line. In the two adjacent lines, the period τ of the color subcarrier is m times (in the example, m is O and 1), so even if the recording VTR 51 has a comb filter for Y/C separation, Y/C is normally detected. It is possible to separate
The normally scrambled video signal can be recorded on the magnetic tape in the tape cassette.

In addition, this tape cassette can be used as an existing playback V-r R (
Even when the video signal is played back using the playback system (52) of a VTR, a normally scrambled playback video signal can be played back in the same way. If this reproduced video signal is supplied to a normal television receiver, the horizontal position of the image information part is shifted line by line as described above, so the picture is distorted and the reproduced image becomes unwatchable. be done. In addition, in this embodiment, the range of shifting of the image information part changes for each field.
Moreover, since the difference in the amount of shift between fields is selected to be an odd multiple of τ/2, the phase of the color subcarrier is reversed for each field, and the hue is reversed, making the reproduced image display even more unsightly. I can make you do it.

In response, the above-mentioned reproduced video signal is supplied to the video signal processing device 53 of this embodiment as a pano] video signal, and a password whose reception name is the same as the password entered in the video signal processing device 50 is input. By doing so, it is possible to output a normal reproduced video signal with the deviation of the image information part canceled to the output terminal 54. However, the switch circuit 26 of the video signal processing device 53 is set so that the delay amount is switched in the opposite direction compared to that of the video signal processing device 50.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and the deviation between adjacent 2Hs is not limited to within τ, and the contents of the ROM 44 shown in FIG. It is also possible to easily change the scrambling pattern even for the same identification number by changing the scrambling pattern after the lapse of time. Furthermore, the above scrambling process may be performed only on the luminance signal or only on the carrier color signal.

In addition, delay circuits 251 to 257.29, switch circuit 2
6.28 and delay amount switching control signal generation circuit 27
may be configured with a digital circuit, and the delay amount may be obtained through digital processing.

In this case, after the output signal of the switch circuit 18 is A/D converted by an A/D converter using a sampling clock having a repetition frequency four times as high as the color subcarrier frequency, predetermined signals are input as delay circuits 251 to 257.29, respectively. delay interval τ, τ
A shift register that obtains the
The signal is configured to be converted into an analog signal by a converter and output.

Furthermore, memories may be used instead of shift registers as the delay circuits 25+ to 257.29, and predetermined delay amounts τ and τ× may be obtained by controlling the write address and read address.

Effects of the Invention As described above, according to the present invention, the difference in the amount of delay for the image information portion between two adjacent lines is made m times the period of the color subcarrier (where m is O or a positive integer). Therefore, even if an existing VTR has a comb filter for Y/C separation and a comb filter for crosstalk removal in the reproduced carrier color signal, etc., scrambled video can be processed without changing the configuration. & signals, and also has an AFC loop that obtains a continuous wave from the color burst signal, returns the reproduced low frequency conversion carrier color signal to its original band, and at the same time removes time axis fluctuations. Since the synchronization signal part is not scrambled, the AFC loop can operate normally, and only a specific person who knows the password can obtain normal playback images through the video signal processing device that performs descrambling processing. It has features such as being able to

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of an embodiment of the present invention, FIGS. 2 and 3 are signal waveform diagrams for explaining the operation of FIG. 1, and FIG. 4 is an embodiment of the main parts in FIG. 1. FIG. 5 is an explanatory diagram of stored data in the ROM in FIG. 4, FIG. 6 is an explanatory diagram of stored data in the RAM in FIG. 4, and FIG. 7 is an example of use of the device of the present invention. 8 and 9 are waveform diagrams of video signals showing respective conventional scrambling methods, and FIG. 10 is a block system diagram showing another example of the conventional scrambling method. 15...Color video signal input terminal, 17, 18°28
... switch circuit, 21 ... horizontal synchronization signal separation circuit, 23 ... field discrimination circuit, 24 ... delay line, 251-25. ．． 29... delay circuit, 26...
... Delay amount switching switch circuit, 27... Delay amount switching control signal generation circuit, 30... Adder, 31.
...output terminal, 35a to 35d, 38...counter,
44...Read-only memory (ROM), 45.
・Random access memory (RA) for pattern storage
M). Patent applicant Victor Company of Japan Ltd. Figure 2 Figure 3 Address of time ROM (decimal) Figure 6 Figure 7 Figure 8 Figure 9

Claims (3)

[Claims] (1) separation means for separating an image information part in a preset section and a synchronization signal part in other sections for each horizontal scanning period based on a horizontal synchronization signal of an input video signal; The image information portions in two adjacent horizontal scanning periods differ by a period m times the period τ of the color subcarrier of the input video signal (where m is 0 or a positive integer). A video signal processing device comprising: a delay means for delaying the image information from the delay means; and a multiplexing means for multiplexing the separated synchronization signal portion onto the delayed image information portion from the delay means and outputting the resultant as a video signal. (2) The video signal processing apparatus according to claim 1, wherein the delay means determines a pattern of change in the delay time based on a password given from the outside. (3) Separation means for separating the image information portion of a preset section and the synchronization signal portion of other sections for each horizontal scanning period based on the horizontal synchronization signal of the input video signal; and separation by the separation means. The image information portion in two adjacent horizontal scanning periods is a period of m times the period τ of the color subcarrier of the input video signal (where m is 0 or a positive integer). a delay means for delaying the image information portions of two adjacent fields differently and for different periods of an odd multiple of 1/2 of the period τ, and delaying the image information portions from the delay means; A video signal processing device comprising: multiplexing means for multiplexing the separated synchronization signal portions and outputting the same as a video signal.