JPH0114733B2 - - Google Patents

Info

Publication number
JPH0114733B2
JPH0114733B2 JP56015174A JP1517481A JPH0114733B2 JP H0114733 B2 JPH0114733 B2 JP H0114733B2 JP 56015174 A JP56015174 A JP 56015174A JP 1517481 A JP1517481 A JP 1517481A JP H0114733 B2 JPH0114733 B2 JP H0114733B2
Authority
JP
Japan
Prior art keywords
circuit
signal
variable phase
output signal
clock pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56015174A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57129010A (en
Inventor
Masahiro Nakajima
Hiromi Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56015174A priority Critical patent/JPS57129010A/ja
Publication of JPS57129010A publication Critical patent/JPS57129010A/ja
Publication of JPH0114733B2 publication Critical patent/JPH0114733B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30—Time-delay networks

Landscapes

  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Dc Digital Transmission (AREA)
JP56015174A 1981-02-03 1981-02-03 Delay adjusting circuit of non-return-to-zero signal Granted JPS57129010A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56015174A JPS57129010A (en) 1981-02-03 1981-02-03 Delay adjusting circuit of non-return-to-zero signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56015174A JPS57129010A (en) 1981-02-03 1981-02-03 Delay adjusting circuit of non-return-to-zero signal

Publications (2)

Publication Number Publication Date
JPS57129010A JPS57129010A (en) 1982-08-10
JPH0114733B2 true JPH0114733B2 (enrdf_load_stackoverflow) 1989-03-14

Family

ID=11881440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56015174A Granted JPS57129010A (en) 1981-02-03 1981-02-03 Delay adjusting circuit of non-return-to-zero signal

Country Status (1)

Country Link
JP (1) JPS57129010A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS57129010A (en) 1982-08-10

Similar Documents

Publication Publication Date Title
US7941686B2 (en) Phase controllable multichannel signal generator having interleaved digital to analog converters
US4445215A (en) Programmable frequency ratio synchronous parallel-to-serial data converter
JP2745869B2 (ja) 可変クロック分周回路
KR890005990A (ko) 샘플 레이트 변환 시스템
JPH0773219B2 (ja) 並直列変換装置
CA2220523A1 (en) Digital phase detector employing a digitally controllable delay line
JPH0114733B2 (enrdf_load_stackoverflow)
US5680133A (en) Analog-to-digital converter
CA2195193A1 (en) Digital phase locked loop
KR100561640B1 (ko) 분주클럭발생방법
KR100212551B1 (ko) 개선된 동기 클럭 발생장치
EP0384595A3 (en) Digital phase shifter
JPH0244424B2 (enrdf_load_stackoverflow)
US5055917A (en) Output apparatus for image signals
JPH09284246A (ja) デマルチプレクサ
SU1478284A1 (ru) Синтезатор частот
JPH0756933B2 (ja) 位相調整回路
JPH0234053A (ja) 位相同期回路
JP2970296B2 (ja) データ多重化回路
JPS6331979B2 (enrdf_load_stackoverflow)
JPS63107318A (ja) 可変分周器
JPH03204251A (ja) クロック同期回路
JPH06177722A (ja) 広範囲遅延生成回路
JPS6171732A (ja) 速度変換回路
EP0851687A3 (en) Circuit for generating PAL chrominance signals