JPH0114693B2 - - Google Patents
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- Publication number
- JPH0114693B2 JPH0114693B2 JP55031053A JP3105380A JPH0114693B2 JP H0114693 B2 JPH0114693 B2 JP H0114693B2 JP 55031053 A JP55031053 A JP 55031053A JP 3105380 A JP3105380 A JP 3105380A JP H0114693 B2 JPH0114693 B2 JP H0114693B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- recess
- forming
- notch
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims 2
- 229910003460 diamond Inorganic materials 0.000 claims 1
- 239000010432 diamond Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 16
- 238000005530 etching Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特に主表面から内
部に向つて切り込んだ部分を有するシリコンの立
体的半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a three-dimensional silicon semiconductor device having a portion cut inward from a main surface.
３つ以上の端子を有する半導体装置において、
通常２つ以上の端子は半導体基体の一主表面上に
配置される。これらの端子に接続される半導体領
域を含めて半導体装置の端子間の容量は半導体装
置の性能に大きな影響を及ぼす。すなわち容量が
大きいと高周波成分を短絡することになり有効な
機能を果さなくなる。たとえばエミツタ接地型バ
イポーラ素子のベース・エミツタ容量が大きいと
入力信号が短絡され、エミツタ・コレクタ容量が
大きいと出力信号が短絡され、ベース・コレクタ
容量が大きいと出力信号が入力端子に帰還され
る。電界効果トランジスタのソース・ゲート容
量、ソース・ドレイン容量、ゲート・ドレイン容
量についても同様のことがいえる。 In a semiconductor device having three or more terminals,
Typically two or more terminals are located on one major surface of the semiconductor substrate. Capacitance between terminals of a semiconductor device including semiconductor regions connected to these terminals has a large effect on the performance of the semiconductor device. In other words, if the capacitance is large, high frequency components will be short-circuited and the device will no longer function effectively. For example, if the base-emitter capacitance of a grounded emitter bipolar element is large, the input signal will be short-circuited, if the emitter-collector capacitance is large, the output signal will be short-circuited, and if the base-collector capacitance is large, the output signal will be fed back to the input terminal. The same can be said of the source-gate capacitance, source-drain capacitance, and gate-drain capacitance of field effect transistors.
寄生する容量を減少させ高周波特性を改善させ
るため半導体の主表面から切り込んだ部分に端子
構造を形成することが提案されている。加工精度
の向上、微小寸法領域の実現、集積密度の向上、
自己整合プロセスの利用等の点から切り込み部分
側壁は主表面にほぼ垂直になることが望ましい場
合が多い。しかしながら、素子外部への接続のた
めのリード線、ボンデイングパツド等もすべて切
り込み部分内に形成することはかえつて容量を増
加させる場合も多い。たとえば低抵抗基板上に約
10μｍの高抵抗エピタキシヤル層を成長し表面か
ら深さ約3μｍの切り込み部を形成した場合、ボ
ンデイングパツドを切り込み部底面上に形成する
のと切り込み部以外の主表面上に形成するのでは
基板・ボンデイングパツド間の容量は明らかに後
者の方が小さくし易い。加工工程上も後者の方が
便利なことが多い。集積回路内の素子間の接続を
するリード線についても同様のことがいえる。 In order to reduce parasitic capacitance and improve high frequency characteristics, it has been proposed to form a terminal structure in a portion cut from the main surface of a semiconductor. Improving processing accuracy, realizing micro-dimensional areas, increasing integration density,
From the standpoint of utilizing a self-alignment process, etc., it is often desirable that the sidewalls of the cut portion be substantially perpendicular to the main surface. However, forming all lead wires, bonding pads, etc. for connection to the outside of the element within the notch often increases the capacitance. For example, on a low resistance board, approx.
When growing a 10 μm high-resistance epitaxial layer and forming a notch with a depth of approximately 3 μm from the surface, it is better to form the bonding pad on the bottom of the notch or on the main surface other than the notch.・The capacitance between bonding pads is obviously easier to reduce in the latter case. The latter is often more convenient in terms of the processing process. The same can be said of lead wires that connect elements within an integrated circuit.
このように切り込み部内から切り込み部外へ導
電性部材を配置させる場合、切り込み部側壁が主
表面に垂直ないしはアンダカツトしていると配線
の段切れを起す。 When a conductive member is disposed from inside the notch to outside the notch in this manner, if the side wall of the notch is perpendicular to or undercuts the main surface, a break in the wiring will occur.
本発明の目的は配線の段切れなしに切り込み部
内から切り込み部外へ導電性部材を延在させるの
に適した立体的半導体装置の製造方法を提供する
ことである。 An object of the present invention is to provide a method for manufacturing a three-dimensional semiconductor device suitable for extending a conductive member from inside a cutout to outside the cutout without breaking the wiring.
（111）主面のシリコン基板に対してほぼ垂直
な側壁を有する指向性ドライエツチングがPCl3
プラズマによつて実現される。エツチングガスと
してPCl3を使つたSiのプラズマエツチングに於
て、（111）基板を使いラインパターンの方向を＜
112＞に平行になるようにとると第１図ａに示さ
れるようにその断面が矩形になるようにエツチン
グされる。図中１はSi基板、２はSiエツチング用
マスクの熱酸化膜である。また＜112＞方向と垂
直になる辺（すなわち＜110＞方向）の断面は、
第１図ｂに示されるように、傾斜してエツチング
される。なお、典形的実験例のエツチングは、Si
エツチング用マスクとして熱酸化膜6000Åを使用
し、エツチング装置は、電力400Wの平行平板型
により放電が行なわれた。PCl3ガス圧は、７×
10-2 Tprr、エツチング時間は10分間位で、Siは約
2.0μｍエツチングされた。SiO2とSiとに対するエ
ツチ速度比は10倍以上と大きくSiO2は有効なマ
スクとなる。 (111) Directional dry etching with sidewalls almost perpendicular to the main silicon substrate is PCl 3
Realized by plasma. In plasma etching of Si using PCl 3 as the etching gas, a (111) substrate was used and the direction of the line pattern was
112>, it is etched so that its cross section becomes rectangular as shown in FIG. 1a. In the figure, 1 is a Si substrate, and 2 is a thermal oxide film of a mask for Si etching. Also, the cross section of the side perpendicular to the <112> direction (i.e., the <110> direction) is
It is etched obliquely as shown in FIG. 1b. Note that the etching in the typical experimental example is
A thermal oxide film of 6000 Å was used as an etching mask, and the etching device was a parallel plate type with a power of 400 W and discharge was performed. PCl 3 gas pressure is 7×
10 -2 Tprr , etching time is about 10 minutes, Si is about
2.0μm etched. The etch rate ratio of SiO 2 to Si is more than 10 times, making SiO 2 an effective mask.
次に、傾斜の向きがどちらになるかについて説
明する。 Next, the direction of the inclination will be explained.
第２図ａにマーカーが（110）のSi基板の上面
図を示す。この基板は、第２図ａのｙを中心軸と
して（111）面からx゜傾いているとする。この様
子を第２図ｂの正面図に示す。３は（111）x゜オ
フの基板、４は、基板３の（110）面方向を示す
マーカー、５は基板３内にパターンニングされた
＜112＞に平行なライン、６は（111）面である。
７はエツチ後のＡ−A′の断面で第１図ｂに相当
する。この様に、基板の傾きの方向により断面の
傾斜の方向が決定される。すなわち＜111＞軸の
射影方向にある端部側壁は垂直よりゆるやかな傾
斜を有する。傾斜する角度θは一般に主表面のオ
フ角度ｘより大きい。＜111＞軸の射影方向±約
10゜であればほぼ同様の傾向を示す。 FIG. 2a shows a top view of a Si substrate with markers (110). It is assumed that this substrate is tilted x degrees from the (111) plane with y in FIG. 2a as the central axis. This situation is shown in the front view of FIG. 2b. 3 is a (111) x degree off board, 4 is a marker indicating the direction of the (110) plane of the substrate 3, 5 is a line parallel to <112> patterned in the substrate 3, and 6 is a (111) plane It is.
7 is a cross section taken along line A-A' after etching and corresponds to FIG. 1b. In this way, the direction of inclination of the cross section is determined by the direction of inclination of the substrate. That is, the end side wall in the projection direction of the <111> axis has a gentler inclination than the vertical one. The tilt angle θ is generally larger than the off angle x of the major surface. <111> Axis projection direction ± approx.
At 10°, almost the same tendency is shown.
次に前述の性質を利用したメサ型SITの製作例
について記す。第３図はインターデイジタル型
SITの概略上面図を示すものである。８は、ゲー
トボンデイングパツド部、９は、ゲートライン
部、１０は、ソースボンデイングパツド部、１１
は、ソースラインである。第４図ａは、従来のプ
ラズマエツチングにより製作されたもので、第３
図のＢ−B′断面であり、第４図ｂは同様第３図
のＡ−A′断面で、ゲート部の長さ方向の断面で
ある。この方法では、ゲートのボンデイングパツ
ト部もエツチングされて堀り込まれた部分に形成
されている。１２はn+Si基板、１３はn-(i)型高
抵抗エピタキシヤル層、１４は熱酸化膜、１５は
ゲートp+拡散層、１６はソースn+拡散層、１７
はゲートメタル、１８はソースメタル、１９はゲ
ートライン、２０はゲートボンデイングパツド部
である。第５図ａ，ｂに本発明により得られたメ
サ型SITの断面形状を示す。図中第４図と同一番
号は対応する部分を示す。第５図ｂは、ゲート部
の長さ方向の断面で、ライン部だけがエツチング
され、ボンデイングパツド部は、エツチングされ
てない部分２０上に設けられている。端面の傾斜
部を介して切り込み部内から切り込み部外へ段切
れなく導電性部材１９，２０が延在する。 Next, we will describe an example of manufacturing a mesa-type SIT that utilizes the above-mentioned properties. Figure 3 is an interdigital type
1 shows a schematic top view of SIT. 8 is a gate bonding pad portion, 9 is a gate line portion, 10 is a source bonding pad portion, 11
is the source line. Figure 4a is a pattern produced by conventional plasma etching.
4b is a cross section taken along the line BB' in FIG. 3, and FIG. 4b is a cross section taken along the line AA' in FIG. In this method, the bonding pad portion of the gate is also formed in the etched and dug portion. 12 is an n + Si substrate, 13 is an n - (i) type high resistance epitaxial layer, 14 is a thermal oxide film, 15 is a gate p + diffusion layer, 16 is a source n + diffusion layer, 17
18 is a gate metal, 18 is a source metal, 19 is a gate line, and 20 is a gate bonding pad portion. Figures 5a and 5b show the cross-sectional shape of a mesa-type SIT obtained by the present invention. In the figure, the same numbers as in FIG. 4 indicate corresponding parts. FIG. 5b is a longitudinal cross-section of the gate part, in which only the line part is etched, and the bonding pad part is provided on the unetched part 20. The conductive members 19 and 20 extend seamlessly from the inside of the notch to the outside of the notch via the inclined portion of the end face.
前述の実験例を用いて本発明の具体的な製造方
法の例について説明する。第２図で説明したと同
様にして、基板の傾きが分つているものを使い第
２図ａに示した様に＜110＞に平行でボンデイン
グパツト部がA′側にくるようにパターニングす
る。熱酸化膜をエツチングマスクとして使い
PCl3ガス圧７×10-2 Tprr、電力400Wで10分間エツ
チングすると、第６図ａに示す様なエツチング深
さ約2.0μｍの断面形状が得られる。これは第２図
ａのＡ−A′に相当する断面で、ゲートの長さ方
向の断面である。 A specific example of the manufacturing method of the present invention will be explained using the above-mentioned experimental example. In the same manner as explained in FIG. 2, using a substrate with different inclinations, patterning is performed so that it is parallel to <110> and the bonding pad portion is on the A' side as shown in FIG. 2a. Using thermal oxide film as an etching mask
When etching is performed for 10 minutes at a PCl 3 gas pressure of 7×10 -2 Tprr and a power of 400 W, a cross-sectional shape with an etching depth of approximately 2.0 μm as shown in FIG. 6a is obtained. This is a cross section corresponding to A-A' in FIG. 2a, and is a cross section in the longitudinal direction of the gate.
次に全面酸化により6000Åの酸化膜をつける。
ゲートの底部だけを残してレジスト（OMR・
83）で側面、上面をカバーしたのが第６図ｂであ
り、２１はOMR・83である。指向性プラズマエ
ツチングによりゲート底部の酸化膜だけを除去す
る。このエツチングは例えばC3F8ガス圧0.1Tprrで
５分間エツチングする事により達成できる。レジ
ストを除去した後、ゲートにp+を拡散したのが
第６図ｃである。この後、ソースにn+を拡散し、
メタル蒸着、分離を行なえば第５図ａ，ｂの構造
が得られる。 Next, a 6000 Å thick oxide film is applied by oxidizing the entire surface.
Resist (OMR) leaving only the bottom of the gate
83) covers the side and top surfaces, as shown in Figure 6b, and 21 is OMR・83. Only the oxide film at the bottom of the gate is removed by directional plasma etching. This etching can be achieved, for example, by etching at a C 3 F 8 gas pressure of 0.1 Tprr for 5 minutes. After removing the resist, p + was diffused into the gate, as shown in Figure 6c. After this, diffuse n + into the source,
By performing metal vapor deposition and separation, the structures shown in FIGS. 5a and 5b can be obtained.
なお縦型SITについて説明したが、本発明は切
り込み部内から切り込み部外へ導電性部材を形成
する構造であれば、上記の例に限ることなく広く
応用される。 Although the vertical SIT has been described, the present invention is not limited to the above example and can be widely applied to any structure in which a conductive member is formed from inside the notch to outside the notch.
２，３の例を第７図ないし第９図に示す。基板
面方位、切り込み部の長さ方向、切り込み部内か
ら切り込み部外への取り出し方向は上記実施例と
同様である。第７図ａ，ｂに1GFETの例を示す。
ｎ型基板３０にp+型領域３１，３２を拡散ない
しイオン注入によつて形成し、中間部分を切り込
んでP+型領域３１，３２を分離する。切り込み
部底面上に絶縁膜３５を介して金属、ポリシリコ
ンないし金属シリサイド等の導電性ゲート電極３
２を設ける。p+型領域３１，３２上にも電極３
１′，３２′を設ける。電極３３，３１′３２′は垂
直な側壁を利用して自己整合させてもよい。ゲー
ト電極３３の取り出し部分を第７図ｂに示す。傾
斜面を利用してボンデイングパツト部３６へ段切
れなく接続されている。３４はゲート絶縁膜以外
の絶縁膜である。このような構造の1GFETはド
レイン電圧の変化によつて実効チヤンネル長が影
響されることが少なくすぐれた飽和型−特性
を得るのに有効である。第８図ａ，ｂはIIL型論
理ユニツトを示す。第８図ａにおいてn+型基板
４０上にn-型エピタキシヤル層４１が形成され、
ｐ型拡散領域４２，４３n+型拡散領域４５，４
６がエピタキシヤル層４１内に形成されている。
対向するｐ型領域４２，４３はそれぞれ切り込み
部に形成されており、インジエクタトランジスタ
のエミツタ、コレクタを形成している。エミツタ
電極４２′、コレクタ（制御）電極４３′はそれぞ
れ切り込み内底面上に形成され、第８図ｂに示す
ように切り込み部外へ取り出される。n+基板４
０、n-型領域４１、ｐ型領域４２、n+型領域４
５，４６が倒立型マルチコレクタインバータトラ
ンジスタを形成する。４５′，４６′は出力電極で
ある。第９図はパンチスルー型バイポーラトラン
ジスタを示す。p+型コレクタ領域５０上にp-型
コレクタ領域５１、n-型ベース領域５２、p+型
エミツタ領域５３が形成されている。n-型ベー
ス領域５２は薄く、高抵抗率でエミツタ接合コレ
クタ接合よりの空乏層で無バイアス時でもほぼ空
乏化している。このほぼ空乏化したn-型ベース
領域の電位を効果的に制御するため隣接するベー
ス電極５２′間の距離は十分短かくしてある。ベ
ース電極５２′の取り出し方は第５図ｂに示した
実施例とほぼ同様である。なお５０′，５３′はそ
れぞれコレクタ電極、エミツタ電極である。 Examples 2 and 3 are shown in FIGS. 7 to 9. The substrate surface orientation, the length direction of the notch, and the direction of extraction from the inside of the notch to the outside of the notch are the same as in the above embodiment. Figures 7a and 7b show examples of 1GFET.
P + type regions 31 and 32 are formed in an n type substrate 30 by diffusion or ion implantation, and the P + type regions 31 and 32 are separated by cutting in the middle portion. A conductive gate electrode 3 made of metal, polysilicon, metal silicide, etc. is placed on the bottom surface of the notch via an insulating film 35.
2 will be provided. Electrodes 3 are also placed on the p + type regions 31 and 32.
1' and 32' are provided. The electrodes 33, 31'32' may be self-aligned using vertical side walls. The extracted portion of the gate electrode 33 is shown in FIG. 7b. It is seamlessly connected to the bonding pad part 36 by using the inclined surface. 34 is an insulating film other than the gate insulating film. A 1GFET with such a structure is effective in obtaining excellent saturation type characteristics since the effective channel length is less affected by changes in drain voltage. Figures 8a and 8b show an IIL type logic unit. In FIG. 8a, an n - type epitaxial layer 41 is formed on an n + type substrate 40,
p-type diffusion regions 42, 43n + -type diffusion regions 45, 4
6 is formed within the epitaxial layer 41 .
Opposing p-type regions 42 and 43 are formed in cut portions, respectively, and form the emitter and collector of the injector transistor. An emitter electrode 42' and a collector (control) electrode 43' are formed on the inner bottom surface of the notch, respectively, and are taken out of the notch as shown in FIG. 8b. n + board 4
0, n - type region 41, p type region 42, n + type region 4
5 and 46 form an inverted multi-collector inverter transistor. 45' and 46' are output electrodes. FIG. 9 shows a punch-through bipolar transistor. A p − type collector region 51 , an n − type base region 52 , and a p + type emitter region 53 are formed on the p + type collector region 50 . The n - type base region 52 is thin, has high resistivity, and is a depletion layer from the emitter junction to the collector junction, and is almost depleted even when no bias is applied. In order to effectively control the potential of this nearly depleted n - type base region, the distance between adjacent base electrodes 52' is made sufficiently short. The method of taking out the base electrode 52' is almost the same as the embodiment shown in FIG. 5b. Note that 50' and 53' are a collector electrode and an emitter electrode, respectively.
第１図ａ，ｂはPCl3プラズマエツチングの特
徴を説明するための（111）シリコン基板の概略
断面図、第２図ａ，ｂは第１図ａ，ｂの断面形状
とシリコン基板の方位との関係を示す概略上面図
と概略断面図、第３図はインターデジタル型電極
の概略上面図、第４図ａ，ｂは従来技術による半
導体装置の概略断面図、第５図ａ，ｂは本発明の
実施例による半導体装置の概略断面図、第６図
ａ，ｂ，ｃは第５図ａ，ｂの実施例の製造工程を
示す概略断面図、第７図ａ，ｂは本発明の他の実
施例を示す概略断面図、第８図ａ，ｂは本発明の
他の実施例を示す概略断面図と概略上面図、第９
図はさらに他の実施例を示す概略断面図である。
Figures 1a and b are schematic cross-sectional views of a (111) silicon substrate for explaining the characteristics of PCl 3 plasma etching, and Figures 2a and b are the cross-sectional shapes of Figures 1a and b and the orientation of the silicon substrate. 3 is a schematic top view of an interdigital electrode, FIGS. 4a and 4b are schematic sectional views of a semiconductor device according to the prior art, and FIGS. A schematic sectional view of a semiconductor device according to an embodiment of the invention, FIGS. 6a, b, and c are schematic sectional views showing the manufacturing process of the embodiment of FIGS. 8a and b are a schematic sectional view and a schematic top view showing another embodiment of the present invention, and FIG. 9 is a schematic sectional view showing another embodiment of the present invention.
The figure is a schematic sectional view showing still another embodiment.
Claims (1)
の（111）面に対する角度が±10゜以内にある面を
表面とするウエハ上において、少なく共４つの長
辺を＜112＞方向、短辺を＜110＞方向とするマス
クパターンを形成する第１の工程と、前記マスク
パターンの長辺に沿つて、前記表面と垂直な側壁
を有し、かつ、前記マスクパターンの一方の短辺
に沿つて、前記表面と鈍角をなす平坦な側壁を有
する凹部をPCl3ガス使用の平行平板型プラズマ
エツチングにより形成する第２の工程と、前記凹
部内に制御電極を形成する第３の工程と、前記表
面と鈍角をなす側壁を介し前記凹部内の制御電極
から切り込んでない表面上のボンデイングパツド
部上に向つて延在する導電性電極を形成する第４
の工程とを少なくとも含む立体的半導体装置の製
造方法。1. On a wafer whose surface is a plane with an angle within ±10° to the (111) plane of a semiconductor single crystal having a diamond crystal structure, at least four long sides are in the <112> direction and the short sides are in the <110> direction. a first step of forming a mask pattern having a side wall perpendicular to the surface along the long side of the mask pattern, and a side wall perpendicular to the surface along one short side of the mask pattern; a second step of forming a recess with a flat side wall forming an obtuse angle with the surface by parallel plate plasma etching using PCl 3 gas; a third step of forming a control electrode in the recess; a fourth conductive electrode extending from the control electrode in the recess through the sidewall of the recess and onto the bonding pad portion on the uncut surface;
A method for manufacturing a three-dimensional semiconductor device, comprising at least the steps of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3105380A JPS56126919A (en) | 1980-03-11 | 1980-03-11 | Three-dimensional semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3105380A JPS56126919A (en) | 1980-03-11 | 1980-03-11 | Three-dimensional semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56126919A JPS56126919A (en) | 1981-10-05 |
| JPH0114693B2 true JPH0114693B2 (en) | 1989-03-14 |
Family
ID=12320732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3105380A Granted JPS56126919A (en) | 1980-03-11 | 1980-03-11 | Three-dimensional semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56126919A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100404220B1 (en) * | 1996-03-22 | 2004-01-13 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device using tilt etching process |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52119859A (en) * | 1976-04-02 | 1977-10-07 | Hitachi Ltd | Electrode constitution of semi-conductor device |
-
1980
- 1980-03-11 JP JP3105380A patent/JPS56126919A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52119859A (en) * | 1976-04-02 | 1977-10-07 | Hitachi Ltd | Electrode constitution of semi-conductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56126919A (en) | 1981-10-05 |
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