JPH01146361A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01146361A JPH01146361A JP30530287A JP30530287A JPH01146361A JP H01146361 A JPH01146361 A JP H01146361A JP 30530287 A JP30530287 A JP 30530287A JP 30530287 A JP30530287 A JP 30530287A JP H01146361 A JPH01146361 A JP H01146361A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating substrate
- crystal
- silicide layer
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000013078 crystal Substances 0.000 claims abstract description 43
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 38
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 18
- 239000010980 sapphire Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 229910052596 spinel Inorganic materials 0.000 claims abstract description 6
- 239000011029 spinel Substances 0.000 claims abstract description 6
- 238000000605 extraction Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052593 corundum Inorganic materials 0.000 abstract description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract description 5
- 229910018999 CoSi2 Inorganic materials 0.000 abstract description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 abstract 4
- 239000000395 magnesium oxide Substances 0.000 abstract 2
- 229910012990 NiSi2 Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- 239000012212 insulator Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- 239000012495 reaction gas Substances 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- BYFGZMCJNACEKR-UHFFFAOYSA-N aluminium(i) oxide Chemical compound [Al]O[Al] BYFGZMCJNACEKR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は５ｏＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎ５ｕｌａ
ｔｏｒ）構造の半導体装置に関し。[Detailed Description of the Invention] [Summary] The present invention is based on 5oI (Silicon On In5ula).
(tor) structure semiconductor device.
絶縁基体とＳｉ活性層との格子不整合に起因する結晶欠
陥の発生を抑止し、デバイスの高集積化。Suppresses the occurrence of crystal defects caused by lattice mismatch between the insulating substrate and the Si active layer, resulting in higher integration of devices.
高速化を目的とし、。Aimed at speeding up.
素子形成層と絶縁基体と、それらの間に挿入されたシリ
サイド層とを有する構成、あるいは素子形成層と絶縁基
体と、それらの間に交互に積層された。各１層以上のシ
リサイド層とシリコン層からなる多層構造とを有する構
成とする。The structure includes an element forming layer, an insulating substrate, and a silicide layer inserted between them, or an element forming layer and an insulating substrate are alternately laminated between them. The structure has a multilayer structure each consisting of one or more silicide layers and a silicon layer.
本発明はｓｏｒ構造の半導体装置に関する。 The present invention relates to a semiconductor device having a sor structure.
ＳＯ５（Ｓｉｌｉｃｏｎ Ｏｎ ５ａｐｐｈｉｒｅ）や
、 Ｓｉ基板上に形成されたマグネシャスピネル（Ｍｇ
Ｏ・ＡｌｚＯ＋）に代表される絶縁物上のＳｉ構造（Ｓ
ＯＴ）の半導体装置は次のような多くの優れた特徴があ
り、注目されている。SO5 (Silicon On 5apphire) and magnetic spinel (Mg) formed on a Si substrate.
Si structure (S
OT) semiconductor devices have many excellent features, such as the following, and are attracting attention.
■ 基板容量が小さく、高速化がはかれる。■Small board capacitance, allowing for faster speeds.
■ 高耐圧化がはかれる。■ High voltage resistance is possible.
■ 耐放射線強化がはかれる。■ Enhanced radiation resistance.
■ ランチアンプがなく、誤動作しない。■ No launch amplifier, no malfunctions.
ＳＯＳ構造は最も古くから開発され、技術的に一番進歩
したＳＯＩ構造であり、 ＭＯ３型トランジスタとして
一部実用化されている。The SOS structure has been developed for the longest time, is the most technologically advanced SOI structure, and has been partially put into practical use as MO3 type transistors.
し−かしながらサファイア結晶とＳｉ結晶との格子不整
合は約５．６％あり、このために発生する多数の結晶欠
陥によりバイポーラトランジスタへの適用は未だなされ
ていない。However, the lattice mismatch between the sapphire crystal and the Si crystal is approximately 5.6%, and due to the large number of crystal defects that occur due to this, it has not yet been applied to bipolar transistors.
特に、縦型バイポーラトランジスタに応用する場合、
Ｓｉ活性層のサファイア基板との界面側にコレクタ抵抗
を減らすために高濃度不純物ＳｉＮを最低数μｍの膜厚
で導入しなければならない。Especially when applied to vertical bipolar transistors,
In order to reduce collector resistance on the interface side of the Si active layer with the sapphire substrate, high concentration impurity SiN must be introduced to a thickness of at least several μm.
しかしながら、 Ｓｉ層の膜厚を厚くすると微細な素子
間分離が困難となり、デバイスの高集積化。However, increasing the thickness of the Si layer makes it difficult to achieve fine isolation between elements, which leads to higher integration of devices.
高速化をはかる上で問題となる。This poses a problem when trying to increase speed.
上記のように、サファイア結晶とＳｉ結晶との格子不整
合は約５．６％であるが、さらに、格子不整合の緩和を
はかったスピネル結晶を用いたＳＯ■構造でＭｇＯ・Ａ
ｌ２Ｏ３結晶とＳｉ結晶との格子不整合はＳｉの３格子
とＭｇＯ・ＡｈＯｚの２格子との間で約０．８％である
。As mentioned above, the lattice mismatch between the sapphire crystal and the Si crystal is approximately 5.6%, but in addition, the MgO・A
The lattice mismatch between the 12O3 crystal and the Si crystal is about 0.8% between the 3-lattice of Si and the 2-lattice of MgO.AhOz.
このような、絶縁体とＳｉ結晶との格子不整合に起因す
る結晶欠陥は素子性能に悪影響を与えるため、集積回路
用の材料としてさらに薄膜で、高品位の結晶を得る技術
が望まれている。Crystal defects such as these caused by lattice mismatch between the insulator and the Si crystal have a negative impact on device performance, so there is a need for technology to obtain thinner, higher-quality crystals as materials for integrated circuits. .
本発明は、薄膜で、高品位のＳＯ■結晶を得て。The present invention obtains high-quality SO* crystals in thin films.
これを用いてバイポーラトランジスタの低コレクタ抵抗
化、高集積化、高速化を目的とする。The aim is to use this to lower the collector resistance, increase the integration density, and increase the speed of bipolar transistors.
上記問題点の解決は、素子形成層と絶縁基体と５それら
の間に挿入されたシリサイド層とを有する半導体装置、
あるいは素子形成層と絶縁基体と。The solution to the above problem is to provide a semiconductor device having an element formation layer, an insulating substrate, and a silicide layer inserted between them.
Or an element forming layer and an insulating base.
それらの間に交互に積層された。各１層以上のシリサイ
ド層とシリコン層からなる多層構造とを有する半導体装
置により達成される。Laminated alternately between them. This is achieved by a semiconductor device having a multilayer structure each consisting of one or more silicide layers and a silicon layer.
前記の絶縁基体にサファイア基板、もしくは半導体基板
上に形成されたマグネシャスピネル結晶を、前記シリサ
イド層はＮ１５Ｉｚ ＋ もしくはＣｏ５１ｚを用い
ると結晶欠陥の少ない高品質のＳＯＴ構造が得られる。When a sapphire substrate or a magnetic spinel crystal formed on a semiconductor substrate is used as the insulating substrate, and N15Iz + or Co51z is used as the silicide layer, a high-quality SOT structure with few crystal defects can be obtained.
また、バイポーラトランジスタにおいては前記シリサイ
ド層、あるいは多層構造をコレクタ引き出し層に使用す
れば、薄膜で低コレクタ抵抗が実現でき、素子の微細化
が可能となる。Furthermore, in a bipolar transistor, if the silicide layer or multilayer structure is used as a collector lead-out layer, a thin film can realize low collector resistance, and the device can be miniaturized.
本発明者により最近開発されたシリサイド気相成長法に
より、絶縁体上にＮｉＳｉ、やＣｏ５１ｚ等のシリサイ
ド結晶をエピタキシャル成長できるようになった。By the silicide vapor phase growth method recently developed by the present inventor, it has become possible to epitaxially grow silicide crystals such as NiSi and Co51z on an insulator.
本発明はこの技術を用いて、絶縁体上にシリサイド結晶
、あるいはシリサイド結晶／Ｓｉ結晶の多層構造を形成
し、この上にＳｉ活性層を成長したものである。The present invention uses this technique to form a silicide crystal or a multilayer structure of silicide crystal/Si crystal on an insulator, and then grows a Si active layer thereon.
次に、これらの中間バッファ層の機能を説明する。Next, the functions of these intermediate buffer layers will be explained.
（１） シリサイド結晶
（ａｌ ＳＯＳ構造：
格子定数はＣｏＳ ｉ ２が５．３６人、 Ｎ１５ｉｚ
が５．４１人でいずれもＳｉに比し小さく９例えばＣｏ
Ｓ ｉ ｚはサファイアとの格子不整合は４．１％で、
Ｓｉ／サファイア□間の５．６％に比し約３０％整合
性が向上する。第５↓
図のＸ線回折パターンより分かように、 Ｃｏ５１ｚ／
サファイア結晶の方がＳｉ／サファイア結晶より半値幅
が小さく、結晶性が改善されている。(1) Silicide crystal (al SOS structure: lattice constant is 5.36 for CoS i 2, N15iz
is 5.41 people, both of which are smaller than Si.9 For example, Co
The lattice mismatch of S i z with sapphire is 4.1%,
The consistency is improved by about 30% compared to 5.6% between Si/sapphire□. As can be seen from the X-ray diffraction pattern in Figure 5↓, Co51z/
The sapphire crystal has a smaller half width than the Si/sapphire crystal and has improved crystallinity.
（ｂｌスピネル結晶を用いたＳｏｌ構造：Ｓｉ結晶／Ｍ
ｇＯ・Ａｌ２Ｏ３結晶の格子不整合はＳｉの３ 格子ト
ＭｇＯ・Ａｌ２Ｏ，（７） ２格子トノ間で約＋０．８
％であるが、 Ｃｏ５１ｚ結晶／ ＭｇＯ・Ａｌｚ（ｈ
結晶の格子不整合は約−０，５％であり、約４０％整合
性が向上する。(Sol structure using bl spinel crystal: Si crystal/M
The lattice mismatch of gO.Al2O3 crystal is approximately +0.8 between the 3 lattice of Si and the 2 lattice of MgO.Al2O, (7).
%, but Co51z crystal/MgO・Alz(h
The crystal lattice mismatch is about -0.5%, and the matching is improved by about 40%.
（２） シリサイド結晶／Ｓｉ結晶の多層構造さらに
、格子不整合による結晶欠陥を抑止する方法として、相
似する構造を持つ結晶を交互に成長して超格子構造とす
ることは知られている。(2) Multilayer structure of silicide crystal/Si crystal Furthermore, as a method of suppressing crystal defects due to lattice mismatch, it is known to alternately grow crystals with similar structures to form a superlattice structure.
本発明は前記成長技術を用いて、絶縁体上に各層の厚さ
が数１０〜数１００人のシリサイド結晶とＳｉ結晶を交
互に成長し、厚さ０．１〜１μｍの多層構造を形成し、
この上にＳｉ素子形成層を成長することにより、それぞ
れの界面で結晶欠陥を横方向に発散させるか、ループ状
に閉じ込めるようにしたものである。The present invention uses the above-mentioned growth technique to alternately grow silicide crystals and Si crystals, each layer having a thickness of several tens to several hundreds, on an insulator to form a multilayer structure with a thickness of 0.1 to 1 μm. ,
By growing a Si element forming layer on top of this, crystal defects are made to diverge laterally at each interface or are confined in a loop shape.
この場合、 ＮｉＳｉ、とＳｉ、およびＣｏ５１ｚとＳ
ｔの格子不整合はそれぞれ約０．４％と１．３％である
。In this case, NiSi, and Si, and Co51z and S
The lattice mismatches of t are approximately 0.4% and 1.3%, respectively.
第１図は第１の発明の一実施例を説明するバイポーラト
ランジスタの模式断面図である。FIG. 1 is a schematic cross-sectional view of a bipolar transistor illustrating an embodiment of the first invention.
図において、ｌはサファイア基板、２′はＮ１５ｉｚ、
Ｃｏ５１ｚ等のシリサイド層、３はＳｉ活性層でコレク
タ領域、４はベース領域、５はエミッタ領域、６はコレ
クタコンタクト領域、７は５ｉ０２素子分離領域である
。In the figure, l is a sapphire substrate, 2' is N15iz,
A silicide layer such as Co51z, 3 is a Si active layer and a collector region, 4 is a base region, 5 is an emitter region, 6 is a collector contact region, and 7 is a 5i02 element isolation region.
製造工程の概略は次のようである。The outline of the manufacturing process is as follows.
前記のシリサイド成長法を用いて。using the silicide growth method described above.
面指数（１０１２）のサファイア基板上に厚さ約０．７
μｍで面指数（１００）のＣｏＳｉ２結晶をエピタキシ
ャル成長する。Approximately 0.7 thick on a sapphire substrate with a plane index of (1012)
A CoSi2 crystal with a surface index (100) in μm is epitaxially grown.
Ｃｏ５１ｚのエピタキシャル成長条件は次のようである
。The epitaxial growth conditions for Co51z are as follows.
■ 基板： （ｆｏ１２）のサファイア基板■ 原料
ガス： ５ｉＣ１ａ、 Ｈｅバブル流量（２０℃）１０
ｃｃ ／分。■ Substrate: (FO12) sapphire substrate ■ Raw material gas: 5iC1a, He bubble flow rate (20℃) 10
cc/min.
■ 固体原料： ＣｏＣ１ｚ、保持温度７００℃。■ Solid raw material: CoC1z, holding temperature 700°C.
キャリア（Ｈｅ）流量５１／分。Carrier (He) flow rate 51/min.
■ 成長温度：８８０℃。■ Growth temperature: 880℃.
■ 反応ガス： Ｈｚ／Ｈｅ、混合比２０％。■ Reaction gas: Hz/He, mixing ratio 20%.
■ 成長速度：５００人／分。■ Growth rate: 500 people/min.
この後は通常の工程によりＳｉ活性層３を成長しく成長
温度９００〜１０００℃）、素子形成を行う。Thereafter, the Si active layer 3 is grown by a normal process (at a growth temperature of 900 to 1000 DEG C.), and the device is formed.
第２図は第１の発明の他の実施例を説明するバイポーラ
トランジスタの模式断面図である。FIG. 2 is a schematic cross-sectional view of a bipolar transistor illustrating another embodiment of the first invention.
図において、１１はＳｉ基板、１１′はＮ１５ｉｚ、Ｃ
ｏ５１ｚ等の基板側シリサイド層、１２は５ｉ０２層、
１３はＭｇ０−Ａｌ２Ｏ３層、２′はＮ１５ｉｚ、Ｃ０
５ｉｚ等の活性層側シリサイド層でコレクタ引き出し層
、３はＳｉ活性層でコレクタ領域、４はベース領域、５
はエミッタ領域、６はコレクタコンタクｊ−領域、７は
５ｉＯ１素子分離領域である。In the figure, 11 is a Si substrate, 11' is N15iz, C
Substrate side silicide layer such as o51z, 12 is 5i02 layer,
13 is Mg0-Al2O3 layer, 2' is N15iz, C0
A silicide layer on the active layer side such as 5iz is a collector extraction layer, 3 is a Si active layer and is a collector region, 4 is a base region, 5
is an emitter region, 6 is a collector contact j-region, and 7 is a 5iO1 element isolation region.
製造工程の概略は次のようである。The outline of the manufacturing process is as follows.
■ Ｓｉ基板上にＣｏ５１ｚ ｆｉｌｌ ’をエピタキ
シャル成長。（反応ガスはＳｉＣｌ２−ＣｏＣＩｚ−Ｈ
ｚ／ｌｌｅ系、成長温度８００〜１０００℃）
■ 本発明者が既、に開発した絶縁物気相エピタキシャ
ル成長法を用いて、厚さ０．２μｍのＭｇＯ・ＡｌｚＯ
：＋ ７１１３のエピタキシャル成長。■ Epitaxial growth of Co51z fill' on Si substrate. (The reaction gas is SiCl2-CoCIz-H
(z/lle system, growth temperature 800 to 1000°C) ■ MgO/AlzO with a thickness of 0.2 μm was grown using the insulator vapor phase epitaxial growth method that the present inventor had already developed.
:+ Epitaxial growth of 7113.
（反応ガスはＭｇＣｌ ｚ−ＡＩＣｈ−Ｃ（ｈ−Ｈｚ系
、成長温度９００〜１０００℃）
■ ウェット酸化（酸化温度１０００℃）。(The reaction gas is MgCl z-AICh-C (h-Hz system, growth temperature 900 to 1000°C). ■ Wet oxidation (oxidation temperature 1000°C).
ＭｇＯ・Ａｌ２Ｏ３層１３を通して、下層のＣｏＣ１，
層１１′の一部を酸化することにより厚さ約１μｍのＳ
ｉＯ□層１２全１２する。Through the MgO・Al2O3 layer 13, the lower layer CoC1,
By oxidizing a part of the layer 11', a layer of S with a thickness of about 1 μm is formed.
iO□ layer 12 total 12.
この層は、ウェハの反りを緩和し、高耐圧化がはかれる
役目を持つ。This layer has the role of reducing warping of the wafer and increasing the withstand voltage.
■ 活性層側シリサイド層（コレクタ引き出し層）とし
て厚さ０．７μｍのＣｏ５１ｚ層２′を成長。■ A Co51z layer 2' with a thickness of 0.7 μm was grown as a silicide layer on the active layer side (collector extraction layer).
（成長温度８ＯＯ〜１０００℃） この後は通常の工程によりＳｉ活性層３を成長し。(Growth temperature 8OO~1000℃) After this, a Si active layer 3 is grown using a normal process.
素子形成を行う、。Perform element formation.
第３図は第２の発明の一実施例を説明するバイポーラト
ランジスタの模式断面図である。FIG. 3 is a schematic cross-sectional view of a bipolar transistor illustrating an embodiment of the second invention.
図において、１はサファイア基板、２は多層構造でコレ
クタ引き出し層、 ２ＡはのＮ１５ｉｚ、Ｃｏ５１ｚ等
のシリサイド層、 ２ＢはＳｉ層、３はＳｉ活性層でコ
レクタ領域、４はベース領域、５はエミッタ領域。In the figure, 1 is a sapphire substrate, 2 is a multilayered collector extraction layer, 2A is a silicide layer such as N15iz, Co51z, etc., 2B is a Si layer, 3 is a Si active layer and is a collector region, 4 is a base region, and 5 is an emitter. region.
６はコレクタコンタクト領域、７は５ｉｎ２素子分離領
域である。6 is a collector contact region, and 7 is a 5in2 element isolation region.
第４図は第２の発明の他の実施例を説明するバ・イポー
ラトランジスタの模式断面図である。FIG. 4 is a schematic cross-sectional view of a bipolar transistor illustrating another embodiment of the second invention.
図において、１１はＳｉ基板、１２はＳｉＯ□層、１３
はＭｇ０−Ａｌ２Ｏ３層、２は多層構造でコレクタ引き
出し層、 ２ＡはＮ１５ｉｚ、Ｃｏ５１ｚ等のシリサイ
ド層、 ２ＢはＳｉ層、３はＳｉ活性層でコレクタ領域
、４はベース領域、５はエミッタ領域、６はコレクタコ
ンタクト領域、７は５ｉ０２素子分離領域である。In the figure, 11 is a Si substrate, 12 is a SiO□ layer, and 13 is a SiO□ layer.
is a Mg0-Al2O3 layer, 2 is a multilayered collector extraction layer, 2A is a silicide layer such as N15iz, Co51z, etc., 2B is a Si layer, 3 is a Si active layer and is a collector region, 4 is a base region, 5 is an emitter region, 6 7 is a collector contact region, and 7 is a 5i02 element isolation region.
第３図、第４図のシリサイド／Ｓｉ多層構造は作用の欄
で説明した諸元を用いる。The silicide/Si multilayer structure shown in FIGS. 3 and 4 uses the specifications explained in the section of operation.
第１図〜第４図のシリサイド層、またはシリサイド／Ｓ
ｉ多層構造は低抵抗（抵抗率ρ＝ ２Ｘ１０−５Ωｃｍ
）であり、厚さ０．１〜１μｍの薄膜で十分コレクタ抵
抗を下げることができる。Silicide layer or silicide/S in Figures 1 to 4
i Multilayer structure has low resistance (resistivity ρ = 2X10-5Ωcm
), and a thin film with a thickness of 0.1 to 1 μm can sufficiently lower the collector resistance.
このように、基板と活性層間にシリサイド層。In this way, a silicide layer between the substrate and the active layer.
またはシリサイド／Ｓｉ多層構造の導入により、その上
のＳｉ活性層は薄膜で高品位の結晶を得ることができる
ため、微小な素子間分離が可能となり。Alternatively, by introducing a silicide/Si multilayer structure, the Si active layer thereon can be formed into a thin film with high quality crystals, making it possible to achieve minute isolation between elements.
素子寸法を大幅に小さくでき、高集積化、高速化が達成
できる。The device dimensions can be significantly reduced, and higher integration and higher speeds can be achieved.
以上説明したように本発明によれば、 ＳＯＩ構造にお
いて、絶縁基体とＳｉ活性層との格子不整合に起因する
結晶欠陥の発生を抑止し、 Ｓｉ活性層は薄膜で高品位
の結晶を得ることができ、デバイスの高集積化、高速化
が達成できる。As explained above, according to the present invention, it is possible to suppress the occurrence of crystal defects due to lattice mismatch between an insulating substrate and a Si active layer in an SOI structure, and to obtain high-quality crystals in a thin Si active layer. This makes it possible to achieve higher integration and higher speed devices.
第１図は第１の発明の一実施例を説明するバイポーラト
ランジスタの模式断面図。
第２図は第１の発明の他の実施例を説明するバイポーラ
トランジスタの模式断面図。
第３図は第２の発明の一実施例を説明するバイポーラト
ランジスタの模式断面図。
第４図は第２の発明の他の実施例を説明するバイポーラ
トランジスタの模式断面図。
第５図（１１，（２１はＳｉ／サファイア結晶とＣｏ５
１ｚ／サフアイア結晶のＸ線回折パターンである。
図において。
１はサファイア基板。
２は多層構造でコレクタ引き出し層。
２八はＮ１５ｉｚ、Ｃｏ５１ｚ等のシリサイド層。
２ＢはＳｉｌ’ｉ１
２′はＮ１５ｉｚ、Ｃｏ５１ｚ等のシリサイド層。
３はＳｉ活性層でコレクタ領域。
４はベース令頁域。
５はエミッタ領域。
６はコレクタコンタクト領域。
７はＳｉＯ□素子分離領域。
１１はＳｉ基）反。
１１’はＮ１５ｉｚ、ＣｏＳｉ２等の基板側シリサイド
層。
１２はＳｉＯ□層。
’ １３は？ＩｇＯ・へ１２０３層である。FIG. 1 is a schematic cross-sectional view of a bipolar transistor illustrating an embodiment of the first invention. FIG. 2 is a schematic cross-sectional view of a bipolar transistor explaining another embodiment of the first invention. FIG. 3 is a schematic cross-sectional view of a bipolar transistor illustrating an embodiment of the second invention. FIG. 4 is a schematic cross-sectional view of a bipolar transistor explaining another embodiment of the second invention. Figure 5 (11, (21 is Si/sapphire crystal and Co5
1z/X-ray diffraction pattern of sapphire crystal. In fig. 1 is a sapphire substrate. 2 has a multi-layer structure with a collector pull-out layer. 28 is a silicide layer such as N15iz or Co51z. 2B is Sil'i1, and 2' is a silicide layer such as N15iz or Co51z. 3 is a Si active layer and a collector region. 4 is the base page area. 5 is the emitter area. 6 is a collector contact area. 7 is a SiO□ element isolation region. 11 is a Si group). 11' is a substrate side silicide layer such as N15iz or CoSi2. 12 is a SiO□ layer. 'What about 13? There are 1203 layers of IgO.
Claims (6)
たシリサイド層とを有することを特徴とする半導体装置
。(1) A semiconductor device comprising an element formation layer, an insulating substrate, and a silicide layer inserted between them.
層された、各１層以上のシリサイド層とシリコン層から
なる多層構造とを有することを特徴とする半導体装置。(2) A semiconductor device characterized by having a multilayer structure consisting of an element forming layer, an insulating substrate, and one or more silicide layers and silicon layers alternately stacked between them.
体基板上に形成されたマグネシャスピネル（ＭｇＯ・Ａ
ｌ＿２Ｏ＿３）結晶であり、前記シリサイド層はＮｉＳ
ｉ＿２、もしくはＣｏＳｉ＿２であることを特徴とする
特許請求の範囲第１項記載の半導体装置。(3) The insulating substrate is a sapphire substrate or a magnetic spinel (MgO・A) formed on a semiconductor substrate.
l_2O_3) crystal, and the silicide layer is NiS
The semiconductor device according to claim 1, characterized in that the semiconductor device is i_2 or CoSi_2.
とを特徴とする特許請求の範囲第１項記載の半導体装置
。(4) The semiconductor device according to claim 1, wherein the silicide layer is a collector extraction layer.
体基板上に形成されたマグネシャスピネル（ＭｇＯ・Ａ
ｌ＿２Ｏ＿３）結晶であり、前記シリサイド層はＮｉＳ
ｉ＿２、もしくはＣｏＳｉ＿２であることを特徴とする
特許請求の範囲第２項記載の半導体装置。(5) The insulating substrate is a sapphire substrate or a magnetic spinel (MgO・A) formed on a semiconductor substrate.
l_2O_3) crystal, and the silicide layer is NiS
The semiconductor device according to claim 2, characterized in that the semiconductor device is i_2 or CoSi_2.
特徴とする特許請求の範囲第２項記載の半導体装置。(6) The semiconductor device according to claim 2, wherein the multilayer structure is a collector extraction layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30530287A JPH01146361A (en) | 1987-12-02 | 1987-12-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30530287A JPH01146361A (en) | 1987-12-02 | 1987-12-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01146361A true JPH01146361A (en) | 1989-06-08 |
Family
ID=17943465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30530287A Pending JPH01146361A (en) | 1987-12-02 | 1987-12-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01146361A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1794806A2 (en) * | 2004-09-21 | 2007-06-13 | International Business Machines Corporation | METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY |
| US8169749B2 (en) | 2007-05-22 | 2012-05-01 | Hitachi Global Storage Technologies, Netherlands B.V. | Post-assembly head/disk offset adjuster |
-
1987
- 1987-12-02 JP JP30530287A patent/JPH01146361A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1794806A2 (en) * | 2004-09-21 | 2007-06-13 | International Business Machines Corporation | METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY |
| EP1794806A4 (en) * | 2004-09-21 | 2011-06-29 | Ibm | METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY |
| US8169749B2 (en) | 2007-05-22 | 2012-05-01 | Hitachi Global Storage Technologies, Netherlands B.V. | Post-assembly head/disk offset adjuster |
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