JPS60144953A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To reduce the misfit of crystal lattices between both magnesia-spinel layer and a semiconductor layer, and to obtain a wafer with the excellent semiconductor layer having few crystal defects by superposing the magnesia-spinel layer and the semiconductor layer on a magnesia substrate in succesion. CONSTITUTION:MgCl2 in a boat 14A at an upper step of a chamber 13 in a reaction tube 11 is heated 18B and gasified, and forwarded on mangnesia wafers 16 by H2 introduced 12A. Al in a boat 14B at a lower step is heated 18A, and AlCl2 is manufactured by HCl fed in together with H2 and forwarded onto the wafers 16. Magnesia- spinel is grown on the wafers 16 heated 18C through a predetermined reaction. Magnesia-spinel having excellent crystallizability is grown within a range of a growth temperature of 750<=T<=1,200 deg.C, the concentration ratio of MgCl2 to AlCl2 of 0.05<= R<=10 and a growth rate of 0.002<=SG<=0.5mum/min, and a lattice constant extends over 7.9-8.15Angstrom . When Si, GaAs, etc. are grown on the wafer, crystal defects are reduced, and electrical characteristics are also improved. Accordingly, when the wafer is used, elements can be isolated completely, and floating capacitance between the wafer and a substrate is also reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an improvement in a semiconductor wafer having a semiconductor layer formed on an insulating crystal substrate. For convenience, in this specification, the term "semiconductor substrate" refers to all substrates on which various semiconductor layers are grown or necessary processing is performed.

Conventional technology and problems Conventionally, Sol (silicon on 1nsula
Several types of semiconductor wafers are known.

Figure 1 shows an example of such a semiconductor urchin/S, 5O3.
(silicon on 5apphire) structure; FIG.

In the figure, 1 indicates a substrate made of sapphire (α-A*2C++), magnesia spinel (MgO.AAzO:+), etc., and 2 indicates a silicon (St) layer. In addition, MgO・A11'zO3 is exactly (Mg
O) x ・ (Alx O3) I-X (0<x〈
1), but is abbreviated as described above in this specification.

When a semiconductor device is manufactured using this wafer, it has excellent features such as the ability to reduce stray capacitance and the ability to easily and completely isolate elements.

However, there are also disadvantages, for example, since the thermal expansion coefficients of the substrate 1 and the silicon layer 2 are significantly different, for example, if the silicon layer 2 is formed thick, the wafer may be warped greatly. This causes inconvenience in the normal semiconductor device manufacturing process.

In addition, in silicon/sapphire structures, defects tend to occur in silicon due to the difference in lattice constant between silicon and sapphire (because of poor crystal quality, MOS (m
metal oxide semiconductor)
) Even if transistors are good, it is not possible to obtain good characteristics when manufacturing semiconductor devices in which junctions play an important role, such as bipolar transistors.

Furthermore, in the silicon/magnesia spinel structure, although the crystal quality of the silicon layer is good, since high quality magnesia spinel cannot be obtained, the substrate 1 is likely to break.

FIG. 2 is a cutaway side view of a main part of a semiconductor wafer developed by the present inventors in order to eliminate the drawbacks of the conventional example explained with reference to FIG.

In the figure, numeral 4 indicates a silicon substrate, numeral 4 indicates a magnesia spinel layer, and numeral 5 indicates a silicon layer.

This conventional example has a structure in which a magnesia spinel layer 4 is epitaxially grown on a silicon substrate 3, and a silicon layer 5 is further epitaxially grown on top of that, so the crystallinity of the magnesia spinel layer is good.
The crystal quality of the silicon layer 5 is also excellent compared to that of the conventional example shown in FIG. 1, and it is fully possible to form a bipolar transistor.

Further, since the magnesia spinel layer 4 is sandwiched between the silicon substrate 3 and the silicon layer 5, no warpage occurs.

However, even this conventional example is not completely satisfactory in terms of crystal quality, and there is still room for improvement. That is, in this conventional example, there are surprisingly many crystal defects such as stacking faults. A possible cause of this is a crystal lattice misfit between the silicon layer 5 and the magnesia spinel layer 4. Further, stray capacitance when a semiconductor element is formed in the silicon layer 5 may become a problem.

Purpose of the Invention The present invention reduces crystal lattice misfit between a magnesia spinel layer and a silicon layer, thereby making it possible to obtain a semiconductor wafer having a high quality silicon layer with few crystal defects. It is.

Structure of the Invention The semiconductor wafer of the present invention has a structure including a magnesia spinel layer and a semiconductor layer formed in this order on a magnesia substrate.

According to experiments conducted by the present inventors, for example, it is possible to grow a magnesia spinel layer of very high quality on a magnesia substrate obtained by the pulling method. Some semiconductor layers, such as silicon, gallium arsenide (GaAs'), and gallium oxide (GaP), have no crystal defects (and are of extremely high quality).

Examples of the invention FIG. 3 is a cutaway side view of essential parts of an embodiment of the present invention.

In the figure, 6 indicates a magnesia (M g O) substrate, 7 indicates a magnesia spinel layer, and 8 indicates a silicon layer.

The magnesia substrate 6 in this embodiment is an insulator,
Currently, it is not possible to grow a semiconductor layer such as the silicon layer 8 on top of this. However, magnesia
Since the spinel layer 7 can be grown in high quality, if a semiconductor layer such as the silicon layer 8 is grown on the magnesia spinel layer 7, the semiconductor layer will be of high quality without crystal defects. Moreover, the stray capacitance is equivalent to the SOS structure.

FIG. 4 shows magnesia on a magnesia substrate in the present invention.
FIG. 2 is an explanatory diagram of the main parts of a vapor phase growth apparatus used when growing a spinel layer.

In the figure, 11 is a reaction tube, 12A, 12B.

12C is a gas introduction pipe, 13 is a source chamber, 14A
, 14B is a source port, 15 is a wafer holder, 1
6B wafer, 17 exhaust pipe, 18A.

18B and 18C are resistance furnaces, and 19A, 19B, and 19C are arrows indicating gas inflow, respectively.

In this apparatus, magnesium chloride (MgCn
A source boat 14A containing MgCl! 2 is generated, and the gaseous MgCl2 is sent onto the sea urchin fly 6 by the H2 gas which is introduced from the gas introduction pipe 12A and acts as a carrier gas.

In addition, a source boat 14B containing metal aluminum (A/) is arranged in the lower stage of the source chamber 13,
It is heated in the resistance furnace 18A, and the gas introduction pipe 12
HC7, which is sent from B together with the carrier gas Hz gas! Reacts with gas to form gaseous aluminum chloride (A
βCX3) is generated and sent onto the sea urchin fly 6 as before.

Furthermore, the CO2 gas, which is introduced from the gas introduction pipe 12C together with the Hz gas as a carrier gas, is also sent onto the wafer 16.

In such an atmosphere, on the wafer 16 heated by the resistance furnace 18C, a reaction as shown in the following equation occurs and magnesia spinel grows.

M g Cl z +2 A ll CII 3 +
4 COz 1,000 4 Hz → Mg0-AA'203+8H
CI! +4CO The conditions under which the growth experiment was conducted as described above are listed below.

■ Substrate material: Magnesia Surface index: (100-inch shape: 3 x 3 (cm) square thickness 70.5' (+u) ■ Magnesia spinel growth temperature T sub = 92 s (℃) MgCA2
Temperature T+ = 830 C'C) CO2 flowff1p l
= 200 (cc/min) HCII style MFz = 2
5 Ccc 1 minute] H2 flow rate F3 = 20 CI! /min] Growth rate S, = 200 C person/min] Growth film thickness t = 1. ．． Or μm] FIG. 5 is a diagram showing the rocking curve of X-ray diffraction in the magnesia substrate/magnesia spinel layer structure formed as described above.

As can be seen, when the growth is performed as described above, the lattice constant is 4.17 C) and the double lattice is 8.34 (λ
] (Lattice constant 8.03C on a magnesia substrate with diffraction angle 2θ-43,4°)] (Diffraction angle 2θ-45,16)
A layer of magnesia spinel is formed.

On the wafer 16 fabricated under the above conditions, a growth temperature of 950 ("
C), the growth rate is 0.8 [μm/min] and the film thickness is 1
A silicon layer with a thickness of 0 [μm] was grown.

The surface condition of the silicon layer grown in this manner is good, and there are few crystal defects. As for electrical properties, the hole mobility of electrons is 950 Ccm/v.
s), the concentration was lXIQ+6 (cm-3).

By the way, the present inventors set the spinel growth temperature T to 750 (°C)≦T as the growth conditions for magnesia spinel.
≦1200 (“C) The concentration ratio R of magnesium chloride and aluminum chloride is changed as follows: 0.05≦R≦10 The growth rate is changed as follows: 0.002C μm/min]≦5c SG≦0.5 [μm/min] In all cases, magnesia spinel with good crystallinity was grown, and its lattice constant was 7.9 to 8.15. .

By the way, conventionally, in a semiconductor wafer with a Sol structure,
A known technique is to obtain insulation with high voltage resistance by forming a recess in a semiconductor substrate and providing a semiconductor region for forming a semiconductor element in the recess insulated from other parts. If a wafer is manufactured, a high quality silicon layer cannot be obtained as in the above case, and a silicon dioxide (Si02) layer is formed in a silicon semiconductor substrate by applying the ion implantation method, and it is used as an insulating substrate. Alternatively, an insulating substrate is formed by forming a convex part on a silicon semiconductor substrate and alternately stacking a silicon dioxide layer and a polycrystalline silicon layer thereon, and then polishing the silicon semiconductor substrate from the back side. There is also a known technique in which the convex portion is left and all the remaining portions are removed, but all of these methods increase the cost.

However, the present invention is also extremely effective in manufacturing a half-door wafer having such a structure, and this will be described in detail next.

FIG. 6 is a cross-sectional side view of a main part of another embodiment of the present invention, in which, as described above, a recess is formed in a semiconductor substrate, and a semiconductor region for forming a semiconductor element is formed in the recess. A semiconductor wafer provided insulated from others is illustrated. Although this semiconductor wafer is suitable for manufacturing bipolar semiconductor devices, it is not limited to this, and can be used to manufacture various semiconductor devices such as field effect semiconductor devices, diodes, and SIRIS. Wafers can be easily obtained.

In the figure, 21 is a magnesia substrate, 21A is a recess formed in the magnesia substrate 21, 22 is a magnesia spinel layer, 23 is an n+ type silicon semiconductor layer for collector contact, and 24 is an n type silicon active layer. It shows.

FIGS. 7 to 10 are cross-sectional side views of essential parts of semicircular wafers at key points in the process to explain the manufacturing of the embodiment shown in FIG. This will be explained with reference to the figures. In each figure, the same parts as those explained in connection with FIG. 6 are indicated by the same symbols.

See Figure 7■ For example, chemical vapor deposition (chemical vapor deposition)
A silicon dioxide film (not shown) is formed on the magnesia substrate 21 by applying the ur deposition (CVD) method, and is patterned by applying ordinary photolithography technology to form the area where the recess is to be formed. An opening is formed in the opening.

(2) Etching the magnesia substrate 21 using the silicon dioxide film as a mask to form a recess 21A having a size and depth corresponding to the dimensions of the semiconductor device to be manufactured;
After that, the silicon dioxide film serving as a mask is removed.

See FIG. 8. For example, by applying a vapor phase growth method, the magnesia spinel layer 22 is grown to a thickness of, for example, about 1 μm.

See FIG. 9. For example, by applying a vapor phase growth method, the n+ type silicon semiconductor layer 23 is grown to a thickness of, for example, about 5 μm.

Refer to FIG. 10. For example, by applying a vapor phase growth method, the n-type silicon active layer 24 is grown to a thickness of, for example, about 30 (μm).

Refer to FIG. 6■ For example, by applying a polishing method such as etching or lapping, unnecessary n-type silicon active layer 24, The n+ type silicon semiconductor layer 23 and magnesia spinel layer 22 are removed to flatten the surface.

It goes without saying that the silicon active layer 24 in the semiconductor wafer produced in this way is of high quality with few crystal defects and also has a high breakdown voltage.

It is easy to complete a bipolar semiconductor device by applying normal techniques to the semiconductor wafer completed through the above steps. Further, when the semiconductor wafer is used, it is also possible to have a high voltage circuit and a low voltage circuit coexisting, for example, a power transistor and its drive circuit.

Now, conventionally, a pnp transistor and an npn transistor are placed on the same substrate.
It is known to form a transistor into a complementary semiconductor device, in which case a lateral pnp transistor is replaced with an npn transistor.
) In combination with run risk, Darlington connection is used to create a transistor that looks good and has a large common emitter DC current amplification factor hFE, but this technology increases the number of elements and reduces operating speed. There are drawbacks.

However, even in such cases, the use of the semiconductor wafer according to the invention is very advantageous and good results can be obtained.

Next, the present invention will be described in detail regarding a semiconductor wafer suitable for manufacturing this type of transistor.

FIG. 11 shows a cutaway side view of essential parts of this embodiment.

In the figure, 31 is a magnesia substrate, 31A is a shallow recess, 31B is a deep recess, 32 is a magnesia spinel layer,
Reference numeral 33 indicates a p + -type silicon semiconductor layer, 34 indicates a p-type silicon semiconductor layer, 35 indicates an n + -type silicon semiconductor layer, and 36 indicates an n-type silicon semiconductor layer.

12 to 15 are cross-sectional side views of essential parts of a semiconductor wafer at key points in the process for explaining the manufacturing of the embodiment shown in FIG. 11. The explanation will be given below with reference to these figures. In each figure, the same parts as those explained in connection with FIG. 11 are indicated by the same symbols.

See Figure 12 ■ For example, by applying the CVD method, a silicon dioxide film (not shown) is formed on the magnesia substrate 31, and patterning is performed by applying ordinary photolithography technology to the recessed area. An opening is formed in the area to be formed.

(2) The magnesia substrate 31 is etched using the silicon dioxide film as a mask to form shallow recesses 31A and deep recesses 31B, and then the silicon dioxide film used as the mask is removed.

Note that the depth of the shallow recess 31A may be, for example, about 3° [μm], and the depth of the deep recess 31B may be, for example, about 60 [μm].

See FIG. 13 ■ For example, magnesia spinel JW32 is grown to a thickness of, for example, about 1 [μm] by applying a vapor phase growth method.

Refer to FIG. 14■ For example, by applying a vapor phase growth method, the p+ type silicon semiconductor layer 33 is formed to a thickness of, for example, about 5 [μm], and the n-type silicon semiconductor layer 34 is formed to a thickness of, for example, about 25 [μm].
The thickness of the type silicon semiconductor layer 35 is about 5 [μm], for example, and the thickness of the n-type silicon semiconductor layer 36 is about 25 [μm], for example.
Continue to grow each in order.

See FIG. 11 ■ For example, by applying a polishing method such as lapping, polishing is performed until the portion of the magnesia substrate 31 in which no recess is formed is exposed, and unnecessary portions are removed.

As a result, in the shallow recess 31A, an n-type silicon semiconductor layer 34 surrounded by a magnesia spinel layer 32 and a p + type silicon semiconductor layer 33 for collector contact is formed.
is exposed, and in the deep recess 31B is an n-type silicon semiconductor surrounded by a magnesia spinel layer 32, a p + type silicon semiconductor layer, a p type silicon semiconductor layer, and an n + type silicon semiconductor layer 35 for collector/collector. Layer 36 is exposed.

When manufacturing a semiconductor device using the semiconductor wafer thus produced, a pnp transistor is formed in the shallow recess 3LA, and an npn transistor is formed in the deep recess 31B.

According to this embodiment, a silicon layer having any conductivity type, impurity concentration, and thickness can be formed on the same substrate, so it is effective when npn type and pnp type transistors are provided together. It is now possible to easily realize a high-voltage, high-speed complementary semiconductor device, which has conventionally been difficult to achieve on the same substrate.

In the above embodiment, a pnp transistor was formed in the shallow recess 31A, and an npn transistor was formed in the deep recess 31B. You can also do the opposite. It goes without saying that it is also possible to combine not only transistors but also transistors and other semiconductor elements such as silice.

Effects of the Invention The semiconductor wafer of the present invention has a structure comprising a magnesia spinel layer and a semiconductor layer formed in this order on a magnesia substrate, and silicon, gallium arsenide, Semiconductor layers such as gallium phosphide have a significantly smaller lattice misfit with the magnesia spinel layer, resulting in fewer crystal defects and higher quality, as well as improved electrical properties. Are better.

Therefore, when a semiconductor device is manufactured using this semiconductor wafer, for example, it is possible to completely isolate the elements, and the stray capacitance with the substrate can be reduced to the same level as an SOS structure. can be obtained.

[Brief explanation of drawings]

Figures 1 and 2 are cut-away side views of essential parts of different conventional examples, Figure 3 is a cut-away side view of essential parts of an embodiment of the present invention, and Figure 4 is a diagram showing the manufacturing process of an embodiment of the present invention. FIG. 5 is a diagram showing the rocking curve of X-ray diffraction in the structure of magnesia spinel layer/magnesia substrate, and FIG. 7 to 10 are cut-away side views of main parts of other embodiments, and FIGS. 7 to 10 are cut-away side views of main parts of a semiconductor wafer at key points in the process to explain the case of manufacturing the embodiment shown in FIG. , 11th
The figure is a cutaway side view of a main part of still another embodiment of the present invention.
12 to 14 are cross-sectional side views of essential parts of a semiconductor wafer at key points in the process for explaining the manufacturing of the embodiment shown in FIG. 11. In the figure, 6 indicates a magnesia substrate, 7 indicates a magnesia spinel layer, and 8 indicates a silicon layer. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 8 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14

Claims (1)

[Claims] A semiconductor wafer comprising a magnesia spinel layer and a semiconductor layer formed in this order on a magnesia substrate.