JPS62143442A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62143442A
JPS62143442A JP28492485A JP28492485A JPS62143442A JP S62143442 A JPS62143442 A JP S62143442A JP 28492485 A JP28492485 A JP 28492485A JP 28492485 A JP28492485 A JP 28492485A JP S62143442 A JPS62143442 A JP S62143442A
Authority
JP
Japan
Prior art keywords
crystal layer
semiconductor
film
single crystal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28492485A
Other languages
Japanese (ja)
Inventor
Hiroshi Goto
広志 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP28492485A priority Critical patent/JPS62143442A/en
Publication of JPS62143442A publication Critical patent/JPS62143442A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)

Abstract

PURPOSE:To form fine element isolations and to contrive an increase in the integration and density of an IC by epitaxially growing second semiconductor crystal layers selectively on the exposed insulating substrate except a first semiconductor crystal layers. CONSTITUTION:An Si single crystal layer (first semiconductor crystal layer) 12 is epitaxially grown on a substrate 11. The surface of the crystal layer 12 is oxidized to form a thin SiO2 and a (SiO2+Si3N4) film 13 is formed thereon. The film 13 is selectively etched and the films 13 are coated only on the crystal layer 12 at desired regions. The crystal layer 12 is selectively etched away using the films 13 as masks. A heating is performed in an oxidizing atmosphere and SiO2 films 14 are formed on the side surfaces of each crystal layer 12. Si single crystal layers 15 are epitaxially grown selectively on the exposed parts of the substrate 11. Lastly, the masks of the films 13 are removed. Thereby, the fine element isolations are formed and an increase in the integration and density of the IC is attained.

Description

【発明の詳細な説明】 [概要] 半導体結晶層のエピタキシャル成長が可能な絶縁基板上
に、第1の半導体結晶層をエピタキシャル成長し、次い
で、その半導体結晶層を選択的に除去した後、残存した
半導体結晶層の側面に絶縁膜を形成し、次いで、上記除
去部に選択的に第2の半導体結晶層をエピタキシャル成
長する。
[Detailed Description of the Invention] [Summary] A first semiconductor crystal layer is epitaxially grown on an insulating substrate on which a semiconductor crystal layer can be grown epitaxially, and then the semiconductor crystal layer is selectively removed, and then the remaining semiconductor is removed. An insulating film is formed on the side surface of the crystal layer, and then a second semiconductor crystal layer is selectively epitaxially grown on the removed portion.

そうすれば、微細な絶縁膜からなる素子分離帯が形成さ
れる。
In this way, an element isolation band made of a fine insulating film is formed.

[産業上の利用分野〕 本発明は半導体装置の製造方法のうち、特にSOI構造
半導体装置において絶縁分離された単結晶半導体層を形
成する方法に関する。
[Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolated single crystal semiconductor layer in an SOI structure semiconductor device.

半導体集積回路(IC)は需要の拡大と共に、LSI、
VLSIと高度に微細化、高集積化されてきたが、それ
は高集積化するほど、高性能化されるメリットがあるた
めである。
As demand for semiconductor integrated circuits (IC) increases, LSI,
It has been highly miniaturized and highly integrated compared to VLSI, because the higher the integration, the higher the performance.

一方、ICはシリコンなどの半導体基板自体に多数の半
導体素子を形成させるのが一般的であるが、他の方法と
して、絶縁基板上に半導体結晶層をエピタキシャル成長
させたS OI  (Silicon 0nInsul
ator)構造の基板が知られており、半導体結晶層の
エピタキシャル成長が可能な絶縁材料を用いて、絶縁基
板上に半導体結晶層を成長し、その半導体結晶層に半導
体素子を形成する方法がある。そのような構造のICは
寄生容量が少なく、高速化できる等の利点があり、S 
OS (SiliconOn 5apphire)構造
はその代表的なものである。
On the other hand, ICs generally have a large number of semiconductor elements formed on a semiconductor substrate itself such as silicon, but another method is SOI (Silicon Insul), in which a semiconductor crystal layer is epitaxially grown on an insulating substrate.
A method is known in which a semiconductor crystal layer is grown on an insulating substrate using an insulating material that allows epitaxial growth of a semiconductor crystal layer, and a semiconductor element is formed in the semiconductor crystal layer. ICs with such a structure have advantages such as low parasitic capacitance and high speed.
The OS (Silicon On 5apphire) structure is a typical example.

しかし、このようなSol構造においても、できるだけ
高集積化することが望ましいことは当然である。
However, even in such a Sol structure, it is natural that it is desirable to increase the integration as much as possible.

[従来の技術と発明が解決しようとする問題点]さて、
半導体結晶層のエピタキシャル成長が可能な絶縁材料と
しては、上記したサファイヤ基板の他にマグネシャスピ
ンネル(Mg O・A1203)基板などが知られてお
り、何れも結晶性の基板である。
[Problems to be solved by conventional technology and invention] Now,
In addition to the above-mentioned sapphire substrate, a magnetic spinel (MgO.A1203) substrate is known as an insulating material on which a semiconductor crystal layer can be grown epitaxially, and all of them are crystalline substrates.

ところで、このような絶縁基板上の半導体結晶層にIC
を形成する場合、半導体素子間を電気的に絶縁する素子
分離(Isolatton)が必要になる。
By the way, an IC is formed on a semiconductor crystal layer on such an insulating substrate.
When forming a semiconductor device, element isolation (isolatton) is required to electrically insulate between semiconductor elements.

しかし、従来、SOI構造で実施されている素子分離法
は、通常の半導体基板と同様にLOCO8法による絶縁
膜分離か、または、トレンチ(溝)分離である。第2図
はLOCO3法による絶縁膜分離したSol構造の半導
体基板を示しており、1はマグネシャスピンネル基板、
2はシリコン単結晶層、3は酸化シリコン(SiO2)
膜で、形成方法は周知のように、シリコン単結晶層2を
形成した後、選択的に酸化して5i02膜3を形成する
方法である。そして、シリコン単結晶層2が半導体素子
形成領域、5i02膜3が分離帯となる。
However, the element isolation methods conventionally implemented in the SOI structure are insulating film isolation by the LOCO8 method or trench isolation, as in the case of ordinary semiconductor substrates. Figure 2 shows a Sol structure semiconductor substrate separated by an insulating film by the LOCO3 method, 1 is a magnetic spinel substrate,
2 is a silicon single crystal layer, 3 is silicon oxide (SiO2)
As is well known, the film is formed by forming a silicon single crystal layer 2 and then selectively oxidizing it to form a 5i02 film 3. The silicon single crystal layer 2 becomes a semiconductor element formation region, and the 5i02 film 3 becomes a separation zone.

また、第3図はトレンチ分離法を示しており、1はマグ
ネシャスピンネル基板、2はシリコン単結晶層、4は溝
分離帯で、溝分離帯4は溝内の表面に5i02膜を形成
し、その中に多結晶シリコン膜などを埋没させた分離構
造である。
Furthermore, Fig. 3 shows the trench isolation method, in which 1 is a magnetic spinel substrate, 2 is a silicon single crystal layer, 4 is a trench isolation zone, and the trench isolation zone 4 is formed by forming a 5i02 film on the surface inside the trench. It is an isolated structure in which a polycrystalline silicon film or the like is buried.

上記の方法は、一般の半導体基板と同じ素子分離法であ
るが、絶縁基板特有の分離法として、第4図(a)およ
び(b)に示すように、予め、マグネシャスピンネル基
板1上に選択的に絶縁膜5を被着しておいて(同図(5
)参照)、次いで、露出した基板■上に選択的にエピタ
キシャル成長して、シリコン単結晶層2を形成する(同
図(b)参照)方法がある。
The above method is the same element isolation method as for general semiconductor substrates, but as a separation method specific to insulating substrates, as shown in FIGS. An insulating film 5 is selectively deposited on the
), and then selectively epitaxially grows on the exposed substrate (2) to form a silicon single crystal layer 2 (see FIG. 3(b)).

しかし、これらの分離法は素子分離帯を微細に形成する
ことが難しく、例えば、膜厚2μm程度のシリコン単結
晶層2を成長する場合、如何に微細化しても最小の分離
幅は1μm程度、実際上では2μm位の分離帯幅となっ
て、それ以上の微細な幅の分離帯を形成することは困難
である。
However, with these separation methods, it is difficult to form device isolation bands finely. For example, when growing a silicon single crystal layer 2 with a thickness of about 2 μm, the minimum separation width is about 1 μm, no matter how fine it is. In practice, the separation band width is about 2 μm, and it is difficult to form a separation band with a finer width than that.

本発明は、このようなSOI構造の素子分離帯を更に微
細化する形成方法を提案するものである。
The present invention proposes a method of forming element isolation bands in such an SOI structure to further miniaturize them.

[問題点を解決するための手段] その問題は、半導体結晶層をエピタキシャル成長し得る
絶縁基板上に、表面および側面が絶縁膜で被覆された第
1の半導体層を島紙上に形成し、次いで、前記第1の半
導体結晶層以外の露出した前記絶縁基板上に、選択的に
第2の半導体結晶層をエピタキシャル成長する工程が含
まれる半導体装置の製造方法によって解決することがで
きる。
[Means for solving the problem] The problem is to form a first semiconductor layer on an island paper whose surface and side surfaces are covered with an insulating film on an insulating substrate on which a semiconductor crystal layer can be grown epitaxially, and then This problem can be solved by a method for manufacturing a semiconductor device that includes a step of selectively epitaxially growing a second semiconductor crystal layer on the exposed insulating substrate other than the first semiconductor crystal layer.

[作用コ 即ち、本発明は、エピタキシャル成長の可能な絶縁基板
上に、第1の半導体結晶層をエピタキシャル成長し、次
いで、その半導体結晶層を選択的に除去し、次いで、残
存した半導体結晶層の側面に絶縁膜を形成し、次いで、
第1の半導体結晶層の除去部分に選択的に第2の半導体
結晶層をエピタキシャル成長する。
[In other words, the present invention epitaxially grows a first semiconductor crystal layer on an insulating substrate capable of epitaxial growth, then selectively removes the semiconductor crystal layer, and then removes the side surface of the remaining semiconductor crystal layer. An insulating film is formed on the
A second semiconductor crystal layer is selectively epitaxially grown on the removed portion of the first semiconductor crystal layer.

そうすれば、第1の半導体結晶層の側面に形成した絶縁
膜からなる微細な素子分離帯が形成される。
In this way, a fine element isolation band made of an insulating film formed on the side surface of the first semiconductor crystal layer is formed.

[実施例J 以下1図面を参照して実施例によって詳細に説明する。[Example J An embodiment will be described in detail below with reference to one drawing.

第1図(a)〜(elは本発明にかかる形成方法の工程
順断面図を示している。まず、同図fa)に示すように
、マグネシャスピンネル基板11上にシリコン単結晶層
12(第1の半導体結晶層)をエピタキシャル成長する
。成長法は、基板11を1000℃前後に加熱し、その
上に四塩化シリコン(SiC+4 )ガスを送入し分解
させて成長する方法である。そうすると、マグネシャス
ピンネル基板11の結晶方向に沿ったシリコン単結晶層
12が形成される。
FIGS. 1(a) to 1(el) show step-by-step cross-sectional views of the formation method according to the present invention. First, as shown in FIG. (first semiconductor crystal layer) is epitaxially grown. The growth method is to grow by heating the substrate 11 to around 1000° C. and feeding silicon tetrachloride (SiC+4) gas thereon to decompose it. Then, a silicon single crystal layer 12 is formed along the crystal direction of the magnetic spinel substrate 11.

次いで、第1図(blに示すように、シリコン単結晶層
12の表面を酸化して薄い5i02膜を生成し、その上
に化学気相成長(CVD)法で窒化シリコン(Si3 
N4 )膜を被着して、膜厚2000人程度の5i02
膜+Si3N4膜13からなる耐酸化・耐エツチング性
膜を形成し、その上にレジスト膜パターン(図示せず)
をマスクにして選択的に5i02膜十Si3 N413
をエツチングして、所望領域のシリコン単結晶層12の
上にのみ5i02膜+Si3N4膜13を被覆する。
Next, as shown in FIG. 1 (bl), the surface of the silicon single crystal layer 12 is oxidized to form a thin 5i02 film, and silicon nitride (Si3
N4) 5i02 with a film thickness of about 2000
An oxidation-resistant and etching-resistant film consisting of the film + Si3N4 film 13 is formed, and a resist film pattern (not shown) is formed on it.
5i02 film + Si3 N413 selectively using a mask
5i02 film+Si3N4 film 13 is coated only on the silicon single crystal layer 12 in a desired region.

次いで、第1図(C1に示すように、5i02膜+Si
3 N4膜13をマスクにして、露出したシリコン単結
晶層12をCF4と02との混合ガスを用いたりアクテ
ィブイオンエツチング(RI E)法によって、選択的
にエツチング除去する。
Next, as shown in FIG. 1 (C1), 5i02 film + Si
3 Using the N4 film 13 as a mask, the exposed silicon single crystal layer 12 is selectively etched away using a mixed gas of CF4 and 02 or by active ion etching (RIE).

次いで、第1図(d)に示すように、酸化雰囲気中で約
900℃に加熱し、マスクで被覆して残存させたシリコ
ン単結晶層12の側面(露出部分)に、膜厚2000〜
4000人の5i02膜14を形成する。
Next, as shown in FIG. 1(d), the silicon single crystal layer 12 is heated to about 900° C. in an oxidizing atmosphere and coated with a mask to form a film with a thickness of 2000 to 2000° C. on the side surface (exposed portion) of the remaining silicon single crystal layer 12.
4000 5i02 films 14 are formed.

次いで、第1図(elに示すように、再び1ooo℃前
後に加熱し、四塩化シリコン(SiCI4)あるいはジ
クロールシラン(SiH2C12)ガスを送入し分解さ
せて、シリコン単結晶層12をエツチング除去したマグ
ネシャスピンネル基板1工の露出部上に、シリコン単結
晶層15(第2の半導体結晶層)を選択的にエピタキシ
ャル成長し、最後に、5i02膜+Si3N4 膜13
のマスクを除去する。この時、5iC14や5iH2C
I2のような塩素系ガスを用いると、酸化物(St O
□膜+Si3N4膜13マスク)の上にはシリコンは成
長せずに、マグネシャスピンネル基板11のような結晶
基板の上にのみ選択的に成長させることができる。
Next, as shown in FIG. 1 (el), the silicon single crystal layer 12 is etched away by heating it again to around 100° C. and introducing silicon tetrachloride (SiCI4) or dichlorosilane (SiH2C12) gas to decompose it. A silicon single crystal layer 15 (second semiconductor crystal layer) is selectively epitaxially grown on the exposed portion of the magnetic spinel substrate 1, and finally, a 5i02 film + Si3N4 film 13 is grown.
remove the mask. At this time, 5iC14 or 5iH2C
When a chlorine-based gas such as I2 is used, oxides (St O
Silicon can be selectively grown only on a crystal substrate such as the magnetic spinel substrate 11 without growing silicon on the □ film + Si3N4 film 13 mask).

以下の工程は、表出したシリコン単結晶層12゜15の
部分に、半導体素子を形成する。
In the following steps, a semiconductor element is formed in the exposed silicon single crystal layer 12.15.

尚、上記の形成方法において、シリコン単結晶層12.
15をn型シリコン層に形成するには、上記工程の最終
に、砒素イオンを全面に注入すれば良い。又、一方のシ
リコン単結晶7112をn型とし、他方のシリコン単結
晶層15をp型として、0MO5ICなどを形成する場
合には、シリコン単結晶層12を成長してマスクを被覆
する前の工程で砒素イオンを全面に注入してn型にし、
次に、シリコン単結晶JW15を成長した後、マスクを
除去する前の工程で硼素イオンを注入してp型にする。
Note that in the above-described forming method, the silicon single crystal layer 12.
In order to form 15 in the n-type silicon layer, arsenic ions may be implanted into the entire surface at the end of the above process. In addition, when forming 0MO5IC etc. by making one silicon single crystal layer 7112 n-type and the other silicon single crystal layer 15 p-type, the step before growing the silicon single crystal layer 12 and covering the mask. Then implant arsenic ions into the entire surface to make it n-type.
Next, after growing the silicon single crystal JW15, boron ions are implanted to make it p-type in a step before removing the mask.

以上のようにして形成すれば、素子分離帯がザブミクロ
ン程度に微細化され、ICを一層高集積化することがで
きる。
If formed as described above, the element isolation band can be miniaturized to the order of submicrons, and the IC can be further highly integrated.

[発明の効果] 上記の説明から明らかなように、本発明によればSOI
構造ICの製造方法において、微細な素子分離が形成で
きて、ICの高集積・高密度化に大きく寄与するもので
ある。
[Effect of the invention] As is clear from the above explanation, according to the present invention, SOI
In the method of manufacturing a structural IC, fine element isolation can be formed, which greatly contributes to high integration and high density of ICs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(e)は本発明にかかる形成方法の形成
工程順断面図、 第2図、第3図および第4図(at、 (blは従来の
素子分離の断面図、または、形成順断面図である。 図において、 1.11はマグネシャスピンネル基板、2はシリコン単
結晶層、 3’、  4. 5は従来の素子分離帯、12はシリコ
ン単結晶N(第1の半導体結晶N)、13は5i02 
f!!+5taN4膜(耐酸化・耐エツチング性膜)、 14は5i02膜(絶縁膜・本発明の素子分離帯)15
はシリコン単結晶層(第2の半導体結晶層)、を示して
いる。 本姿明嗜9・3ポ践1戸p tr1面mmIII 徒1鯖、線絨ケ酎をネT畔面の g12  因 谷しf/Iトε〉十づi膚tヒ未了表hカ図第 3 図 攻表□w# %” x−ネL・0沖超 @ 4 図
FIGS. 1(a) to (e) are cross-sectional views of the forming method according to the present invention in the order of formation steps, FIGS. 2, 3, and 4 (at, bl are cross-sectional views of conventional element isolation, , are cross-sectional views in the order of formation. In the figure, 1.11 is a magnetic spinel substrate, 2 is a silicon single crystal layer, 3', 4.5 is a conventional element isolation band, and 12 is a silicon single crystal N (first semiconductor crystal N), 13 is 5i02
f! ! +5taN4 film (oxidation resistant/etching resistant film), 14 is 5i02 film (insulating film/device isolation band of the present invention) 15
indicates a silicon single crystal layer (second semiconductor crystal layer). Honga Akashi 9.3 points practice 1 house p tr 1 side mm III 1 mackerel, line carpet ga sho ne T side face g12 Inayashi f/I tε〉10zui skin thi unfinished expression hka Figure No. 3 Figure Attack Table □w# %” x-ne L・0 Oki Super@4 Figure

Claims (1)

【特許請求の範囲】[Claims]  半導体結晶層をエピタキシャル成長し得る絶縁基板上
に、表面および側面が絶縁膜で被覆された第1の半導体
層を島紙上に形成し、次いで、前記第1の半導体結晶層
以外の露出した前記絶縁基板上に、選択的に第2の半導
体結晶層をエピタキシャル成長する工程が含まれてなる
ことを特徴とする半導体装置の製造方法。
A first semiconductor layer whose surface and side surfaces are covered with an insulating film is formed on an island paper on an insulating substrate on which a semiconductor crystal layer can be epitaxially grown, and then the insulating substrate is exposed other than the first semiconductor crystal layer. A method for manufacturing a semiconductor device, comprising the step of selectively epitaxially growing a second semiconductor crystal layer thereon.
JP28492485A 1985-12-17 1985-12-17 Manufacture of semiconductor device Pending JPS62143442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28492485A JPS62143442A (en) 1985-12-17 1985-12-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28492485A JPS62143442A (en) 1985-12-17 1985-12-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62143442A true JPS62143442A (en) 1987-06-26

Family

ID=17684820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28492485A Pending JPS62143442A (en) 1985-12-17 1985-12-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62143442A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234861A (en) * 1989-06-30 1993-08-10 Honeywell Inc. Method for forming variable width isolation structures
US5291058A (en) * 1989-04-19 1994-03-01 Kabushiki Kaisha Toshiba Semiconductor device silicon via fill formed in multiple dielectric layers
KR19990057360A (en) * 1997-12-29 1999-07-15 김영환 Device Separation Method of Semiconductor Device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291058A (en) * 1989-04-19 1994-03-01 Kabushiki Kaisha Toshiba Semiconductor device silicon via fill formed in multiple dielectric layers
US5234861A (en) * 1989-06-30 1993-08-10 Honeywell Inc. Method for forming variable width isolation structures
KR19990057360A (en) * 1997-12-29 1999-07-15 김영환 Device Separation Method of Semiconductor Device

Similar Documents

Publication Publication Date Title
US6448114B1 (en) Method of fabricating a silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness
US4398992A (en) Defect free zero oxide encroachment process for semiconductor fabrication
US6879000B2 (en) Isolation for SOI chip with multiple silicon film thicknesses
JPS5820141B2 (en) semiconductor equipment
KR890003382B1 (en) Manufacturing method of dielectronic isolation complementary ic.
JPS62143442A (en) Manufacture of semiconductor device
US4775644A (en) Zero bird-beak oxide isolation scheme for integrated circuits
US4635344A (en) Method of low encroachment oxide isolation of a semiconductor device
US5212111A (en) Local-oxidation of silicon (LOCOS) process using ceramic barrier layer
JPH05304202A (en) Fabrication of semiconductor device
JPS59135743A (en) Semiconductor device and manufacture thereof
JPS60258957A (en) Manufacture of soi type semiconductor device
JPS6359538B2 (en)
JPS61289642A (en) Manufacture of semiconductor integrated circuit device
US20090053864A1 (en) Method for fabricating a semiconductor structure having heterogeneous crystalline orientations
JPS63229838A (en) Formation of element isolation region
JPS58169935A (en) Manufacture of semiconductor device
JPS6257232A (en) Isolation device and making thereof
JPS5918655A (en) Manufacture of semiconductor device
JPH05211230A (en) Manufacture of semiconductor device
JPH05335407A (en) Manufacture of semiconductor device
JPS59172247A (en) Manufacture of semiconductor device
JPS6185839A (en) Manufacture of semiconductor integrated circuit
JPH02232948A (en) Manufacture of semiconductor device
JPS6030150A (en) Manufacture of semiconductor device