JPS5864045A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To uniformly prepare the crystallinity of an element forming region by epitaxially growing an insulating crystalline layer on a substrate and a semiconductor crystalline layer on the insulating layer, forming by etching an insular semiconductor crystalline layer and burying and growing an insulating crystalline layer in the etched and removed region. CONSTITUTION:The first insulating crystalline (EGI) layer 12 is grown in vapor phase on a silicon substrate 11. Then, an n<+> type silicon crystalline layer 13 and an n type silicon crystalline layer 14 are epitaxially grown. Further, a photoresist film mask 15 is formed on the upper surface of the layer 14, and silicon crystalline layers 13, 14 of an interelement isolating region are etched and removed by a plasma etching method. In this case, the EGI layer becomes a blocking layer, and the substrate 11 is not etched. Then, the mask 15 is removed, the second EGI layer 16 is grown in vapor phase, and the interelement isolating region is buried. Subsequently, the layer 16 grown from the layer 14 is polished and removed, a bipolar semiconductor element I3 is formed on the layer 14, windows are opened at an SiO2 film 17, thereby forming base, emitter and collector contacting regions and electrodes B, E, C.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semi-III device, and more particularly to an improvement in a method for forming isolation between devices.

Semiconductor integrated circuits (ICs) require isolation between individual semiconductor elements in order to electrically insulate them, and a well-known isolation method involves epitaxially growing crystal layers of opposite conductivity on a semiconductor crystal substrate. Well-known methods include PIF junction isolation on the four sides of an aS with two elements formed, or oxide film isolation (insulation isolation) on the four sides, but these methods have wide isolation bands and are difficult to achieve high integration. It has problems such as being moldy and creating parasitic capacitance between it and the substrate. On the other hand, as an SOS method, the insulator f7
``A method of epitaxially growing a crystal layer on a sapphire substrate has been proposed, but it is rarely used, especially in bipolar dyeing, because the sapphire substrate is expensive and the crystallinity of the crystal layer is poor. The situation is that it is not.

Even better, on semiconductor crystal substrates such as silicon substrates! Edge Crystal (K, G, Engineering, EpiiaXLal erowth
A method has been devised in which a layer (onInsulator) is grown and then a semiconductor crystal layer of silicon or the like is epitaxially grown on it. ) is a typical example, and is known to have good crystal consistency with silicon substrates. Figure 1 shows a cross-sectional structural diagram of the conventional example.
This is done after selectively etching one side of the silicon substrate.
On top of that, KKGIMi12 and silicon crystal layer 3 are epitaxially grown and surrounded by KGIfi2.
In this method, semiconductor elements TI and T2 are formed inside and outside the area, respectively. However, this method has the drawback that it is difficult to form the felt region too small, making it difficult to achieve high density, and the characteristics of the semiconductor elements T1 and T2 inside and outside the felt region are non-uniform. is limited.

The present invention aims to eliminate such drawbacks, and its features include a step of epitaxially growing a first PGI layer on a semiconductor crystal substrate and then epitaxially growing a semiconductor crystal layer on the 131st layer J'; This method of manufacturing a semiconductor device includes the steps of selectively etching away a semiconductor crystal layer to form an island-shaped semiconductor crystal region, and growing a second EGI layer buried in the etching removed region, as shown in the drawings below. This will be explained in more detail with reference to Examples.

FIGS. 2 to 7 show sequential cross-sectional views of the manufacturing process according to the present invention. First, as shown in FIG.
First v'aI layers 1 and 2 having a film thickness of 1 [μm] are grown on the film 1 by vapor phase epitaxial growth. When the EGI layer 12 is made of magnetic spinel, the growth temperature is set to about 1000['c], and aluminum chloride (A], 01g) gas and magnesium chloride (MgO1□) gas are fed into the growth reactor together with a carrier gas. , by appropriately controlling the molar ratio of the two to form a length rL on the silicon substrate 11.

Next, as shown in FIG. 3, monosilane (81H4) and arsine (A2B)) were grown using a silicon vapor phase growth apparatus.
Using as a raw material, an n-type silicon crystal layer 13 is epitaxially grown on the KG substrate 12, and then an n-type silicon crystal layer 14 is epitaxially grown by varying the amount of arsine mixed therein. The thickness of the n+ type silicon crystal layer 130 is about 1 [, un), and the thickness of the n type silicon crystal layer 14 is about 2 [μm], and the thickness of II& is 1
01'-1011+, -11.

Next, as shown in FIG. 1184, a photoresist film mask 15 (or a silicon nitride film mask may also be used) is formed on the upper surface, and a mixed gas of freon (AY4) and oxygen is used for etching to remove the gaps between the elements by plasma etching. The silicon crystal layers 13 and 14 in the separation region are removed by etching. At this time, since the layer 101 is not etched, the etching prevention layer 11 and the silicon substrate 11#'i are not etched.

Next, as shown in Figure 5, 7 photoresist film masks 1
After removing the second KGI layer 16, a second KGI layer 16 is grown by vapor phase epitaxial growth to bury the element isolation region removed by etching. In this case, the appropriate width of the element circumferential region 1111i is about 2 [μm], and the EGI layer has good crystallinity if this width is set to about 2 [μm]. However, in the separation formation method according to the present invention, as long as the insulation of the second 801 layer 16 is good, even if the crystallinity is poor, it will not affect the device characteristics, so the width may vary somewhat.

Next, as shown in FIG. 6, the KGI layer 16 grown on the upper surface of the n-type silicon crystal layer 14 is polished and removed by chemical polishing. Chemical polishing uses an alkaline solution mixed with alumina (A1203) fine particles (e.g. 'rxzoy').
1voo-rxzoN) is rotary polished under Efl.

In this way, a bipolar semiconductor element T3, for example, is formed on the exposed n-type silicon crystal layer 14 using a known technique. For device formation, in the present invention, the silicon dioxide (8102) film 17 on the surface is preliminarily exposed to chemical vapor phase t? , long (CvD) method is preferred. This is because it is convenient for flattening the surface, and from now on, the 8102 film 17
Windows are opened to form base, emitter, and collector contact regions and their electrodes B, E, and Q.

The above is an example, and in this way the element is formed fR.
If the regions are formed separately, the crystallinity of each region becomes uniform in two ways, and no variation is observed in the characteristics of the semiconductor element formed in each region. In addition, the element formation area can be made as small as possible, which has the effect of improving the degree of integration, and is extremely useful for improving the performance of ICs.

Although the method for forming the Finpn type bipolar element has been described above, it goes without saying that the present invention can also be applied to forming a pn'p type bipolar element and other elements.

[Brief explanation of drawings]

FIG. 1111 is a sectional view of a conventional element isolation structure, and FIGS. 2 to 7 are process steps of the manufacturing method according to the present invention. In the figure, 1,1lFi semiconductor crystal substrate (silicon substrate),
2, 12 and 16 are FiGI layers and 13°'14#'i silicon crystal layers. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 [

Claims (1)

[Claims] A step of epitaxially growing a first insulating crystal layer on a semiconductor crystal substrate, further epitaxially growing a semiconductor crystal layer on the insulating crystal layer, and selectively etching away the semiconductor crystal layer to form an island-shaped semiconductor crystal region. A method for manufacturing a semiconductor device, comprising the steps of: forming a second insulating crystal layer, and growing a second insulating crystal layer in a buried manner during the etching removal process.