JPH01146321A - Compound semiconductor substrate - Google Patents

Abstract

PURPOSE:To control a crystal defect which is generated in case a III-V compound semiconductor layer is formed on a group IV metal semiconductor substrate, and to obtain an InP layer having little crystal defect and of higher quality by a method wherein a first InP layer and a layer formed by laminating alternately an InAsXP1-X thin layer and an InP thin layer are laminated on the Si substrate and a third InP layer is formed thereon. CONSTITUTION:A compound semiconductor laminated layer constituted by laminating at least three layers of a first semiconductor layer 2 consisting of InP, a second semi conductor layer 3 formed by laminating alternately an InAsXP1-X (0<x<1) thin layer 4 and an InP thin layer 5 and a third semiconductor layer 6 consisting of InP is formed on an Si substrate 1. For example, the substrate 1 cleansed in HF aqueous solution prior to a growth is used and a heat treatment is performed in a PH3+H2-containing atmosphere for 10 minutes or thereabouts at 1000 deg.C. Subsequently, after temperature is lowered down to 400-700 deg.C and the layer 2 is formed in a film thickness of 10-3000nm, the thin film alternate layer 3 formed by laminating the layers 4 and 5 having a film thickness of 2.5-100nm in 10-30 layers is formed as the second semiconductor layer at the temperature of 400-7000 deg.C. Moreover, the formation of the InP layer 6 of a layer thickness of 2-5mum is performed continuously.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention makes it possible to reduce crystal defects in indium phosphide (InP) formed on a silicon (Si) substrate and to improve the quality accordingly. The present invention relates to a compound semiconductor substrate having a layered structure.

<Prior Art> In recent years, thin film crystal growth technology for compound semiconductors has made remarkable progress, and various characteristic devices such as semiconductor lasers, solar cells, and ultrahigh-speed devices using two-dimensional electron gas have been manufactured. However, these devices have
Since it uses a group compound semiconductor substrate, it is very expensive, and it is very brittle and easily damaged. In addition, it has various problems such as difficulty in growing the crystal, making it difficult to increase the area. Therefore, the technology of forming a III-V compound semiconductor on a group III raw conductor substrate, which is inexpensive, has good crystallinity, and has a large area, is attracting attention.
Research on aAs thin film crystal growth technology has become active.

A conventional technique for growing a GaAs thin film on a Si substrate is a two-step growth method (Japanese Patent Publication No. Sho 6l-1) in which GaAs is first grown thinly at a low temperature, and then the temperature is raised to grow it thickly.
70715), a method using a Ge intermediate layer between a Si substrate and GaAs (IEEE Electron Device
e Lett, EDL-2, 169 (1981)),
A method of using alternating layers of GaAs and other l[l-V group compound semiconductors with similar lattice constants as intermediate layers has been proposed, and FETs, light emitting diodes, semiconductor lasers, etc. have been prototyped. In addition, recently, even better GaAs
In order to obtain thin films, strained superlattice layers of InGaAs and GaAs have been formed, and good characteristics have been obtained (A
ppl, Phys, Lett, 48 (1986)
1223).

On the other hand, compared to GaAs, the peak velocity of electrons is higher and the thermal conductivity is higher.
It is considered to be promising as it may be possible to obtain a microwave power amplification element that operates at a higher frequency than aAs and has a higher output.

<Problems to be solved by the invention> InP substrates are more expensive than GaAs, large-diameter ones cannot be obtained (currently 2-inch shapes), and the crystal quality of commercially available substrates has a defect density of 10'm- Only about 2 items were obtained. To overcome these shortcomings,
Research on crystal growth of InP on Si substrates is also progressing. However, although there have been several reports, the crystal quality is still not satisfactory, and there are few examples of its application to devices. The difference in lattice constant between Si and InP is 8. L% is approximately twice the difference in lattice constant between Si and GaAs, and the dissociation pressure of InP is high, so P is easily desorbed during growth and the surface morphology deteriorates. This made it difficult to improve crystal quality. In particular, the several reports mentioned above show that In
These methods include those in which P is grown directly on a Si substrate, but none of these methods can alleviate the effects of large lattice misalignments and stress, resulting in a decrease in crystal quality, and it is difficult to obtain a grown layer with good reproducibility. That is difficult.

Regarding this problem, the present inventors J, J, A, P.

Lett, 26 (1987 JL1587), by using a GaAs intermediate layer, we have developed a technology that allows a high-quality InP layer to be grown over the entire surface with good reproducibility on a 4-inch Si substrate.However, in this way, The obtained InP epitaxial layer also has a crystal defect density (etching bit density; EPD) of 1 to 2
Only insufficient characteristics were obtained at 10' cm-2,
For practical application to devices, even better crystal growth, that is, higher quality (defect reduction) is required. The present invention was created in view of the above points.
By controlling the crystal defects that occur when a III-V compound semiconductor with large lattice misalignment, such as InP, is formed on a semiconductor substrate (particularly Si, etc.), we can create a higher quality InP layer with fewer crystal defects. We propose a compound semiconductor substrate that makes this possible.

Means and operation for solving the above problems> In order to achieve the above object, the compound semiconductor substrate of the present invention has a first InP layer and an InAsxP layer on a Si substrate.
A structure in which alternating layers of 1-x (0 < x < 1) thin layers and InP thin layers are laminated in order from the substrate side, and a desired second InP layer is further formed thereon. This is what was done.

This is a technology applied to the InP layer of the strained superlattice layer, which is a conventional technology, and by applying stress to the first InP layer, which is the base material, crystal defects in the InP layer can be bent or terminated. This reduces crystal defects penetrating and exposing the InP surface, thereby forming a higher quality InP layer.

Engineering nASxP1- with a larger lattice constant than InP
Using X (X20.01~0.20) means that Si
(or GaAs)Cd8. d to aA3<dBnp
In contrast to the compressive stress generated in the first InP layer due to the lattice mismatch with be done. In addition, on the other hand, ■nXGa1
-XAs is also considered, but InG on the first InP layer
It is also possible that disturbances at the InP interface related to P elimination during aAs growth inhibit the high quality of InP crystals.
For the above reasons, it is expected that I nA s xP , -X/InP alternating layers are effective for this purpose.

As per the above explanation, I n A s x P 1 x is effective as the ■-■ group compound mixed crystal constituting the alternating layers, but when forming such alternating layers, Due to lattice misalignment, new crystal defects may occur, and high quality may not necessarily be achieved. Various formation conditions (growth temperature, X value, alternating layer It is necessary to optimize the layer thickness, number of cycles, and growth rate.

The mixed crystal ratio X is preferably about 0.1 or less, and the thickness of each layer of the alternating layers is 100A.
The number of layers is preferably about 30 or less, preferably about 10 to 20 layers.

In addition, during or after the growth of a compound semiconductor substrate having the above structure, the temperature is 100 to 25° below the growth temperature.
By performing heat treatment at a temperature approximately 0° C. higher, it is possible to form a compound semiconductor substrate having a high quality InP layer with fewer crystal defects.

<Example> Hereinafter, an example according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a structural cross section of a compound semiconductor substrate according to an embodiment of the present invention.

In Fig. 1, 1 is a Si substrate, which is a group II raw conductor substrate, and 2
3 is an InP layer as a first semiconductor layer, and 3 is an alternating thin film layer as a second semiconductor layer, which is constructed by alternately stacking InAsXP 1-x layers 4 and InP layers 5. Reference numeral 6 denotes an InP layer which is a third semiconductor layer, which together constitute a compound semiconductor substrate.

The structure shown in Figure 1 above? One way to achieve this is by reducing the pressure M
0 using the OCVD method, the reaction tube internal pressure is 100~
Although it is used at a reduced pressure of 25 Torr, it is also possible to form it at atmospheric pressure.

The underlying substrate 1 was cleaned in an HF aqueous solution prior to growth 4
Using an inch-shaped Si substrate, heat treatment is performed at 1000° C. for about 10 minutes in a PH3+H2 atmosphere. followed by 4
The temperature is lowered to 00 to 700°C, and the first semiconductor layer, InP
After forming a layer with a thickness of lO~3000nm, 400~7
2.5 to 100 as the second semiconductor layer at 00°C.
I n A s x P 1 ++ with nrn film thickness
A thin film alternating layer 3 was formed by laminating 10 to 30 x layers 4 and InP layers 5 alternately. Furthermore, the desired layer thickness 2
An InP layer 6 of ~5 μm was formed.

The raw material gases used here were trimethylindium (TMI) and phosphide 7 when forming the InP layers (2, 3 and 6).
(PH3), and for the InAsXPl-x layer 4, TMI, arsine (AsH3) and DPH3 were used. When forming the InP layers (2°3 and 6), the respective supply amounts were 5.6 x 10-5 (mole fraction) for TMI and 5.6 x 10-5 (mole fraction) for PH.
The feed ratio of TMI and TMI was 70 to 1000. or,
In InAs P, the same % TMI supply amount and PH3 and TMI supply ratio as above
00, and the supply ratio of As H3 and PH3 was set so that the required X value (mixed crystal ratio) could be obtained as the As H3 supply amount. By diluting the above raw material gas with H2, the total flow rate in the reaction tube was set to 15 t/min.

FIG. 2 is a diagram showing a structural cross section of a compound semiconductor substrate according to another embodiment of the present invention, and the same parts as in FIG. 1 are indicated by the same symbols.

In FIG. 2, l is a Si substrate which is a group III raw conductor substrate;
Reference numeral 7 denotes a GaAs layer as an intermediate layer formed on a Si substrate, and has a two-layer structure of a low-temperature formed GaAs layer 8 and a GaAs layer 9. 2 is InP as the first semiconductor layer
2 of the low-temperature formed InP layer 10 and InP layer 11.
It has a layered structure. 3 shows the entire alternating thin film layer as the second semiconductor layer, and this alternating thin film layer 3 is made of InAs.
A plurality of XPl-x (0<x<1) layers 4 and InP layers 5 are alternately stacked. Furthermore, this thin film alternating layer 3
A compound semiconductor substrate as an embodiment of the present invention is constructed by laminating an InP layer as a third semiconductor layer on the substrate.

One way to realize the structure shown in Figure 2 above is by using reduced pressure MO.
CVD method was used. Here, the reaction tube internal pressure is 100~2
Although the pressure is reduced to 5 Torr, it can be formed at atmospheric pressure as well.

As the base substrate 1, a 4-inch Si substrate was used that had been cleaned in an HF aqueous solution prior to crystal growth, and was heated at 1000°C.
Heat treatment is performed in an A S H3+H2 atmosphere for about 10 minutes. Subsequently, the temperature was lowered to 400°C, and a low-temperature formed GaAs intermediate layer 8 was formed with a layer thickness of 10 to 20 nm.
Raise the temperature to 0°C and heat the GaAs intermediate layer 9 to 20~looon.
It was formed with a layer thickness of m. The temperature continued to drop to 400℃,
After forming the InP layer 10 with a thickness of 10 to 20 nm at a low temperature, the temperature is raised to 600°C, and the InP layer 11 is formed with a thickness of 10 to 30 nm.
It was formed with a layer thickness of 00 Onm. Furthermore, maintain this temperature,
I n A s with a film thickness of 2.5 to 1 OO nm, respectively.
x P 1-x layer 4 and InP layer 5 alternately 10 to 30
The layers were laminated to form alternating thin film layers 3. Furthermore, an InP layer 6 having a desired layer thickness of 2 to 5 μm was continuously formed.

The raw material gas supply conditions used here were such that when forming the GaAs layers (8 and 9), triethyl gallium (TE
G) and arsine (AsHa), and also an InP layer (4,
When forming 5, 6, 10 and 11), trimethylindium (TMI) and phosphine (PH3) were used, and I
For nAs XP 1-x, TMI and As
H3 and PH3 were used. The supply amount of each is the same as that of the GaAs layer (
8 and 9) During formation, TEG is 2.5X10 (to molar fraction As H3 and TEG supply ratio is 100.InP
When forming layers 4, 5, 6, 10 and 11), the TMI is 5
．． 6X10' (mole fraction), and the supply ratio of PH3 and TMI is 70 to 2oo. Also, ■nAsXP
In 1-x, the TMI supply amount and PH3 are the same as above.
and TMI supply ratio respectively 5.6X10-5 (mole fraction)
and 70 to 200, and the A s H3 supply amount is set so that the required X value (mixed crystal ratio) can be obtained.
The supply ratio of H3 and PH3 was set. By diluting the above raw material gas with H2, the total flow rate in the reaction tube was 15t.
/min.

As a result, under all conditions in this example, mirror-finished (good flatness) In
A P layer was obtained, and an InP layer having good uniformity of layer thickness distribution of ±8% or less was obtained. Further, observation using an optical microscope shows that no cracks are observed even in the InP layer with a thickness of approximately 12 μm. This means that I
This corresponds to the fact that the residual stress in the nP layer is small.
It is also very useful when forming devices that require relatively large layer thicknesses, such as LEDs. Furthermore, HBr
It was confirmed that a single domain InP single crystal layer was obtained over the entire surface of the 4-inch Si substrate based on the etching pattern shape using +H3P04 (hydrogen bromide + phosphoric acid) solution. In addition, the bits generated by the above etching correspond to crystal defects, and the density per unit area is 1 x 107 bits.
In the case where there is no intervening thin film alternating layer 3 consisting of and InP layer 5 (0
,5~2X108 orchid cm), it is reduced,
It was confirmed that by inserting the alternating layers 3, a higher quality InP layer 6 was obtained.

In addition, a typical laminated structure is 5i (525 μm thick)
100) Substrate 1 or 3 off toward<
0.0 at 1000°C prior to growth using a 110> substrate.
10m1 under H2 atmosphere containing 15Torr of PH3
A heat treatment is performed for 100°C, and then a low-temperature formed GaAs layer (intermediate layer) 8 is formed on the substrate 1 at 10OA and 400°C, and then the temperature is raised to 600°C, and the GaAs layer 9 is
A was formed. Furthermore, after forming 20OA of low-temperature InP layer lO as 7 buffer layers at 400°C, InP layer was formed at 600°C.
The layer 11 was formed to have a thickness of 2 μm. Subsequently, I nA SO,1P with a film thickness of 100A was formed as a thin film alternating layer 3 at 600°C.
A total of 10 layers (a film thickness of 2000 Å) were formed by alternately combining 5 InP layers 5 each having a thickness of 0.9 and 10 OA. Furthermore, the desired InP layer 6 is formed at a temperature of 600° C. to a thickness of 2 to 4 μm to form a compound semiconductor stacked structure? Obtained. In this sample as well, the defect density is -IX1071 solid/,
A high quality InP layer was obtained.

In this way, according to this example, a compound semiconductor substrate having a higher quality InP layer can be formed on a 4-inch Si substrate by reducing the crystal defects described above.

This example is an example of the formation of a compound semiconductor substrate, and by further optimizing the formation conditions and performing heat treatment at a temperature higher than the growth temperature after growth,
Furthermore, a compound semiconductor substrate having a high quality InP layer with low crystal defects can be obtained.

<Effects of the Invention> As described above, the present invention provides an I
The defects that occur when forming nP are called I n A s
By using a new compound semiconductor stacked structure using thin films or alternating layers of x P 1- x and InP,
As a result, a compound semiconductor substrate having a higher quality InP layer can be obtained at a lower cost, and its deformation capacity can be increased by increasing the diameter. or,
Since the Si substrate is used, which has relatively high rigidity, it has good handling properties and is easy to handle.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view schematically showing the structure of one embodiment of the present invention, and FIG. 2 is a cross-sectional view schematically showing the structure of another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Si substrate, 2...1st semiconductor layer (InP layer 9.3...2nd semiconductor layer (alternating thin film layer), 4...
InAsXPl-x layer, 5...InP layer, 6... third semiconductor layer (InP layer), 7-GaAs layer (intermediate J-
), 8... Low temperature formed GaAs layer (intermediate layer), 9-Ga
As (intermediate layer), 10... Low temperature formed InP layer, 11.
...InP layer.

Claims (1)

[Claims] 1. On a silicon (Si) substrate, a first semiconductor layer made of InP, an InAs_xP_1_-_x (0<x<1) thin layer and an InP
1. A compound semiconductor substrate characterized in that a compound semiconductor laminated layer is formed by laminating at least three layers: a second semiconductor layer formed by alternately laminating P thin layers, and a third semiconductor layer made of InP. 2. The compound semiconductor stack includes the Si substrate and the In
GaA is used as an intermediate layer between the first semiconductor layer made of P and the first semiconductor layer made of P.
Claim 1 characterized in that it has an s layer.
The compound semiconductor substrate described in Section 1. 3. InAs_xP_1 constituting the second semiconductor layer
Claim 1, characterized in that the ____x layer and the InP layer each have a thickness of about 100 nm or less, and are alternately laminated in a number of about 30 or less layers. The compound semiconductor substrate described.