JPH01143525U - - Google Patents
Info
- Publication number
- JPH01143525U JPH01143525U JP3843588U JP3843588U JPH01143525U JP H01143525 U JPH01143525 U JP H01143525U JP 3843588 U JP3843588 U JP 3843588U JP 3843588 U JP3843588 U JP 3843588U JP H01143525 U JPH01143525 U JP H01143525U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- conversion circuit
- level conversion
- diode
- connect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Description
第１図はこの考案に係るレベル変換回路の一実
施例を示す回路図、第２図ａおよび第２図ｂは第
１図の入出力波形を示す図、第３図は従来のレベ
ル変換回路を示す回路図、第４図ａおよび第４図
ｂは第３図の入出力波形を示す図である。
１……ＣＭＯＳＩＣ、２……ダイオード、３…
…ノード、４……正電源端子、５……負電源端子
、６……第１分圧抵抗、７……第２分圧抵抗、８
……ノード、９……第３分圧抵抗、１０……ＥＣ
ＬＩＣ、１１……レベル変換回路、１２……コン
デンサ、１３……レベル変換回路。
FIG. 1 is a circuit diagram showing an embodiment of the level conversion circuit according to this invention, FIGS. 2a and 2b are diagrams showing the input and output waveforms of FIG. 1, and FIG. 3 is a conventional level conversion circuit. FIGS. 4a and 4b are diagrams showing the input and output waveforms of FIG. 3. 1...CMOSIC, 2...Diode, 3...
... Node, 4... Positive power supply terminal, 5... Negative power supply terminal, 6... First voltage dividing resistor, 7... Second voltage dividing resistor, 8
...Node, 9...Third voltage dividing resistor, 10...EC
LIC, 11... Level conversion circuit, 12... Capacitor, 13... Level conversion circuit.
Claims (1)
変換回路において、Ｃ―ＭＯＳＩＣの出力にダイ
オードのカソードとコンデンサを接続し、互いに
並列に接続したこのダイオードおよびコンデンサ
を介して２本の抵抗器に接続し、第１の抵抗器の
他端は正電圧源に接続し、第２の抵抗器は第３の
抵抗器およびＥＣＬＩＣの入力に接続し、第３の
抵抗器の他端は負電圧源に接続してなるレベル変
換回路。 In a level conversion circuit that converts C-MOS to ECL level, connect the cathode of a diode and a capacitor to the output of the C-MOSC, and connect to two resistors via the diode and capacitor connected in parallel to each other. The other end of the first resistor is connected to a positive voltage source, the second resistor is connected to a third resistor and the input of the ECLIC, and the other end of the third resistor is connected to a negative voltage source. level conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3843588U JPH01143525U (en) | 1988-03-25 | 1988-03-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3843588U JPH01143525U (en) | 1988-03-25 | 1988-03-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01143525U true JPH01143525U (en) | 1989-10-02 |
Family
ID=31264985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3843588U Pending JPH01143525U (en) | 1988-03-25 | 1988-03-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01143525U (en) |
-
1988
- 1988-03-25 JP JP3843588U patent/JPH01143525U/ja active Pending