JPH01143255A - Read-only memory - Google Patents

Abstract

PURPOSE: To obtain a read only memory wherein density is high, manufacturing cost is low, and row selection/sensing constitution is simple, by applying one out of four states of a diffusion region which has the same conductivity type as a substrate and impurity layer concentration higher than the substrate and a channel region part. CONSTITUTION: An FET of a memory cell is programed by applying one out of four kinds of P<+> impurity diffusion patterns to a channel region. The four kinds of diffusion patterns are (A) a case wherein P<+> impurity diffusion region is not contained in the channel region, (B) a case wherein a P<+> impurity diffusion region 30 is contained only in a channel region part of the drain 20 side, (C) a case wherein a P<+> impurity diffusion region 32 is contained only in a channel region part of the source 22 side, (D) a case wherein a P<+> impurity diffusion region 34 is contained in both of the channel region parts of the drain side and the source side. When the above combination is properly set, one out of four saturation currents can be generated in one direction. The FET's have the same dimension, and the respective P<+> impurity diffusion regions can have the same impurity density by using the minimum design rule. Manufacturing is enabled one time with a masking/P<+> ion implantation process.

Description

DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATION FIELD OF THE INVENTION The present invention relates to read-only memories, and more particularly to FETs (FETs) capable of storing two bits (four values) per memory cell. Single device read-only memory using field effect transistors.

B. Conventional technology ROM (read only memory) is mainly used for storing microprograms and Kanji font patterns, but read/write dynamic RA
Like M (random access memory), it is becoming increasingly highly integrated. Ordinary mask RO using I”ET
M is programmed to store one bit per memory cell, i.e., to represent a binary 1 or a binary 0 depending on whether the memory cell's F. However, in order to increase the amount of data stored per unit area, various methods have been proposed for storing two bits, ie, four values, per memory cell.

One conventional method is, for example, Japanese Patent Publication No. 58-5 '6199.
As shown in the publication, the width (W) vs. length (
r, ) ratio (W/L ratio) is used, and by changing the conductance of the cell FET, the
It stores bits.

This method has the advantage that the manufacturing process is simple because it only requires one ion implantation for setting the threshold value, but it requires changing the dimensions of the FET depending on the cell.
The disadvantage is that minimum design rules cannot be applied to all cell FETs, and cell density cannot be increased.

Another method is to program two bits of information per cell using four types of threshold values in the cell FET, as shown in, for example, Japanese Unexamined Patent Publication No. 56-153582. The threshold value of each cell FET is set by changing the impurity concentration on the substrate surface by ion implantation. Although this method has the advantage of applying minimum design rules to the cell FET, it requires a three-step mask/ion implantation step to program the threshold, making it problematic in terms of manufacturing cost and turn-around time. There is.

Japanese Patent Publication No. 60-45508 discloses another ROM technology in which ions are selectively implanted into the channel region on the source side and the channel region on the drain side of a cell FET to store two bits per cell. There is. This technique has the advantage of using minimal design rules and can be manufactured in a single mask/ion implant step, but it also allows the cell FET to operate bidirectionally by swapping the source and drain of the cell FET during read. The drawback is that it complicates the column selection and sensing configuration of the memory array because it reads one bit in each direction (two bits in both directions).

C8 Problems to be Solved by the Invention It is an object of the present invention to provide an improved multilevel FET that retains the advantages of the prior art described above and does not have the disadvantages mentioned above.
It is to provide ROM.

Means for Solving the D0 Problem The ROM memory of the present invention has an array of memory cells arranged in rows and columns. Each memory cell consists of a single FET with a gate electrode connected to a row line (word line), a drain connected to a bit sense line, and a source connected to a column line. The cell FET has four states: a state in which the channel region does not include the same electrocardiographic type diffusion region as the semiconductor substrate, a state in which the channel region contains the diffusion region only in the channel region adjacent to the drain region, and a state in which the channel region is adjacent to the source region. A state in which only the area portion includes the above diffusion area,
and a state including the diffusion region in at least portions of both channel regions adjacent to the drain region and the source region. The diffusion region on the source region side has a large effect on the threshold value of the cell FET, and the diffusion region on the drain side has a large effect on the conductance. The cell FET operates unidirectionally between the bit sense line and the column line, producing one of four different saturated "direct currents" depending on the programmed state.

E. Embodiment FIG. 1 shows a memory cell array using memory cells according to the present invention, and FIG.
Four types of cells F used in the present invention to store
The cross-sectional structure of ET is shown.

The memory array of FIG. 1 includes three rows and four columns of memory cells, each memory cell consisting of one N-channel FET. The gates of the FETs in each cell row are commonly connected to the word lines WLI to WL3, which are row selection lines, and the drains of the FETs in each cell column are connected to the bit sense lines BLI,
The source of BL2 is connected to column selection lines CLI to CL3. Bit sense line BL1. BL2 is adjacent 1
Column selection line CL2 in the middle, shared by a pair of cell columns
is shared by a pair of adjacent cell columns.

If a larger number of cell columns are included, the bit sense lines and pull selection lines may be arranged alternately in the same way.

The array configuration itself shown in FIG. 2 is well known.

The FET of each memory cell is programmed by providing one of four P+ impurity diffusion patterns in the channel region of the cell FET, as shown in FIG.

These four types of diffusion patterns are (A) when the channel region does not include a P" diffusion region, (+3) drain 20
(C) When the P+ diffusion region 30 is included only in the channel region on the side of the source 22, P' is included only in the channel region on the source 22 side.
and (D) a case where at least the channel region on both the drain side and the source side includes a P'' diffusion region. In this case, as shown in FIG. 2(L)
), there may be a continuous P1 diffusion region 34 throughout the channel region, or there may be two separate P" diffusion regions (in the latter case a configuration including both P9 regions 30 and 32). ) These four types of memory cells are designated A, B, C, and D, respectively, in FIG.

In FIG. 2, 24 is a gate insulating layer, and 26 is a gate electrode connected to a word line.

A feature of the ROM of the present invention is that each cell FET operates in one direction between the bit sense line BL and the column line CL to provide one of four different currents.

The P+ diffusion region is selectively provided in the channel region. Each cell FET has the same dimensions and each P
+Since the diffusion regions can have the same impurity concentration,
It can be manufactured using a single photolithographic masking/P''-(on-implantation process) using the minimum design rule.Furthermore, since the cell FET operates in one direction, the
No complex column selection/sensing configuration is required as in the 0-45508 publication.

Next, the principle of the present invention will be explained. In the present invention, the threshold of the cell FET is mainly controlled by the P+ diffusion region 30 in the channel region portion on the source side, and the threshold value of the cell FET is mainly controlled by the P+ diffusion region 32 in the channel region portion on the drain side.
By controlling the saturation drain current of the ET, in other words, the conductance, and appropriately setting the combination thereof, it is possible to generate one of four saturation currents in one direction. Since the saturation current depends on the presence, position, concentration, and length of the P+ diffusion region in the channel region, the above-mentioned P
By programming the pattern of the diffusion region, four different saturation current values can be generated in one direction.

The impurity concentration of the P-silicon plate is I x 10"/f
f1. The impurity concentration of P" diffusion region 30.32.34 is 2 x 10"'/cot, P" region 30.32.3
4 junction depth is 0.22μ, gate length is 1.0μ, P1
The length of the region 30.32 is 0.15μ, the thickness of the silicon oxide layer of the gate is 250mm, and FIGS. 2(A) and (B)
, (C) and (D) are 11, I2, +3, respectively.
．． When I4, II: I2: ra:l4=1:
A flow ratio of 0.672: 0.424: 0.280 (7)* is obtained.

Since the P+ diffusion regions 30, 32, 34 can have the same impurity concentration, each cell can be programmed with a single masking and boron ion implant.

The ROM memory array of the present invention can be fabricated by any known FET fabrication technique with the addition of a P1 channel ion implantation step. For example, forming semi-buried field oxide regions in non-device areas of a P-silicon substrate, forming a silicon oxide layer on the substrate surface to serve as a gate dielectric, and optionally implanting boron. (
After adjusting the book threshold, P+ diffusion area 30.32.34
Form a resist mask with openings at locations corresponding to ion implant boron, then form a polysilicon gate electrode to serve as a word line and mask the polysilicon gate electrode and field oxide regions. The N+ drain region 20 and the source region 22 are formed by ion-implanting arsenic using the silicon nitride as a material. Boron is 3O-
at 130KeV
Ions are implanted at 4 ions/d.

If the boron concentration for the P+ diffusion region 30.32.34 is too high, the cell'+iJ flow ■1 in the case of FIG. 2(A)
Cell current ■2, I3 in the case of (B), (C), and (D)
, I4 becomes larger, but on the other hand,
If the concentration of boron is too low, the current difference between the currents 11, I2, I3, and I4 will become small, making it difficult to distinguish the sensing currents, so the P+ diffusion region 30 , 32. The boron concentration of 34 is lXl0"'~
I x 10"/C111 is preferred, especially 1-2 x
l O”'/ci is preferred.

The impurity concentration in the source and drain regions is usually 10”/ff.
The boron concentration in the P+ region 30, 32, and 34 is on the order of 1, and the impurity concentration in the P+ region 30, 32, and 34 is very low compared to the impurity concentration in the source and drain regions, and even if boron invades the source and drain regions, it will not have a substantial effect. The mask opening for the P+ region 30 includes a portion of the left side of the drain region 20, the mask opening for the P+ region 32 includes a portion of the right side of the source region 22, and the mask opening for the P+ region 32 includes a portion of the right side of the source region 22. The mask opening for implantation can be made large enough to include part of the left side of the drain region and part of the right side of the source region. A resist mask can be formed.

If two separate P+ regions are used instead of the continuous P3 region 34 of FIG. 2D, the final programming step can be performed after forming the polysilicon gate electrode and source and drain regions. In this case, the resist mask can be patterned to form an opening that exposes the end of the drain region adjacent to the channel region, the end of the source region, or both, and boron ions are implanted, followed by thermal diffusion treatment. good. Boron is implanted directly into the drain and source regions, but since boron has a much faster diffusion rate than arsenic, it is diffused laterally into the channel region by heat treatment, and the P+ region 30.1'' region 32 and these It is possible to simultaneously form a diffusion pattern that includes both of the It is possible to relax the restrictions imposed by

If one cell includes both P+ regions 30 and 32, a single mask opening can be used that exposes both the source and drain region edges.

In the memory array of FIG. 1, reading a memory cell involves driving a selected column line low while keeping the bit sense line high.

This is done by operating the cell FET in saturation. One of four different '11i currents is generated on the bit sense line connected to the selected memory cell.

Detected by a sensing circuit (not shown) connected to the bit sense line.

The sensing circuit is '11! A current detection method or a voltage detection method may be used. Such detection can be performed using any conventionally known circuit, so a detailed explanation will be omitted. For example, in the case of a current detection method, four currents 11, I2, I3 . For I4, I l > Ir, > I 2 > Ir, > T 3 > Ir,
> r 4. Three reference current values Ir, , Ir
This is done by setting 2, Ir, and comparing each reference forward current value with the sensed cell current using three current comparators.
I can do it.

The comparison result can be easily converted to 2 bits by a data decoder. For example, the cell in (A) in Figure 2 is 2-pit'
o o”, (B) is “01”, (C) is 1
0'', (D) represents II I L II, then when all three current comparators produce outputs, 2
generates bit output 1100 II, Ir2 and Ir,
When the comparator generates an output, it generates “01”, and Ir,
When only one comparator generates an output, II I OII is generated, and when no output is generated from all comparators, II
The data decoder may be configured to generate L L II.

Effects of the F0 Invention Since the ROM cell FETs of the present invention can be formed with the same dimensions, they can be manufactured at high density using minimum design rules, and the programming of storage data can be performed in one mask process, reducing turnaround time.・Short time and low manufacturing cost.

Moreover, since two bits can be read in one direction, the column selection/sensing structure is simplified and a very large effect can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating a ROM memory array using memory cells according to the present invention. FIG. 2 is a diagram showing the cross-sectional structures of four types of memory cells used in the present invention. Applicant International Business Machines Corporation Representative Patent Attorney Jinro Yamamoto (1 other person)

Claims (1)

[Claims] A memory device formed in a matrix on a semiconductor substrate of one conductivity type.
The memory cell includes an array of cells, each memory cell having a gate electrode connected to a row select line, a gate electrode formed in the substrate and a bit line.
a single F having a drain region of an opposite conductivity type to the substrate connected to a sense line, and a source region of an opposite conductivity type to the substrate formed in the substrate and connected to a column select line;
A read-only memory consisting of an FET of each memory cell, wherein the FET of each of the memory cells has a channel region that does not include a diffusion region having the same conductivity type as the substrate and having a higher impurity concentration than the substrate. a second state in which the diffusion region is included only in the channel region portion on the drain region side; a third state in which the diffusion region is included only in the channel region portion on the source region side; The channel region portions on both the drain region side and the source region side are given one of the fourth states, and operate in one direction between the bit sense line and the column selection line. A read-only memory configured to conduct one of four different saturation currents.