JPH0664912B2 - Semiconductor memory circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and sometimes to a mask ROM semiconductor memory circuit.

[Conventional technology]

Conventionally, a mask ROM capable of storing 2 bits per memory cell has been proposed with the increase in the capacity of the mask ROM. For example, there is a mask ROM having a configuration shown in FIG.

Referring to FIG. 4, a mask ROM capable of storing 2 bits per memory cell according to the prior art is a current detection P
Has a channel transistors T _{3 0,} typically by connecting a current mirror circuit in the gate portion, the transistor T
Detecting a current flowing through the _{3 0.} In addition, memory transistors T _{3 1} , T _{3 2} , T _{3 3} and T ₃ for memory cells
₄ and, for example, by changing the channel width and the channel length of these memory transistors in four steps, the current flowing through the transistor T _{3 0} changes in four steps when one memory transistor is selected. Binary step
Corresponding to 00, 01, 10 and 11, it is possible to store 2 bits per memory cell.

[Problems to be solved by the invention]

However, the conventional mask ROM capable of storing 2 bits per memory cell as described above has to detect different current values in four steps, and these currents may be different due to variations in manufacturing conditions at the time of manufacturing the mask ROM. There is a drawback that the value is deviated and an erroneous operation occurs when reading the stored contents of the memory cell.

Therefore, an object of the present invention is to provide a semiconductor memory circuit which eliminates the above-mentioned drawbacks and can stably read out the stored contents of 2 bits per memory cell.

[Means for solving problems]

The semiconductor memory circuit of the present invention has a first field effect having a predetermined gate voltage threshold value and a predetermined punch-through voltage value.
A second field effect MOS having a MOS transistor and a gate channel shorter than the gate channel length value of the first field effect MOS transistor so as to have a punch through voltage value lower than the predetermined gate voltage threshold value and a predetermined punch through voltage value. A transistor and a gate oxide film thicker than a gate oxide film of the first field effect MOS transistor so as to have a gate voltage threshold value larger than the predetermined gate voltage threshold value; and a third punch value having the predetermined punch-through voltage value.
Field effect MOS transistor and a gate oxide film thicker than the gate oxide film of the first field effect MOS transistor so as to have a gate voltage threshold value larger than the predetermined gate voltage threshold value and a punch through voltage lower than the predetermined punch through voltage value. Said first field effect MOS to have a value
A plurality of memory cells each including a fourth field effect MOS transistor having a gate channel shorter than a gate channel length value of the transistor; and the first of the memory cells,
When the gate voltage of each of the second, third and fourth field effect MOS transistors is supplied higher than the predetermined gate voltage threshold, the first, second, and
A voltage detection type sense amplifier for detecting a voltage value depending on an on / off state of each of the third and fourth field effect MOS transistors, and the first, second and third memory cells.
And when the drain voltage of each of the fourth field effect MOS transistors is supplied higher than the predetermined punch-through voltage value, the first, second and third memory cells are supplied.
And a current detection type sense amplifier that detects a current value depending on the on / off state of each of the fourth field effect MOS transistors.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are graphs showing the relationship between the drain voltage V _D and the drain current I _D of the memory transistor used in the semiconductor memory circuit of one embodiment of the present invention.

FIG. 1A is a characteristic diagram of a normal memory transistor. When the gate voltage is raised, the memory transistor turns on and a current flows, but when the gate voltage is low, the memory transistor turns off and no current flows. .

FIG. 1 (b) is a characteristic diagram of a memory transistor that has been subjected to operations such as shortening the channel length. It shows the same characteristics as in FIG. 1 (a) in the range where the drain voltage is low, but the drain voltage is high. Then, the punch-through current between the drain and the source of the memory transistor causes a current to flow even when the gate voltage is kept low.

FIG. 1 (c) is a characteristic diagram of a memory transistor that has undergone operations such as thickening the gate oxide film between the gate and the channel region. Since the gate voltage required to turn on the transistor is considerably high, it is appropriate. If the conditions of the gate voltage and the gate oxide film thickness are selected, the memory transistor will not turn on even if the gate voltage is increased.

FIG. 1 (d) is a characteristic diagram in which the memory transistor having the characteristics shown in FIG. 1 (c) has been subjected to operations such as further shortening the channel length. Also in this case, when the drain voltage is increased, punch through is performed. Causes current to flow.

An example in which the above four types of memory transistors are formed on a semiconductor substrate is shown in FIGS. 2 (a) to 2 (d). FIGS. 2 (a) to 2 (d) correspond to the characteristic diagrams of FIGS. 1 (a) to 1 (d), respectively.

Next, referring to FIG. 3 showing a circuit diagram of a semiconductor memory circuit of an embodiment of the present invention, the semiconductor memory circuit of this embodiment has a total of eight semiconductor memory circuits arranged in four rows and two columns. a memory transistor constituted of four transistors of the aforementioned _{(T 1 0 ~T 1 7)} , to select the voltage applied to the drain of the memory transistor _{(T 1} 0 _~T 1 ₇₎ transistor _(T 0 1 through T ₀ ground ₄ and), and the P-channel MOS transistor _{T 0 5} and _{T 0 6} for detecting a current flowing through the memory transistor _{(T 1} 0 _~T 1 _7), the source of the memory transistor _{(T 1} 0 _~T 1 ₇₎ This is a configuration including transistors (T _{2 0 to} T _{2 3} ) that select whether or not to perform. Further, the P-channel MOS transistors T _{0 5} and T _{0 6} are shared by all memory transistors in the column direction, and the transistors (T _{2 0 to} T _{2 3} ) are shared by all memory transistors in the row direction.

Further, the semiconductor memory circuit according to an embodiment of the present invention, a current detection type sense amplifier S ₁ and S ₂ for detecting the stored contents read out from the memory transistor _(T 1 _{0 ~T} 1 ₇₎
And it has a voltage detection type sense amplifier _{S 3} and _{S 4,} also transistor for selecting a voltage applied to the drain of the memory transistor _{(T 1 0 ~T 1 7)} (T 0 1 ~
T _{0 4)} and a memory transistor _{(T 1} 0 _~T 1 7)
P-channel MOS transistor for detecting a current flowing through the _{(T 0} 5 _~T 0 ₆₎ and a memory transistor _{(T 1 0}
Through T _{1 7} transistor for the selection of whether or not to ground the _{source) (T 2 0 ~T 2 3} ) and a control signal for controlling each of the memory transistors _{(T 1 0 ~T 1 7)} (φ 0 1 φ _{2 3} ).

Next, the operation of reading the stored contents of the semiconductor memory circuit of one embodiment of the present invention will be described.

To simplify the description of this embodiment, the transistor T
Transistors other than _{0 5} and T _{0 6} are N-channel MOS
It is assumed to be a transistor.

First, the case of reading the state when the gate voltage of the memory transistor T _{1 0} is increased will be described. (1) The transistor T _{0 is set} at the high level of the control signal φ _{0 1.}
Turn ₁ on.

(2) When the control signal φ _{0 2 is} at a low level, the transistor T ₀
Turn off ₂ .

(3) Each of the control signal φ _{1 0} and the control signal φ _{2 0} is set to a high level to bring the memory transistor T _{1 0} into an operable state.

(4) Set the control signals (φ _{1 1 to} φ _{1 3} ) to low level,
The memory transistors (T _{1 1 to} T _{1 3} ) and the memory transistors (T _{1 5 to} T _{1 7} ) are turned off.

(5) After completing the operations (1) to (4) described above, the output of the voltage detection type sense amplifier S ₃ is read.

In the above operation, if the memory transistor T _{1 0} has the transistor characteristics shown in FIG. 1A or 1B, the memory transistor T _{1 0} is turned on and the potential of the data line D ₁ is changed. Becomes a low level. Further, if the memory transistor T _{1 0} is a transistor characteristics shown in FIG. 1 (c) or FIG. 1 (d), the memory transistor T _{1 0} will remain off, the potential of the data line D ₁ High level.

That is, it is possible to correspond to the information of the status of each of the aforementioned memory transistor T _{1 0} "0" and "1".

Next, the case of reading the state when the drain voltage of the memory transistor T _{1 0} is increased will be described. (1) The control signal φ _{0 2 is set} to a high level to turn on the transistor T _{0 2} .

(2) The control signal φ _{0 1 is set} to low level to turn off the transistor T _{0 1} .

(3) The control signals φ _{1 0} , φ _{1 1} , φ _{1 2} and φ _{1 3} are set to low levels to turn off the memory transistor T _{1 0} .

(4) The control signal φ _{2 0 is set} to the high level, and the punch-through current of the memory transistor T _{1 0} is changed to the transistor T _{2 0.}
To flow through. Control signal (φ _{2 1} ~
φ _{2 3} ) is set to a low level, and the memory transistor (T _{1
Even if 1 to} T _{1 3} ) are in a state where a punch through current flows, the current is cut off.

(5) After completing the operations (1) to (4), the output of the current detection type sense amplifier S ₁ is read.

When the above operation, only have transistor characteristics cause punch-through in the memory transistor T _{1 0} is the first diagram (b) or Figure 1 as shown in (d) of high drain voltage V _D (H) if, current flows through the transistor _{T 0 5.} However, the memory transistors _{T 1 0} is the first diagram (a) or Figure 1 as shown in (c) high-level drain voltage V _D (H)
If the transistor characteristic does not cause punch-through, no current flows in the transistor T _{0 5} .

That is, it is possible to correspond to the information of the status of each of the aforementioned memory transistor T _{1 0} "0" and "1".

The above operation is performed by the other memory transistors (T _{1 1 to} T _{1
The same} can be done for ₇ ).

As a result, 16 bits can be stored in 8 memory cells.

〔The invention's effect〕

As described above, according to the present invention, a mask RO having a memory of 2 bits per memory cell that can be stably read.
Since M can be configured, there is an effect that a large-capacity mask ROM semiconductor memory circuit can be realized.

[Brief description of drawings]

1 (a) to 1 (d) are diagrams showing the relationship between the drain voltage V _D and the drain current I _D of the memory transistor used in the semiconductor memory circuit of one embodiment of the present invention, and FIG. 2 (a). )
2 (d) is a sectional view of a memory transistor used in the semiconductor memory circuit of one embodiment of the present invention, FIG. 3 is a circuit diagram of the semiconductor memory circuit of one embodiment of the present invention, and FIG. It is a circuit diagram of an example semiconductor memory circuit. 1a to 1d …… Semiconductor substrate, 2a to 2d …… Insulating film, 3a to 3d ……
Source, 4a-4d ... Drain, 5a-5d ... Gate, 6a-
6d ...... gate insulating film, _{D 1, D 2} ...... data line, I _D ...... drain _current, S 1 ~S ₄ ...... sense _{amplifiers, T} 0 1 through T
_{0 6} ,, T _{2 0} ~ T _{2 3} ,, T _{3 0} ... Transistor, T _{1 0} ~
_{T 1 7, T 3 1 ~T} 3 4 ...... memory transistor, U, W ...
… Load characteristics, V _D …… Drain voltage, V _D (H) …… High level drain voltage, V _D (L) …… Low level drain voltage,
Xa〜Xd …… Characteristic curve when gate voltage is high level, Ya〜
Yd: Characteristic curve when gate voltage is low level, φ _{0 1} ~
_{φ 0 4, φ 1 0 ~φ} 1 3, φ 2 0 ~φ 2 3 ...... control signal

Claims (1)

[Claims] 1. A first field effect MOS transistor having a predetermined gate voltage threshold and a predetermined punchthrough voltage value, and a predetermined field effect MOS transistor having a punchthrough voltage value lower than the predetermined gate voltage threshold and the predetermined punchthrough voltage value. A second field effect MOS transistor having a gate channel shorter than a gate channel length value of the first field effect MOS transistor, and a gate of the first field effect MOS transistor having a gate voltage threshold larger than the predetermined gate voltage threshold. A gate oxide film thicker than an oxide film, a third field effect MOS transistor having the predetermined punch-through voltage value, and a gate oxidation of the first field effect MOS transistor having a gate voltage threshold value larger than the predetermined gate voltage threshold value. Thicker than the gate oxide film and the specified punch-through voltage value There fourth with the first short gate channel than the gate channel length value of the field-effect MOS transistor to have a punch-through voltage
And a gate voltage of each of the first, second, third, and fourth field-effect MOS transistors of the memory cell, the plurality of memory cells each including the field-effect MOS transistor are set to be larger than the predetermined gate voltage threshold value. And a voltage detection type sense amplifier for detecting voltage values depending on ON / OFF states of the first, second, third and fourth field effect MOS transistors of the memory cell, When the drain voltage of each of the first, second, third and fourth field effect MOS transistors is supplied to be larger than the predetermined punch through voltage value and supplied, the first, second and third memory cells are provided. And a current detection type sense amplifier for detecting the current value depending on the on / off state of each of the fourth field effect MOS transistors. Circuit.