JPS63239693A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To rapidly actuate a 1st bit line by the small current capacity in a memory cell and to actuate a 2nd bit line by an amplified large current to attain rapid operation by connecting a structure for connecting plural 1st bit lines to the 2nd bit lines through current amplifier circuits in series by one stage or more. CONSTITUTION:The structure for connecting plural 1st bit lines 7, 8 to the 2nd bit lines 11, 12 through the current amplifier circuits 3, 4 in series by one stage or more. The drain of each p-channel MOSTR out of the 2nd bit lines 11, 12 is connected to each of the divided 1st bit lines 7, 8. Load capacity based upon the drain of the p-channel MOSTR becomes load capacity between the 2nd bit lines 11, 12 and a power supply and 1/2-1/4 the ordinary load capacity can be reduced. Since the small current capacity in the small memory cell drives the load capacity and the 2nd bit lines 11, 12 and the load capacity of the bit lines 11, 12 can be reduced to 1/3-1/4 by the amplified large current, rapid operation can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit configuration and a data read circuit in a semiconductor memory iH.

[Conventional technology]

A semiconductor memory device consisting of seven transistors (MOS) has
Write data using a photo-etching mask during the manufacturing process Mask ROM 1 EP with floating gate structure
There are ROM and EEPROM, but here we will explain mask ROM, which has a simple and easy-to-understand structure. This mask ROM is, for example, l5SCCDIGEST
OF TECHNICAL PAPER
3, P14e to 1 47.32θ, 1984, the configuration is as shown in Figure 3 (P32θ) and Figure 4 (P147). In Figure 4 of this paper, there is a word line that connects the output of the Row Decoder, which manually receives the signals A and ~Ate of the signals specified by the address input terminal, to the gate of the memory cell, and there are two word lines above and below. One of the two divided 512X is selected and becomes the high level. Also, address signals As~Am, A
The ColumnDecoder (column decoder) that inputs
-N channel MO3) 71 runges are turned on, and as a result, one memory cell from two 512x128 memory cell arrays is connected to a selected sense amplifier by a row decoder and a column decoder.

Data writing to the mask ROM is performed using a photo-etching mask during the manufacturing process.
In the above paper, depending on whether a through hole is formed or not, the connection between the drain of a MOS transistor (which is a memory cell) and the bit line is determined depending on whether or not a through hole is formed. Binary information is written depending on whether there is a route or not. For example, if the selected memory cell has a through hole and is connected to the bit line, the bit line is pulled down to the low level side by the selected memory cell, the input and output of the MOS inverter are shorted, and the sense level is determined. Pull the amplifier input to the low level side. As a result, the output from the three stages of MOS inverters connected to the sense amplifier becomes high level. Also, if the selected memory cell does not have a through hole, there will be no path from the bit line to the power supply terminal, resulting in an open plate.
When the memory cell has a through hole, the input of the bit line and sense amplifier goes to the high level side,
The output after three stages of MOS inverters is at a low level. In this way, in the above-mentioned paper, the binary m-signal is written using a through hole, but it is also possible to change the threshold voltage of the MOS transistor by implanting ions into the channel part of the memory cell. Similarly, 2 applies even if the method depends on whether or not to form a diffusion layer.
It is possible to write value information.

[Problem that the invention seeks to solve]

In the configuration of the IM bit mask ROM in the above paper, as shown in Figure 4, 512 memory cells are connected to one bit line, and although the number varies depending on the through hole, in the most cases all memory cells are connected. is connected to the bit line. At this time, as shown in Figure 1 (al), the bit line is connected to the drain of the MOS transistor through a through hole, and as a result, the bit line has a capacitive load between the 512 drain diffusion layers and the substrate. The most common dish is 512
Since there is a capacitance between the drain of the transistor and the substrate and a capacitance load between the AI forming the bit line and the power supply terminal, the load capacitance becomes extremely large. Here, the MOS transistor which is a memory cell is made to have a minimum size in order to increase the capacity of the memory cell, and for example, according to the 2 μm rule in the above-mentioned paper, the channel width is about 3 μm. As the current capacity of the MOS transistor, which is a memory cell, is set small, it takes a lot of time to operate a large load on the bit line. As capacity increases and miniaturization increases, the channel width of memory cells decreases, which means a decrease in current capacity.Also, as capacity increases, the number of memory cells connected to a bit line increases, resulting in an increase in load capacity, which leads to an increase in operating speed. This will result in a decline.
As a method for reducing the bit line load capacitance, the above paper divides the memory cell array into two as shown in Figures 3 and 4, and uses a configuration in which column transmission transistors and sense amplifiers are inserted between them. Increasing the number results in an increase in the number of column transmission transistors and sense amplifiers, as well as an increase in the wiring area for the sense amplifier output Ii1, etc., resulting in an increase in the chip area. Nikkei Electronics 198
It will be understood that the mask ROM of 2M bits or more shown in 6.4.21, P124 is also divided into about two parts, and the area of the column transmission transistor and sense amplifier section of the divided chip is large.

The present invention reduces the load capacitance of the bit line and drives the bit line with a large current capacity using smaller memory cells without considering the current capacity, thereby achieving a highly integrated and high speed semiconductor memory device. The purpose is to obtain.

[Means for solving problems]

In the semiconductor memory device of the present invention, the bit line is composed of a plurality of bit line groups, and the first bit line is connected to the second bit line via the current amplification circuit, or the first bit line selection circuit and the current amplification circuit.
A configuration in which a plurality of bit lines are connected in series is connected in one or more stages, the first and second lines are connected to the memory cell, and the final stage bit line is connected to the sense amplifier via a bit line selection circuit. It is characterized by

〔Example〕

FIG. 1 shows an embodiment of the present invention in which a plurality of first bit lines are connected to second bit lines via current amplification circuits in one stage, where 1 is a sense amplifier and 2 is a pin. The output terminal of the selection circuit, 3.4 is a current amplification circuit, 5 and θ are memory cells, which are examples of N-channel MO5 transistors, 7.8 is the first bit line, and 9.10 is a current amplification circuit. 11.1
2 is the second bit line, 13.14 is an N-channel MO8 transistor for bit line selection, 15.16 is the output II of the column decoder, and 17.18 is the output line of the row decoder. In the fJ1 diagram, for example, when memory cell 5 is selected, word l117 becomes high level and other words! 118 is at a low level. Further, the column decoder output line 15 becomes high level, the other column decoder output 1a16 becomes low level, the bit line selection N-channel MOS transistor 14 is turned on, and the second bit line 11 is connected to the sense amplifier 1. If the memory cell 5 is wired so that a current path is formed between the data bit line til and the ground, the current capacity of the memory cell 5 from the P-channel MO8 transistor 9 is as follows.
A corresponding current flows through the ground terminal. At this time, since the gate and drain terminals of the P-channel MO3 transistor 9 are connected, the current capability of the memory cell 5 can be taken out by the potential between the power supply terminal and the gate. The current capacity of the memory cell 5 is amplified through the P-channel MOS transistor 10 due to the size ratio of the P-channel MO3 transistor 9 and 10 connected to the gate of the P-channel O5 transistor. ) II11
can be taken out.

For example, if the channel width of the P-channel MO3 transistor 9 is 1, the P-channel MO8) u/transistor! If the channel width of 0 is a ratio of 6 and each channel length is equal, then the bit line of jtT2! 1, a current twice the current capacity of the memory cell 5 can be taken out. On the other hand, since all memory cells connected to bit II8 of if are off, all current amplifying P-channel MO8 transistors are off, and bit I of i2! Only the current 505 times as much as the selected memory cell can be extracted from the memory cell 11. Also, if data is written so that there is no current path from bit 1617 of f41 to ground, that is, if memory cell 5 is turned off, the unselected first bit! Similar to 18, P-channel O5 transistor 9.10
becomes off and current cannot be taken out to the second pin ($111). In this way, the two pieces of information can be configured to directly extract the current capacity.Here, the first
It is possible to make the bit lines by dividing the second bit line, and in the partial diagram shown in FIG. If there are 512 bit lines, and the number of memory cells connected to the first bit line is 32, then 16 first bit lines will be connected to the second bit line via a current amplification circuit. As a result, the length of the first bit line is 171 in the above paper.
6, and the number of memory cells connected to the first bit line is also 1/16, so the first bit line load capacity is 1/small load capacity of the bit line rlEl with the current capacity of the memory cell. It will be driven. Also, the 12 bit lines are
One P channel M for divided first bit line
The drain of the OS transistor will be connected,
The load capacitance due to the drains of the 16 P-channel MO3 transistors and the load capacitance between the second bit line and the Wl power supply are reduced to 173 to 1/4 of the load capacitance in the above paper. In this way, the current capacity of the small memory cell drives a small load capacitance, and a large current is amplified to drive the second bit 1, and the load capacitance of the fi2 bit line is also reduced to 1/3.
~1/4, enabling high-speed operation.

Further, the current amplification circuit can also be formed by two P-channel MOS transistors, and since the number of MOS transistors is increased by two compared to 32 memory cells, this can be done without increasing the area. Further, the sum of the load capacitance of the first bit line and the second bit line to be driven is 1/3Cb+1/18Cb=19/48Cb, where cb is the load capacitance of the circuit in the above paper.
Since the load capacitance is 2 or less, the current consumption due to bit line driving can also be reduced to 1/2 or less.

FIG. 2 shows another embodiment of the present invention, in which a plurality of first bit lines are connected to a second bit line via a current amplification circuit in one stage as in FIG. 1. This is an example.
In FIG. 2, 19.20 is an N-channel MOS transistor that constitutes a current amplification circuit, 1 is an example of a sense amplifier, 21 is a signal that controls the operation of the sense amplifier, and 22 is a reference obtained from a gummy cell, etc. 23 is the output terminal of the sense amplifier, 24 to 26 are N-channel MOS transistors constituting the sense amplifier, and 27 to 29 are P-channel MOS transistors. FIG. 2 shows an example in which the current amplification circuit is constructed from the same N-channel channel MO3 transistor as the memory cell, and the N-channel MOS transistor that is the memory cell is connected to the high power supply side. The sense amplifier shown in FIG. 2 is an example of a current detection type sense amplifier, and is a P-channel MOS). 1211, that is, the current of the amplified memory cell, is detected, and the P-channel MOS
The current capacity of the transistor 29 is compared with the current of the N-channel MOS (N-channel MOS) latdisk 24, which operates with the reference potential 22 at its gate. P-channel MOS transistor 27 and N-channel MOS transistor 25.2Ei are the output 2 of the bit line selection circuit, and also the second bit! !
This is a negative feedback circuit that stabilizes the voltage level of 11. m2
In the illustrated embodiment, the current amplification circuit has the same N
Since it is made of channel MOS transistors, there is no need for an N-channel and P-channel separation band in the memory cell array, and two MOS transistors are used for one first pin (I).
A transistor may be sufficient, and the increase in area due to the current amplification circuit is even smaller, and becomes almost incomprehensible.

The third part is another embodiment of the present invention, and is a partial diagram showing a configuration in which a plurality of first bit lines are connected to the bit line of tJ2 via a selection circuit and a current amplification circuit, and 30.
Jl bit! Signals 134 and 35 select two parallel lines, and 32 and 33 are N-channel MO8 transistors for selecting first bits fi34 and fi35. The TIS diagram shows a configuration in which two parallel first bit lines are connected to a current amplification circuit via a selection circuit, and it is sufficient to arrange a current amplification circuit for the first 112 bit lines, except for memory cells. In this case, only four M, O3) transistors are required, and as in FIG. 2, there are two MOS transistors for one first bit line, and this can be realized without increasing the area.

In the configuration of FIG. 3, only one second bit line is required for two first bit lines (for example, the first bit line is
The second bit line is formed using a material such as polysilicon, which is easier to miniaturize compared to I, etc., and the second bit line is made of a low-resistance wiring material, which is difficult to miniaturize, such as AI, to minimize the memory cell size. be able to. In addition, by forming the first bit line and the second bit line into two lines via an insulating film, and using the upper layer of the second bit line with respect to the semiconductor substrate, it is possible to ! 1 film becomes thicker, and the load capacitance between the wiring layer and the power supply, which includes most of the bit line load capacitance of *2, is reduced,
Even higher speeds can be achieved. Furthermore, ITI's bit line and! By converting the 2 bit lines into 2 ports, the 2nd bit line can be placed on the 1st bit line or on top of the RIi2 between the 1st bit lines. Even if the number of bit lines such as line and second bit line increases, it can be realized without increasing the area.

Next, an embodiment of the present invention will be described in which the bit line described above has a multilayer structure and the first bit line is made of polysilicon material.

FIG. 4 shows the circuit configuration of the tjEa diagram, and is a plan view of the memory cell and the first bit line selection circuit excluding the current amplification circuit, where 36 is a word line made of gate material, and 37 is a word line made of polysilicon material. The first bit line 38 is a polysilicon material for connecting to the source of a MOS transistor which is a memory cell, 39 is an i2 bit line A1140
41 is a contact hole for connecting the polysilicon material and the AI, 42 is a hole for connecting the polysilicon material and the diffusion layer with a buried contact, and 43 is the first pin (Ii) which is connected to the source in the same way. ! 44 is a gate material which is a selection line of the first bit line; and 45 is a step in an oxide film for forming a MOS transistor which is a memory cell. To briefly explain how to create a buried contact, after forming an oxide film for forming a MOS transistor, a gate film layer is applied, then a gate material is coated on the entire surface, and then an oxide film is applied on the gate material. . Next, the gate material is photoetched to etch the oxide film on the gate material, the gate material, and the gate oxide film. Thereafter, drains and drains are formed by ion implantation, etc., and an oxide film is formed on the entire surface. Then, since the oxide film remains on the gate material, it is thicker than the top of the diffusion layer. Similar to the technique for leaving a film, a buried contact hole is photo-etched, a polysilicon material is applied thereon, and a butter 7 is formed by photo-etching. After that, an interlayer insulating film, contact holes, and AI are formed as in a normal MO3 transistor structure. In this way, the first bit line and the source and drain of the memory cell can be connected through buried contacts in a self-aligned manner, making it possible to create a memory cell with the minimum pitch of gate material and polysilicon material. . Polysilicon material has a higher resistivity than metals such as A1, but as in the first bit line of the present invention,
When split and used in short lengths, the first bit line, which is also made of polysilicon material, is
The bit lines are long and have low resistance, making them very useful in configurations where they are driven by large currents. As a result, in order to take full advantage of the characteristics of each, the gate material is usually made of polysilicon material in terms of pattern, and since it is made with the minimum design dimension, the gate material and the first bit line are made of polysilicon material. Memory cells whose dimensions are determined by Although the film is thicker, an efficient configuration is possible in which a large load capacitance is driven by a large current obtained by amplifying the second bit line with a small resistivity.

FIG. 5 shows another embodiment of the present invention, in which there are two stages in which the first bit line is connected to the fJ2 bit line via a current amplification circuit, and 46.47 is the second embodiment. The bit line 48 is an eighth bit line, 49.50 is a current amplification circuit of the 1\2 bit line 48.47, and 51.52 is an N-channel MOS transistor forming the current amplification circuit. The configuration shown in Figure 5 adds one more stage between the first bit line, which drives a small load capacitance with a small current, and the third bit line, which is the final stage. It is designed to drive the load capacity.

FIG. 6 shows another embodiment of the present invention, in which the first bit $1
34 and 35 are connected to a current amplification circuit 62 via selection N-channel MOS transistors 32.33, and an inverting amplification circuit 61 which is a voltage stabilization circuit for the first bit 1134.35. With its output signal,
An N-channel MOS transistor 56 is added to control charging of the first bit line. The current amplification circuit has a two-stage configuration including a 63.64 P channel MOS transistor and a 65.8f3 N channel MOS transistor. 54 outputs a low level signal when either bit line selection signal 30 or 31 of if becomes high level, and 53 outputs a low level signal when the second bit ll1l is selected, that is, as shown in Fig. 186. Although not shown, when the bit line selection signal of ti2 reaches the selection level, it becomes low level, and the inverting amplifier 61 and the first
This is a selection signal for activating the charging control N-channel IVIO3 transistor 56 of the bit line. In the configuration of FIG. 8, for example, when the memory cell 5 is selected and the first bit line 34 is at the initial ground level, the word l1117 and the selection signal 30 are at a high level,
When the selection signals 53 and 54 go low, the N channel M
The source potential of the OS transistor 56 falls to a low level,
As a result, the output of the inverting amplifier 61 becomes high level and charges the first bit line 34 through the current detection P-channel MO3 transistor RO 3. When the source potential of the N-channel MOS transistor 56 rises, the output of the inverting amplifier 61 falls to the low level side, lowering the current capacity of the N-channel MOS transistor 56, thereby attempting to maintain a stable potential. . In the circuit configurations up to Figure 1.5, the load capacitance is reduced and the operating speed of the first bit line is increased depending on the number of divisions of the first bit line, but in the configuration of Figure 6, By dividing the first bit line and using a charging control circuit, the bit line with a small load capacitance tJl is brought to a stable potential more quickly, and the current of the memory cell is amplified to drive the second bit line. , which aims to further increase the operating speed. In the configuration shown in Figure 6, the two first
Although an inverting amplifier circuit and a current amplifying circuit are connected to the bit line, it is possible to reduce the area increase of additional circuits by increasing the number of first bit line selection circuits, as in the configuration up to Figure 3. It is possible. Furthermore, the charge control circuit allows the load capacitance of the first bit line to be increased compared to the configurations up to FIG. 3 without slowing down the operating speed, and the number of inverting amplifier circuits and current amplifier circuits can be reduced. It is possible, and the increase in the square tube area can be made even smaller.

So far, we have explained the parallel type memory cell configuration in which memory cells (MOS)/registers are connected in parallel between the bit line and the voltage ffg terminal. A similar configuration is also possible for a series-parallel type that is connected in parallel to the wire. Furthermore, configurations according to the present invention are possible in addition to the embodiments. For example, the configuration shown in FIG. 3 is one in which two parallel first bit lines are commonly connected via a selection circuit. It is also possible to connect a total of four bit lines in common, and it is also possible to increase the number of parallel first bit lines. Further, in the embodiments, individual explanations have been made regarding the circuit configuration or structure, but a combination of these may also be possible.

[Efficacy of invention]

The present invention uses a plurality of bit line groups as bit lines, and connects one or more stages in series in which a first bit line is connected to a second bit line via a current amplification circuit, thereby achieving a small memory cell size. A high-speed read operation can be achieved by operating the first bit line II at a high speed with the current capacity and operating the second bit line with a large current amplified by the current amplifier circuit. Also, the load capacitance of the second bit line is the capacitance due to the wiring, the capacitance of the output section of the divided first bit line, and f
The capacitance of a single bit tlA of Jl is 9, and the capacitance of the second bit line is significantly reduced and the memory cell is driven by the amplified current, so high-speed operation is possible without dividing the memory cell array. This can be achieved without increasing the chip area. Furthermore, since the capacitance of the bit line is reduced, current consumption due to the bit line load capacitance can also be reduced. Furthermore, by making the bit line have a multilayer structure, which is the structure of the present invention, the above-mentioned high speed can be achieved without increasing the chip surface area.
By reducing the wiring capacitance of the bit lines, higher speeds and lower current consumption are possible. In addition, by making the bit lines multi-layered and making the first bit line a polysilicon material, it is possible to configure the memory cells with the minimum pitch of the design dimensions, similar to the gate material of the MOS transistor that is the memory cell. It is possible to significantly reduce the memory cell size.

An inverting amplifier and an MO3 transistor for charge control are added to the current amplification circuit which is another configuration of the present invention. By achieving stabilization of about 1ffi, it is possible to achieve higher speeds and to reduce the number of bit line divisions, making it possible to realize a high-speed semi-quadramid storage device without increasing the chip area. In addition, by using a multi-stage configuration with only the first bit line and second bit line, it is possible to create an optimal configuration according to the memory capacity. It is possible to realize a high-speed semiconductor memory device with a small size.The present invention is an MROM using a semiconductor.

EPROM, E” FROM, DRAM.

It can be applied to various memory devices such as SRAM.

[Brief explanation of drawings]

1, 1T2 and 3 are examples of the circuit configuration of the present invention.
FIG. 4 is a plan view of a memory cell portion according to an embodiment of the present invention, and FIG. 5 and FIG. 6 are diagrams showing other embodiments of the circuit configuration of the present invention. 1...Sense amplifier 3.4...Current amplifier circuit 5.6...Memory self, 8.34.35...First bit line 11.12.
...Second bit line 15.1θ...Column decoder output line 17.18...
・Word gland 32.33...MO8 transistor for first bit i selection 3B, 44...Gate material 37.38...Polysilicon material 39.40...Al 41...Polysilicon material AI contact hole 42...Hole for buried contact 43.45...
・Level difference in oxide film forming MOS transistor 48...m3 bit line 49.50...Current amplification circuit 61...Inverting amplifier 56...MO5 transistor RO 2 for charging ffl control...
・Current amplifier circuit and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Tsutomu Mogami and 1 other person No. 1 T2 31st

Claims (1)

[Claims] In a semiconductor memory device in which memory cells composed of MOS transistors are selected by word lines and bit lines arranged in a matrix, and information of the selected memory cells is read by a sense amplifier, the bit lines are composed of a plurality of bit line groups, A configuration in which a plurality of first bit lines are connected to a second bit line via a current amplification circuit is directly connected in one or more stages, and the first bit line is connected to the second bit line through a current amplification circuit. 1. A semiconductor memory device, comprising: a bit line charge control transistor; the first bit line is connected to a memory cell; and the final stage bit line is connected to the sense amplifier via a bit line selection circuit.