JPH01280353A - Read-only semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a device which can shorten the turnaround time by writing a piece of information by forming a semiconductor film, containing an impurity, used to connect source-drain semiconductor regions on a word line selectively and in a self-aligned manner with reference to the word line. CONSTITUTION:In a read-only semiconductor memory device having series- connected MISFET rows Q1 to Q4, Q5 to Q8 which have been constituted of two or more word lines WL1 to WL4 extended mutually in parallel and of semiconductor regions 6a to 6l constituting a source region and a drain region, in the mutually adjacent word lines WL1 to WL4, formed in a direction nearly perpendicular to the word lines WL1 to WL4, a piece of information is written by forming a semiconductor film 7, containing an impurity, used to connect the semiconductor regions 6a to 6l on the second word lines WL1 to WL4 selectively and in a self-aligned manner with reference to the word lines WL1 to WL4. For example, a polycrystalline Si film 7 is doped selectively with an n-type impurity such as phosphorus; this impurity is transformed into a low- resistance n<+> type; then, a piece of information is written.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a read-only semiconductor memory device, and in particular,
Mask ROM (Read Only Memory)
It is suitable for application to.

[Summary of the invention]

The present invention includes a plurality of word lines extending parallel to each other, and a semiconductor region forming a source region and a drain region formed between the word lines adjacent to each other in a direction substantially perpendicular to the word lines. Series connection MISF
In a read-only semiconductor memory device having an ET string,
By writing information by selectively forming a semiconductor film containing impurities connecting the semiconductor regions on the word line in a self-aligned manner with respect to the word line, the turnaround time can be reduced. This makes it possible to shorten the time.

[Conventional technology]

Mask ROM is an R to write information during its manufacturing process.
It is an OM, and its memory cells are usually configured with MISFETs. A NAND type mask ROM is known as a type of mask ROM. This NAND type mask R
OM consists of multiple MISFETs connected in series.
It consists of an ISFET string, and information is usually written by
This is done by controlling the threshold voltage of the MISFET through ion implantation.

[Problems to be Solved by the Invention] However, in the conventional NAND mask ROM described above, since information is written in the steps before and after forming the gate insulating film of the MISFET, the time required from writing the information to completing the mask ROM is short. In other words, the turnaround time (
There was a problem that the turn around time was long.

In addition, in Japanese Patent Laid-Open No. 60-9157, in order to shorten the turnaround time, a NAND type in which information is written depending on whether or not metal wiring is provided to short-circuit semiconductor regions constituting a source region and a drain region. Mask ROM has been proposed, but this NAND type mask R
In OM, since it is necessary to contact the semiconductor region with metal wiring, the area of this semiconductor region becomes large.
Therefore, there are some practical problems, such as being disadvantageous in increasing the integration density of memory cells and requiring the use of two-layer metal wiring.

Therefore, an object of the present invention is to provide a read-only semiconductor memory device that can shorten turnaround time.

[Means to solve the problem]

The present invention provides a plurality of word lines (WL
, -WL, ) and mutually adjacent word lines (WL,
A series-connected MISFET array (Q, -Q4 and Q, ~Q,)
In a read-only semiconductor memory device having a semiconductor region (6a
~61) Semiconductor film (7) containing impurities connecting between
) is selectively formed in a self-aligned manner with respect to word lines (WL, -WL4) to write information.

[Effect]

According to the above-mentioned means, information can be written in a later process compared to the conventional technology in which information is written in the process before and after forming the gate insulating film, so the turnaround time can be shortened accordingly. I can do it.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. This embodiment describes the present invention as a NAND type mask ROM.
This is an example applied to.

FIG. 1A and FIG. 1B illustrate a NAN according to an embodiment of the present invention.
A D-type mask ROM is shown. Further, FIG. 2 shows an equivalent circuit of the NAND type mask ROM according to this embodiment.

As shown in FIG. 1A and FIG. 1B, the N
In the AND type mask ROM, a field insulating film 2 such as a 5ift film is selectively formed on the surface of a semiconductor substrate 1 such as a P-type Si substrate, thereby providing isolation between elements. This field insulating film 2
A gate insulating film 3 such as a Stow film, for example, is formed on the surface of the active region surrounded by. Code WL, -WL
Reference numeral 4 denotes word lines for selecting memory cells, and these word lines WL, -WL4 extend parallel to each other at predetermined intervals. Also, the symbols SL, , SL! is MISF, which will be described later.
This is a selection line for selecting an ET column. These word lines WL,
-WL4 and selection lines SL, SSL.

is formed by, for example, a polycrystalline Si film doped with impurities or a polycide film in which a refractory metal silicide film is formed on the polycrystalline St film removed. These word lines WL, ~W
For example, SiO□ is placed on La and the selection lines SL, SL.
An insulating film 4 like a film is formed, and sidewalls 5 made of an insulating material such as SiO□ are formed on the side surfaces thereof.

On the other hand, numerals 6a to 61 indicate, for example, n-type semiconductor regions formed in the semiconductor substrate 1. Among these, the semiconductor regions 6b to 6f and 6h to 61 are connected to the word lines WL, -W.
It is formed between L4 and selection lines SL, SL2,
The semiconductor regions 6a and 6g are formed on one side of the word line WL and on one side of the selection line SL, respectively. Further, these semiconductor regions 6a to 61 are formed in a direction perpendicular to the word lines WL, to WL and the selection lines SL, SL, st, and z in a self-aligned manner with respect to these.

Then, the gate electrode consisting of the word line WL, and the semiconductor region 6 formed on both sides of the word line WL.
An n-channel MISFETQ+ is constituted by the source region and drain region constituted by a and 6b. Similarly, the word line WL! and semiconductor regions 6b and 6c, the n-channel MISFETQt is connected to the word line WL.

and semiconductor regions 6c and 6d to form an n-channel MISFE.
TQ, is the word line WL4 and the semiconductor regions 6d, 6e.
An n-channel MISFET Q4 is configured. Similarly, n-channel MISFE TQs to Q8 are configured. Further, the selection line SL, the semiconductor region 6e,
6f, the n-channel MISFET T is formed, and the selection line SL and the semiconductor regions 6f and 6g form the n-channel MISFET T.
ISFETT is configured. Similarly, n channel M
ISFETT, ,T, is constructed. Note that the semiconductor region 6a is set to the ground potential Vts, and a bit line BL is in contact with the semiconductor region 6g via a polycrystalline Si film 7, which will be described later (see FIG. 2).

The semiconductor regions 6a to 61 have, for example, an n-type low impurity concentration portion below the sidewall 5, and therefore the above-mentioned n-channel MISFETQ+''Qg and T,
-T is a so-called LDD (Lightly D
It has an open drain structure. Note that these n-channel MISFETQ+-Qs and T1~
T4 does not necessarily have to have an LDD structure.

Reference numeral 7 indicates, for example, a P-type second layer polycrystalline Si film. This polycrystalline Si film 7 is used for n-channel MISFET Q I
- a MISFET string consisting of Q 4 and Tt, Tt, and n
Channel MISFETQs ~Qs and T3
, T4, respectively.

In the NAND type mask ROM according to this embodiment, the polycrystalline Si film 7 is selectively doped with an n-type impurity such as phosphorus (P), and thereby information is written (the polycrystalline Si film 7 The portions of the film 7 doped with impurities are doped). That is, the polycrystalline S
Information is transmitted by connecting the source and drain of a specific MISFET among the n-channel MISFETs QI to Q by the low-resistance n-type part containing n-type impurities in the i-film 7 on the word line. It is written. In this embodiment, the n-channel MI 5FETs Q+, Qs, Qs, Q, whose sources and drains are connected by the n-type portion of the polycrystalline Si film 7, are depletion type (normally-on type). ), and polycrystalline S
An n-channel MIS in which the source and drain are connected by the portion of the i-film 7 that remains p-type.
FETQz, Qa, Q7, and Qs are enhancement type (normally-off type). Therefore, the depletion type n-channel MI 5FETQ+, Q3, Q
For example, information ``1'' (or information ``0'') is added to s and Qb.
, enhancement type n-channel MISFETQ,
,Q4 ,Q? , Qa with, for example, information "0' (or information °1"), it is possible to write information.

Further, an n-channel MI 5 whose source and drain are connected by the n-type portion of the polycrystalline Si film 7
FETTI, T, is a depletion type n-channel MI whose source and drain are connected by the portion of the polycrystalline Si film 7 that remains p-type.
S F ETTz , T3 is an enhancement type.

Although not shown in the drawing, in reality, the polycrystalline Si film 7
A glabellar insulating film, a bit line, and a passivation film are formed thereon. This bit line is in contact with the polycrystalline Si film 7 through a contact hole C (see FIG. 1A) formed in this glabellar insulating film.

Next, the NAND according to this embodiment configured as described above
A method of reading out information from the type mask ROM will be explained. - As an example, consider a case where information is read from a memory cell constituted by an n-channel MISFETQ. In this case, the selection line SL.

is set to high level and the above n-channel MISFET! By turning on the above n-channel MISFETQ
! Select the MISFET column that includes. At the same time, the word line WLt is at low level, and the other word lines WL+
,WL! , WL4 is set to high level, and the information of the n-channel MI 5FETQ is read by detecting the current flowing from the bit line BL at that time.

Next, the NAND according to this embodiment configured as described above
An example of a method for manufacturing a type mask ROM will be described. Note that the following description will be made with reference to a cross-sectional view taken along line BB in FIG.

As shown in FIG. 3A, first, for example, a field insulating film 2 is formed by selectively thermally oxidizing the surface of a semiconductor substrate 1, and then the surface of an active region surrounded by this field insulating film 2 is heated, for example. A gate insulating film is formed by oxidation. Next, after sequentially forming a polycrystalline Si film and an insulating film such as an SiO□ film on the entire surface by, for example, the CVD method, these insulating films, the polycrystalline Si film, and the gate insulating film are patterned by etching. Gate insulating film 3 having a predetermined shape, word lines W L + to WL4, selection lines SL, , S
L and an insulating film 4 having a predetermined shape are formed.

Next, n-type impurities such as phosphorus (P) are ion-implanted into the entire surface at a low concentration, and as shown in FIG. 3B, the n-type semiconductor regions 8a to 8g are connected to the word lines WL, −
It is formed in a self-aligned manner with respect to WL4 and selection lines SL, SL. Next, after forming an insulating film over the entire surface, this insulating film is anisotropically etched in a direction perpendicular to the substrate surface by, for example, reactive ion etching (RIE) to form sidewalls 5.

Next, as shown in FIG. 3C, after forming, for example, a second layer of polycrystalline Si film 7 on the entire surface, a p-type impurity such as boron (B) is ion-implanted into this polycrystalline Si film 7. It is doped to make it p-type.

Next, this polycrystalline Si film 7 is patterned by etching to form the shapes shown in FIGS. 1A and 1B (FIG. 3D). Next, on this patterned polycrystalline Si film 7, a photoresist 9 having a predetermined shape with openings corresponding to the semiconductor regions 8a to 8g is formed, and then using this photoresist 9 as a mask, for example, An n-type impurity such as (As) is ion-implanted into the polycrystalline Si film 7. Next, after removing this photoresist 9, a heat treatment is performed to remove n in the polycrystalline St film.
Type impurities are diffused into the semiconductor substrate 1. As a result, semiconductor regions 6a to 6g having low impurity concentration portions below the sidewall 5 are formed in self-alignment with the word lines WL, -WL and the selection lines SL, SL.

After this, annealing is performed for electrical activation of the implanted impurities as necessary.
g indicates the semiconductor regions 8a to 8 in the step shown in FIG. 3B.
It is also possible to form the semiconductor substrate 1 by ion-implanting an n-type impurity such as As into the semiconductor substrate 1 at a high concentration after forming the semiconductor substrate 1.

Next, as shown in FIG. 3H, the polycrystalline Si film 7 in the portions corresponding to the enhancement type n-channel MISFETs Qz, Qa, and Tz is covered with a photoresist 10, and this photoresist 10 is masked. For example, an n-type impurity such as P is ion-implanted into the polycrystalline Si film at a high concentration. As a result, this polycrystalline Si
The film 7 is selectively turned into an n-type, and information is written therein. After this, the photoresist 10 is removed.

Next, a glabellar insulating film is formed on the entire surface, and a contact hole C is formed in this glabellar insulating film, and then a bit line BL made of, for example, aluminum is brought into contact with the polycrystalline Si film 7 through this contact hole C. Thereafter, a passivation film is formed to complete the desired NAND type mask ROM.

As described above, according to this embodiment, the portion of the polycrystalline Si film 7 containing n-type impurities allows the n-channel MI 5
Information is written by connecting the sources and drains above FETs Q+, Q3, Qs, and Qh. The only steps required to complete the mask ROM after writing this information are forming the eyebrow insulating film, contact holes, bit lines, passivation film, etc. Therefore, it is possible to complete the mask ROM in a short time after writing the information. can. That is, according to this embodiment, it is possible to shorten the turnaround time of a NAND mask ROM in which desired information is written. Moreover, since the portions of the polycrystalline Si film 7 containing n-type impurities are formed in a self-aligned manner with respect to the word lines wL and -WL4, the areas of the semiconductor regions 6b to 6f and 6h to 61 can be reduced. Therefore, it is possible to achieve high integration density of memory cells. Further, since only the bit line BL is used as the metal wiring, the reliability of the wiring is higher than that in the case of using two-layer metal wiring.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, ion implantation for writing information is performed using polycrystalline S.
It is also possible to form the i-film 7 and further form a glabellar insulating film on the polycrystalline Si film 7, and then conduct the process through the glabellar insulating film. In this way, it is possible to further shorten the turnaround time. Further, in the above-described embodiment, the P-type polycrystalline Si film 7 is selectively
Although information is written by forming the polycrystalline Si film 7 into a shape, after forming the non-doped polycrystalline Si film 7.
It is also possible to write information by selectively converting into n-type without converting it into p-type.

Furthermore, it is also possible to use other types of semiconductor films instead of the polycrystalline Si film 7.

〔Effect of the invention〕

As explained above, according to the present invention, information is written by selectively forming a semiconductor film containing impurities that connects semiconductor regions to each other on a word line. This can be carried out in a process near the end of the process, and therefore the turnaround time of a read-only semiconductor memory device in which desired information is written can be shortened. Furthermore, since the impurity-containing portion of the semiconductor film is formed in a self-aligned manner with respect to the word line, the area of the semiconductor region can be reduced, making it possible to achieve higher integration density of memory cells. can. Furthermore, since the semiconductor regions are connected by the semiconductor film, the metal wiring can be formed in one layer.

[Brief explanation of the drawing]

FIG. 1A shows a NAND type mask R according to an embodiment of the present invention.
A plan view showing the OM, FIG. 1B is a sectional view taken along line B-B in FIG. 1A, and FIG. 2 is a circuit showing an equivalent circuit of the NAND mask ROM shown in FIG. 111DA and FIG. figure,'
Figures 3A to 3E are NAs shown in Figures 1A and 1B.
FIG. 3 is a cross-sectional view showing an example of a method for manufacturing an ND type mask ROM in order of steps. Explanation of main symbols in the drawings 1: Semiconductor substrate, 2: Field insulating film, 3: Gate insulating film, 6a to 61: Semiconductor region, 7: Polycrystalline Si film, WL, -WL4: Word line, SL, , SL !
: Selection line, Q l-Q @, T t ~ T4 : n
Channel MISFET. Agent Patent Attorney Masatoshi Sugiura

Claims (1)

[Scope of Claims] A plurality of word lines extending parallel to each other, and semiconductor regions constituting source and drain regions formed between adjacent word lines in a direction substantially perpendicular to the word lines. In a read-only semiconductor memory device having a series-connected MISFET array configured, a semiconductor film containing an impurity connecting the semiconductor regions on the word line is selectively formed in a self-aligned manner with respect to the word line. A read-only semiconductor memory device characterized in that information is written by.