JPH01142931A - Coincidence detecting circuit - Google Patents

Abstract

PURPOSE:To correctly decide the coincidence between a current signal group and a reference signal group by inputting the outputs of subtracter groups which calculate differences between the current signal group and reference signal group and providing a maximum value circuit which finds the maximum value among them. CONSTITUTION:The coincidence detecting circuit consists of subtracter groups 211-219 and the maximum value circuit 32 which finds the maximum value among the outputs of the subtracter groups. Data d11-d13, d21-d23, d31-d33, and d01-d09 are inputted as the signal groups to subtracters 211-219, which perform subtraction processing as to all the data and output respective differences. The outputs are inputted to the maximum circuit 32 to decide the maximum value among the differences, and the maximum value b21 is outputted. Consequently, when only one signal of a signal pattern whose coincidence is detected has no correlation, the difference of the one signal having no correlation is detected by the maximum value circuit 32, so correct coincidence detection is performed.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a coincidence detection circuit that can be used for pattern matching used in image recognition, etc. ◎ Prior art In recent years, image processing technology has been applied in many fields. Among these, pattern matching technology in image recognition has become widely used due to the enhancement of ICs and lower prices.◎ Below, with reference to the drawings, we will introduce the matching technology used in conventional pattern matching. The detection circuit will be explained.

FIG. 2 shows a conventional coincidence detection circuit.

In FIG. 2, 211 to 219 are the current signal group d01 to d09 for coincidence detection and the reference signal group d11 to d13 for coincidence detection.
．． d21-d23. The subtracter 0 or 31 that subtracts d31 to d33 is an adder that adds the difference output from the subtracters 211 to 219, and outputs the addition result as b21. The operation of the detection circuit will be explained below. First, the current signal group d01 to dos for coincidence detection has a 3×3 configuration, and therefore the group of reference signals for coincidence detection d11 to d13. d21-d23.
d31 to d33 consist of nine current signal groups for coincidence detection d01 to dos are reference signal groups for coincidence detection d11 to d1
3. d21-d23. The outputs b111 to b119 of the zero subtractors 211 to 219 that perform subtraction between the pixels corresponding to d31 to d33 by the subtracters 211 to 219, respectively, are added by the adder 31. At this time, the output b2 of the adder 31
1 represents the correlation between the current signal group for coincidence detection and the reference signal group for coincidence detection, so for example, the output b21 of the adder 31
By setting a threshold value in , it becomes possible to determine whether or not the current signal group for use in a negative number structure and the reference signal group for coincidence detection match.

Problems to be Solved by the Invention However, in the above configuration, since a match is detected by adding the outputs of the subtracters, for example, even if only one signal of the signal pattern to be detected as a match has no correlation, other signals may be detected. Since it is added to the signal component, a malfunction occurs in which it is determined that there is a match even though there is no match, and it is not suitable for correctly detecting a match. In view of the above problems, the present invention has been developed by: The present invention provides a coincidence detection circuit that can accurately detect coincidence.

Means for Solving the Problem In order to achieve this object, the coincidence detection circuit of the present invention inputs a group of subtracters that takes the difference between a group of current signals and a group of reference signals, and the outputs of the group of subtracters, and It consists of a maximum value circuit that calculates the maximum value at .

Effect: This configuration enables correct detection of coincidence between the current signal group and the reference signal group.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a coincidence detection circuit in an embodiment of the present invention. In FIG. 1, 211 to 219 are subtracters, b111 to b119 are the outputs of the subtractors 211 to 219, and 32 are outputs b111 to b of the subtractors 211 to 219.
This is a maximum value circuit that finds the maximum value among 119.

The operation of the coincidence detection circuit configured as described above will be explained below.

First, data d11 to d13 shown in FIG. d21~d
23. d31 to d33 and d01 to do9 are input as a signal group to subtracters 211 to 219, subtraction processing is performed on all data, and the respective differences are output.

Each difference is input to the maximum value circuit 32, which determines the maximum value among the input differences, and outputs the maximum value as an output b21. As a result, for example, when only one signal of a signal pattern to be detected as a match has no correlation, the maximum value circuit 32 can detect the difference between the uncorrelated signals, making it possible to correctly detect a match.

In this embodiment, the number of reference data groups is nine, but the number of reference data can be increased using a similar method.

Effects of the Invention As described above, the present invention includes a subtracter group that takes the difference between a current signal group and a reference signal group, and a maximum value circuit that inputs the outputs of the subtracter group and calculates the maximum value among them. In particular, it is possible to correctly detect a match, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a coincidence detection circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional coincidence detection circuit. 211-219...Subtractor, 31...
Maximum value circuit O Name of agent Patent attorney Toshio Nakao et al. 16th
1 Figure 32-11 Keidai 4 Rin Off W'Az/I~? t(1-system η

Claims (1)

[Claims] A group of subtracters that take the current signal group and a reference signal group as input and take the difference between them, and a maximum value that takes the outputs of each of the subtracter groups as input, calculates the maximum value among them, and outputs the maximum value. A coincidence detection circuit comprising a circuit.