JP3076391B2 - Overflow processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overflow processing circuit, and more particularly, to an overflow processing circuit for performing overflow processing peculiar to image processing.

[0003]

2. Description of the Related Art A conventional overflow processing circuit is capable of performing an addition / subtraction operation in which overflow processing is performed by a one-time operation, and cumulative addition and accumulation subtraction in a case where the number of overflows is a subtrahend. .

The overflow processing method by the overflow processing circuit includes a method of extending one bit to a higher order and a method of sufficiently expanding the number of bits. In the method of extending the upper one bit, the operation is performed after extending the upper one bit, and the overflow is positive if the upper two bits of the result are 01, overflow if the upper two bits are 10, overflow if the upper two bits are 11 or 00. Detect if not. If an overflow is detected, the output is replaced with the maximum sign of the same polarity as the original operation result. However, if the final result does not inherently overflow in the accumulative operation, an erroneous result will be generated instead. This is because the overflow of the accumulation operation occurs only when the number of times exceeding the positive maximum value differs from the number of times exceeding the negative maximum value. Thus, by counting these times, correction is performed only when a true overflow occurs.

FIG. 3 shows a circuit for performing overflow processing by extending one bit to the higher order. The overflow process of calculating two n-bit values will be described with reference to FIG.

First, the data a32 and data a33 selected by the selector 300 are transmitted to the bit extension circuit 30.
One bit is extended upward by one. The expanded data is operated on by the adder 302, and the operation result and the result clamped by the overflow processing circuit 304 (to be described in detail later) are input to the selector 305. At the same time, the operation result of the adder 302 is cut off by the bit extracting circuit 306 with the upper one bit, and is stored in the register 307. Here, the clamp is a process of replacing the data with a maximum value or a minimum value that can be represented by the bit length of the data. The data a32 and a33 are data that does not overflow.

In the second and subsequent operations, the same processing is performed on the data a31 and data a33 selected by the selector 300. Whether to clamp or not is determined by signal 3
03. When clamping is performed, the result clamped by the overflow processing circuit 304 is selected. When clamping is not performed, the operation result of the adder 302 is selected, and the selected value is output through the selector 305.

Next, details of the overflow processing circuit 304 will be described with reference to FIG. The overflow processing circuit 304 determines an overflow from the two most significant bits of the operation result.

The result of the operation is an overflow processing circuit 304.
Input. In the overflow determination circuit 400, it is determined that the overflow has occurred when the upper 2 bits of the input operation result are 01, the overflow has occurred when the upper 2 bits are 10, and the overflow has occurred when the upper 2 bits have been 00 or 11. If the overflow is positive, the register 401 holding 1 in advance is selected by the selector 404. If the overflow is negative, the register 402 holding -1 is selected.
If no overflow occurs, the register 403 holding 0 is selected. An adder 406 performs an addition operation on the selected value and the value of the register 405. In the case of the accumulation operation, this addition operation is repeated.

As the addition operation is repeated, the value of the register 405 is counted up when the data overflows positively, and is counted down when the data overflows negatively. That is, the register 405
Holds the difference between the number of positive overflows and the number of negative overflows. As a result, it is possible to determine whether the contents of the register 405 are positive or negative and whether the overflow of the accumulation operation is positive or negative. Here, register 4
05 is defined as an overflow counter.

The output of the adder 406 is the clamp judgment circuit 4
07, the register 408 holds the maximum positive value if the value is positive, the register 409 holds the maximum negative value if the value is negative, and the input of the overflow processing circuit 304 if the value is zero. The value 410 is selected and output by the selector 411.

However, such overflow processing is based on continuous addition, and when a subtraction is performed with the value causing the overflow as a decrement, the register 40 is used even if the overflow code is determined.
Since the sign of the overflow count in 5 is not inverted, accurate processing cannot be performed.

Further, the output value cannot be selected during the processing so that the overflow counter value held in the register 405 always becomes positive or zero. Therefore, the cumulative overflow process cannot be performed at the time of the absolute value calculation, and the overflow process of the absolute value calculation cannot be performed.

In preprocessing such as filtering, affine transformation, and fast Fourier transform in image processing, or postprocessing such as image recognition, histogram processing, and labeling, an operation for subtracting an overflowing value and an absolute value operation are required. It is. For some time, an overflow processing circuit capable of performing such an operation has been desired.

[0015]

As described above, in the conventional overflow processing circuit that performs processing by extending one bit to the higher order, subtraction in which the number of overflows is a subtraction is performed.
In addition, there is a problem that the absolute value calculation of the number causing the overflow cannot be performed accurately.

Accordingly, the present invention has been made in view of such a conventional situation, and an object of the present invention is to provide a method of extending one bit to a higher order, in which the number of overflows is subtracted by subtraction. And an overflow processing circuit capable of performing accurate processing even for the calculation of the absolute value of the number causing the overflow.

[Structure of the Invention]

[0018]

Means for Solving the Problems In order to achieve the above object, a first aspect of the present invention is to provide a means for extending an effective digit of an arithmetic unit by one bit to a higher order to detect an overflow, Counting means for counting the difference between the number of times overflow has occurred negatively, and in the case of subtraction in which the number causing overflow is a subtraction, the value of the counting means is used if the result of the operation is positively overflowing. Add one to the two's complement,
Means for adding -1 to a value obtained by taking a two's complement to the value of the counting means when an overflow has occurred negatively.

A second aspect of the present invention is a means for performing an overflow detection by extending an effective digit of an arithmetic unit by one bit to a higher order, and calculating a difference between the number of times an overflow has occurred positively and the number of times an overflow has occurred negatively. Counting means for counting, and when the number which is negatively overflowing is to be subjected to absolute value calculation, the value of the counting means is 2's complement when the calculation result is positively overflowing. And a means for adding -1 to a value obtained by complementing the value of the counting means with a two's complement when an overflow occurs negatively.

[0020]

With the above arrangement, the present invention holds the value of the difference between the number of times that the overflow has occurred positively and the number of times that the overflow has occurred negatively in a register defined as an overflow counter. In the case of subtraction in which the number causing overflow is a subtraction, and when the operation result is exactly overflowing, 1 is added to the value obtained by taking the 2's complement of the register value, that is, the value whose sign is inverted. Add. Conversely, if an overflow has occurred negatively, -1 is added to the value obtained by inverting the sign of the register value.

In the case where the number causing a negative overflow is the target of the absolute value calculation, and the result of the calculation is a positive overflow, the value of the register is two's complement, That is, 1 is added to the sign inverted. Conversely, when an overflow occurs negatively, -1 is added to the value obtained by inverting the sign of the register value.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an overflow processing circuit of the present invention, and FIG. 2 is a configuration diagram of a circuit that performs an absolute value calculation using the overflow processing circuit.

First, an overflow process for an operation in which the number of overflows is reduced is shown in FIG.
This will be described with reference to FIG. The overflow processing circuit shown in the figure has a configuration in which a selector 102 and a positive / negative sign inverter 103 are added to the conventional overflow processing circuit shown in FIG.

The sign inverter 103 has a register 104
The sign of the value of is inverted. The selector 102
If the number of overflows is a subtraction, the output of the sign inverter 103 is selected. Otherwise, the output of the register 104 is selected.

With such a configuration, the signal 10
Whether the value of the register 104 holding the number of overflows up to the previous time is selected or the value obtained through the sign inverter 103 is selected based on 1 and the selected value is added through the selector 102 to the adder 105. B
Input to one input. That is, the value of the sign inverter 103 is input to the b1 input when the calculation is performed with the overflowing number as a subtraction number, and otherwise, the value of the register 104 is input.

On the other hand, the upper two bits of the input value of the overflow processing circuit are judged by the overflow judgment circuit 100. If the upper 2 bits are 01,
The value 1 of the register 107 is selected because it is determined that the overflow has occurred positively in the current operation, and the value of the register 108 is −10 in the case of 10, because it is determined that the overflow has negatively occurred in the current operation. 1 is selected. 11,0
In the case of 0, it is determined that overflow has not occurred at that time, and the value 0 of the register 109 is selected. The selected value is input to the a1 input of the adder 105.

The result of the addition by the adder 105 is input to the register 104 and the clamp determination circuit 110
Is input to In the clamp determination circuit 110, the adder 1
It is determined whether the output of the register 05 is positive, negative or zero. If the output is positive, the register 111 holding the positive maximum value is set. If the output is negative, the register 112 holding the negative minimum value is set to 0. In this case, the input value 113 of the overflow processing circuit is selected. The selected value is output from the selector 114.

Next, calculation of the absolute value of the difference between the two numbers a and b
The overflow processing of b | will be described with reference to FIG. The circuit in the figure includes subtractors 201, 202, 2
Input overflow processing circuit 204 and register 2
06. The subtracter 201 performs ab on the input data a and b, and the subtractor 202 performs ba.

The overflow processing circuit 204 takes in the two operation results output from the subtracters 201 and 202 and makes a clamp judgment. In addition, it has a function of outputting a signal 205 indicating which one of ab and ba is to be selected and outputting a clamped value d when no clamping is performed.

At first, the data a21 and the data b2 selected by the selector 200 are
1, 202. From the second time on, data a22
And data b2 are input to the subtracters 201 and 202. In each of the subtracters 201 and 202, ab and ba are simultaneously set.
Is calculated. The simultaneous operation of the operations in parallel is for speeding up.

The two calculation results are input to the selector 203 and simultaneously to the overflow processing circuit 204. The overflow processing circuit 204 outputs a signal 205 indicating which one of ab and ba is to be selected and a clamped value d when no clamping is performed. Based on the signal 205, one of ab and ba is selected by the selector 203 and output as a value c. This value c is output to the selector 208 and
6 is held. And when clamping, the value d
However, if not, the value c is selected and output by the selector 208 under the control of the clamp control signal 207.

Next, the overflow processing circuit 204 in the absolute value calculation will be described. Since the value of the overflow counter (register 104) must always be positive or zero, a special process is performed to count the number of overflows and obtain the output value c during the accumulation operation. This will be described using Table 1 as an example.

The first input a2 of the absolute value calculation in FIG.
2 is b, the second input b2 is a, and b is the result of the previous cumulative operation. Also, it is assumed that a does not overflow.

The columns ab and ba indicate the state of the calculation result of ab and ba, where 0 indicates a state where no overflow has occurred, + indicates a state where a positive overflow has occurred, and
“-” Indicates a state of overflowing negatively. The column b shows the state of the overflow of the accumulated operation results up to the previous time, and the column flgout shows the value of the overflow counter (register 104) after the absolute value operation. flg (n-
1) represents the value of the overflow counter up to the previous time,
flg (n-1) represents a value obtained by inverting the sign of the value of the overflow counter up to the previous time, that is, a value obtained by taking a two's complement. The last column indicates a value to be output as a result of the absolute value calculation.

When the input b does not cause an overflow (when b is 0) and the operation result does not cause an overflow (when both ab and ba are 0)
Outputs the positive one of ab and ba as the result of the absolute value operation. Here, the term “positive” includes a case in which an overflow occurs and an apparently negative value occurs. When the input b does not overflow and the operation result exactly overflows (ab or b-
When a is +), 1 is added to the overflow counter, and when no overflow occurs, the previous value is held in the overflow counter.

When the input b has a negative overflow (when b is-), ab is output as a result of the absolute value calculation. When the operation result of a-b causes a positive overflow (when a-b is +), 1 is added to a value obtained by inverting the sign of the overflow counter (that is, a value obtained by taking 2's complement), and a negative value is obtained. When an overflow occurs (when a-b is-), -1 is added to a value obtained by inverting the sign of the overflow counter (that is, a value obtained by taking 2's complement). When no overflow has occurred (when ab is 0), a value obtained by inverting the sign of the previous value is held in the overflow counter.

If the input b is overflowing (b is +), ba is output as the result of the absolute value calculation. When the operation result of ba is positively overflowed (when ba is positive), 1 is added to the overflow counter, and when the overflow is negatively generated (when ba is negative), Add -1 to the overflow counter. When no overflow has occurred (when ba is 0), the previous value is held in the overflow counter.

As the clamping process, the number of overflows
If flgout (n-1) is 0, the value selected in Table 1 is output as it is, and if 0, the maximum expressible positive value is output.

[0039]

[Table 1]

[0040]

As described above, according to the overflow processing circuit of the present invention, when an overflow occurs, the value of the overflow counter is set to 2's complement.
As a result, the calculation in which the value causing the overflow is a subtraction and the absolute value calculation can be accurately performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of an overflow processing circuit according to the present invention.

FIG. 2 is a configuration diagram of a circuit that performs an absolute value calculation using the overflow processing circuit of the present invention.

FIG. 3 is a configuration diagram of a conventional circuit that performs overflow processing by extending one bit to an upper order.

FIG. 4 is a configuration diagram of a conventional overflow processing circuit. .

[Explanation of symbols]

100 overflow determination circuit 102, 114, 200, 203, 208 selector 103 positive / negative sign inverter 104, 107, 108, 109, 111, 112, 2
06 Register 105 Adder 110 Clamp determination circuit 201, 202 Subtractor 204 Overflow processing circuit

Claims (2)

(57) [Claims] 1. Means for detecting an overflow by extending an effective digit of an arithmetic unit to a higher order by one bit, counting means for counting a difference between the number of times an overflow has occurred positively and the number of times an overflow has occurred negatively, In the case of a subtraction in which the number causing the subtraction is a subtraction, if the result of the operation has a positive overflow, 1 is added to the value obtained by taking the two's complement of the value of the counting means, and a negative overflow occurs. An overflow processing circuit comprising means for adding -1 to a value obtained by taking a two's complement to the value of the counting means when the counting is performed. 2. A means for detecting an overflow by extending an effective digit of an arithmetic unit to a higher order by one bit, a counting means for counting a difference between the number of times of overflow and the number of times of overflow, and a negative means. If the number causing an overflow is the target of the absolute value calculation, if the result of the calculation is a positive overflow, 1 is added to the value obtained by taking the two's complement of the value of the counting means, and An overflow processing circuit comprising means for adding -1 to a value obtained by complementing the value of the counting means with a two's complement when an overflow has occurred.