JPS6223317A - Frequency rate of variability based relay - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a frequency change rate relay, and more particularly to a frequency change rate relay provided for detecting changes in the frequency of a power system and protecting the power system.

[Technical background of the invention]

Although the frequency of the power system is always maintained constant, if the balance between the amount of generated power and the amount of loaded power in the power system is significantly disrupted due to a system failure or the like, the system frequency increases or decreases. In this case, the greater the degree of unbalance, the greater the frequency change rate, so this is detected by a frequency change rate relay and used as a fail-safe element when implementing system separation, power generation limitation, or load limitation.

Conventionally, for example, according to Japanese Patent Application Laid-Open No. 58-49039,
Detects one cycle period of AC input and stores the value,
When the frequency change rate is detected, the stored value is read out, an adder calculates a predetermined sampling period, and a comparison operation is performed.The frequency change rate detection calculation is performed every cycle, and operation verification is performed multiple times. A frequency change rate relay using a period measurement method has been proposed.

[Problems with background technology]

When applying the frequency change rate relay of the above-mentioned period measurement method to a power grid, it is desirable that the relay operating time be as fast as possible in order to improve the stability of the power grid. However, as shown in Figure 3, if the phase of the input AC waveform changes at point A due to a system fault, etc., and then changes in the opposite direction at point B due to fault removal after several ticks, the system frequency Even though there is no change in , the period measurement result increases or decreases due to the above-mentioned phase change. If the period increases at point A,
Assuming that the period decreases at point B, for example, when performing a comparison operation of two sampling periods that match nv every cycle,
The results are shown in Table 1.

Table 1 However, the symbol 0 shown in the results section of Table 1 means no change, ■ means an increase in the period, and θ means a decrease in the period.

As shown in Table 1, the determination time t2. t3 and tH,
At time t, the frequency falls (the period and frequency have a reciprocal relationship, and an increase in the comparison result means a frequency fall)
It is determined that the frequency increases from the determination time t4 to tγ. In order to avoid unnecessary responses at this time, the conventional technique is to increase the number of motion comparisons, that is, in this case, for example, it is necessary to determine whether there is an increase or decrease in the cycle nine or more times in a row to avoid unnecessary motions. Alternatively, methods can be considered such as increasing the span of the sampling period and canceling out the increase and decrease in the period, but either of these methods will lead to a delay in the operation time when detecting the actual system frequency change, and the system There was a problem that this was not acceptable for improving stability.

[Purpose of the invention]

The present invention has been made to solve the above problems, and provides a frequency change that does not require unnecessary responses to multiple sudden phase changes and can detect actual system frequency changes at high speed. The purpose is to provide rate relays.

[Summary of the invention]

In the present invention, the increase or decrease in the period between predetermined cycles is sequentially determined with respect to the input AC voltage, the determination result is introduced, and thereby it is determined whether the increase or decrease in the period is monotonous,
By allowing the transmission of the protection output as a system frequency change only when this is monotonous, the number of judgments is minimized and the relay operation time is increased, and the relay operation time is increased as much as possible. This was done so that no unnecessary response would be made.

[Embodiments of the invention]

Examples will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a frequency change rate relay according to the present invention. FIG. 1 has a microcomputer circuit as a component, and has a configuration in which the system voltage from a system 1 is introduced into a frequency change rate relay 3 via an auxiliary transformer 2.

The frequency change rate relay 3 includes an input circuit 4 that measures the period of the grid voltage waveform output from the auxiliary transformer 2, and a central processing circuit 5 that performs arithmetic processing to be described later according to the period measurement result from the input circuit 4. , a memory 6 that stores cycle results and processing procedures of the central processing circuit 5, a setting circuit 7 that stores setting values, and an output circuit 8.

FIG. 2 is a flowchart illustrating the arithmetic processing contents of the arithmetic processing circuit. For convenience of explanation, it is assumed that the frequency change rate calculation is performed by comparing two adjacent sampling periods every cycle.

In FIG. 2, first, in step 21, the period measurement result from the input circuit 4 is read and stored in the memory 6. In the Stella f22, the latest 2-san shilling cycle (T at the time of to in Fig. 3) is selected from the cycle results stored in the memory 6.
l) and the two preceding cycles (time to in FIG. 3 is To), and calculate the difference between them. In step 23, a set value is read from the setting circuit 7, and a comparison is made between the read set value and the absolute value of the difference calculation result obtained by the stellar f22. If the comparison result in step 23 is less than the set value (setting company), the input frequency is assumed to be unchanged and step F, which will be described later, is performed.
Move on to 3. On the other hand, if the comparison result in Stella f23 is greater than or equal to the set value (set difference), it is determined that the input frequency change rate is greater than or equal to the set value, and the process moves to the next Stella 7'F1.

In step 24 in step F2, the difference calculation result performed in step 22 is determined to be positive or negative, and if it is positive, the process moves to step 25 and the period is increased (frequency is decreased).
If it is negative, the process moves to step 26 where the cycle is decreased (frequency is increased) and stored in the memory 6 as the current determination result.

Next, in step 27 in step F2, the result of the previous judgment is read from the memory 6, and further in step 28, the current judgment result is compared with the judgment result of the previous one. If the comparison result is in the opposite direction, it is assumed that the cause of this change is not a monotonous change in the input frequency, but a temporary period change due to a phase change at the time of a system failure, and the process proceeds to step 29. to cancel this judgment.

Here, the processing contents of Stella fF2 will be explained in more detail with reference to the example of FIG. 3 with reference to the cloth 1. First, when the cycle increases due to a phase change at point A in Fig. 3, judgment time 1
．． Now, the difference calculation T4-'r! Since it is determined that the cycle has increased (result term ■ in Table 1), and F2, which is the comparison destination, has not changed at the judgment time point two times before, and is determined to be the result term O in Table 1, memory 6 has Judgment time t! In this case, it is stored as an increase in the period (item 2 of the result of judgment time t2 in Table 1). Furthermore, at the next judgment point t3, a comparison operation of 'r5-'r' is performed.

It is stored as a cycle increase in exactly the same way (judgment time t3 in Table 1
Results section ■). Next, at judgment time t4, F6-F4
By calculating the difference between υ, it is determined that the cycle has decreased (item e of the result of the determination time t4 in Table 1), but compared to the current determination time t4, at the previous determination time t2, the comparison target F4 is determined to have increased the cycle. ,
The determination result is in the opposite direction to the period reduction which is the determination result at the current determination time t4. Therefore, the determination result at the current determination time t4 in this case is canceled.

Thereafter, by repeating the same determination routine, the determination results are stored in the memory 6 as shown in Table 2.In other words, at the determination time t4 in Table 1, it was determined that the period decreased e; Since it was determined that the period increased at the previous judgment point t2 based on the previous judgment point t2, this judgment result was in the opposite direction.Therefore, as shown in Table 2, the judgment result e at the judgment point t4 was canceled and it was set to 0 with no change. . Even at the next judgment point t11, at the current judgment point tII, the judgment result is a decrease in the period e, but at the judgment point t before the previous time, based on the current judgment point ts, the judgment result is an increase in the period ■. Therefore, the determination result is in the opposite direction as above. Therefore, as shown in Table 2, canceling the judgment result e at the judgment time t4,
It was set as O with no change.

Finally, in step F3, in Stella 7'30,
Verify the motion multiple times using the judgment results stored so far (in the example in Figure 3, the minimum is 3 (4), and since the number of changes in the same direction is less than 3 times (2 times), unnecessary responses may be made. Never.

As explained above, the judgment results of conventional frequency change rate relays are as shown in Table 1. Therefore, in order to avoid unnecessary responses to phase changes, a detection method that detects only the absolute value of the change and does not look at the direction is necessary. Therefore, motion verification is required at least nine times, and a method for detecting changes in the same direction also requires motion verification at least five times.

On the other hand, according to the present invention, the judgment results are shown in Table 2, and in order to avoid unnecessary responses to phase changes, it is sufficient to perform operation verification at least three times, and in the case of actual frequency changes, compared to the conventional method, It is possible to send out protection outputs at extremely high speeds.

In the above-mentioned embodiment, a method is described in which a comparison operation is performed for two sampling periods every cycle, but the method is not limited to this, and there is also a method that performs a determination every cycle, or a method that performs a comparison operation for various sampling periods. It may be applied to any method.

〔Effect of the invention〕

As explained above, according to the present invention, the increase or decrease in the period between predetermined cycles is sequentially determined for the input AC waveform and stored for a predetermined period, and it is determined whether the increase or decrease in the period is monotonous. If it is not monotonous, it is configured to cancel the judgment result for that time, which reduces the number of false judgments due to temporary period changes and reduces the number of motion verifications to prevent unnecessary responses. can. Therefore, it is possible to provide a highly reliable frequency change rate relay that does not need to react unnecessarily to increases and decreases in the period due to phase changes, etc., and can send out a protective output at high speed when the system frequency actually changes.

[Brief explanation of drawings]

Fig. 1 is a block configuration diagram of an embodiment of the frequency change rate relay according to the present invention, Fig. 2 is a flowchart explaining the processing contents of the central processing circuit, and Fig. 3 is a diagram showing the case where a phase change occurs in the input waveform. It is a waveform diagram explaining the state of periodic change. 1... System, 2... Auxiliary transformer, 3
...Frequency change rate relay, 4...Input circuit, 5...
-Central processing circuit, 6...memory, 7...setting circuit, 8...output circuit.

Claims (1)

[Claims] In a frequency change rate relay that calculates the period of the input AC waveform by counting the reference clock and uses this quantized signal to calculate and detect abnormalities in the frequency of the power system, the period increases or decreases between predetermined cycles with respect to the input AC waveform. a first means for sequentially determining, a second means for introducing the determination result of the first means and determining whether an increase or decrease in the period according to the determination result is monotonous; A frequency change rate relay comprising: third means for permitting transmission of a protection output only when the determination result is monotonous.