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Priority to JP3631988UpriorityCriticalpatent/JPH0449723Y2/ja
Publication of JPH01142061UpublicationCriticalpatent/JPH01142061U/ja
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Publication of JPH0449723Y2publicationCriticalpatent/JPH0449723Y2/ja
System for guaranteed CPU bus access by I/O devices monitoring separately predetermined distinct maximum non CPU bus activity and inhibiting I/O devices thereof