JPH0114076Y2 - - Google Patents

Description

[Detailed explanation of the idea]

This invention is based on envelope attack,
The present invention relates to an envelope generator for an electronic musical instrument that generates various envelopes by time-controlling a speed parameter representing the speed of release and has a reduced number of input terminals. Conventionally, methods for digitally generating an envelope can be roughly divided into two methods: a method in which the waveform is stored, and a method in which the waveform is approximated by a function. For example, envelopes with different shapes,
52-27621, which is used for the effect of temporally changing the harmonic coefficient of a musical tone, and an envelope for amplitude modulation, etc. The former method requires a large amount of memory and is uneconomical, and the latter method also uses CR to control the oscillation frequency of the oscillator, and many types of It is necessary to have an oscillator corresponding to the timbre of the envelope, and the number of input terminals also increases. Therefore, the current situation is that it has no choice but to be quite limited due to configuration and price constraints. In response, a method was proposed and simplified in which one digital number is selected from a group of digital numbers, accumulated by an accumulator, and the envelope calculation timing is obtained from the multi-bit output. , also requires significant components associated with the accumulator. An object of the present invention is to provide an envelope generator for an electronic musical instrument that has a simple configuration, can arbitrarily set the envelope calculation timing, generate many types of envelopes, and has a reduced number of input terminals. In order to achieve the above object, the envelope generator for the electronic musical instrument of the present invention has the following functions:
Decay, split the release into multiple phases,
In an envelope generator for an electronic musical instrument that forms an envelope waveform through calculations at a predetermined timing, an envelope consisting of digital binary numbers is used to control the speed of the attack, decay, and release of the envelope that should be generated in response to key presses. speed parameter generating means for generating a speed parameter; decoding means for decoding the speed parameter from the speed parameter generating means to generate numerical data having a number of bits greater than the number of bits of the speed parameter; and when the envelope is in the attack phase. binary shift control means for sequentially shifting the numerical data from the decoding means according to the phase state and fixing the shift of the data when the envelope is in the decay and release phases; arithmetic means for accumulating data;
It is characterized by forming an envelope waveform whose speed is controlled by a speed parameter. The present invention will be described in detail below with reference to examples. FIG. 1 is an explanatory diagram of the principle of the present invention. As shown in the figure, in the present invention, the envelope is divided into a plurality of phases, for example, 12 phases (hereinafter referred to as phases). The attack portion of the envelope is divided into phases 1 to 4. The day-care section is from phase 5 to phase 8,
The pressed state of the key is stopped at phase 8,
It is represented by 12 phases from phase 9 to phase 12 in the release section after key release. The envelope data is then represented as a floating point number and divided into an exponent and a mantissa as shown in Table 1.

[Table] For example, if the maximum value is 1 or less, the maximum level of the envelope is represented by the exponent "000" and the mantissa "000". If 1000 x 2 ⁰ is 0db, the minimum level is the exponent "111" and the mantissa "000". 000” is 1000×2 ^-7 (−42db)
It is expressed as Then, the exponential characteristic of the envelope is formed using this floating point characteristic. That is, the decay and release parts can be easily formed by down-counting the mantissa part and up-counting the exponent part. The attack portion is obtained by shifting data in accordance with the phase using a binary shift circuit, which will be described later. A method of expressing and forming ADSR using binary floating point numbers as described above is described, for example, in Japanese Patent Application Laid-Open No. 54-1609 "Amplitude Generator for Electronic Organs" proposed by the present applicant.
Since it is disclosed in , the details are omitted. The most important point of the present invention is that the attack, decay, and release lengths are expressed as digital parameters, and these parameters are effectively applied to the envelope calculation means. The method of this calculation means is not particularly limited. Now, considering the release part, in order to be able to change the length of the release from 1 millisecond to 128 milliseconds, we divide this into discrete steps, for example, 32 steps.
Each position is expressed as a 5-bit binary number, and this is sent to the speed parameter decoder as an envelope speed parameter. SL×SC/RT SL: Relative sustain level where SL = (sustain level - minimum level) SC: system clock (Computation time) RT: Release time Here, RT/SC indicates the number of calculations during the release time. generates a value corresponding to . This value is the release time
It means the amount of displacement per each calculation cycle included in RT. Therefore, if a different speed parameter is given for each phase during release, the calculation time included in that phase allows the release to proceed according to the displacement. The same is true for DK. For example, if the sustain level is 0dB, the level at which the release ends, that is, the minimum level, is −
Assuming 42dB, the relative sustain level SL is SL=
0-(-42)=42dB. Assuming that the envelope calculation time is performed every 1ms,
SC=1×10 ^-3 (S) If the release time is 14ms
RT=14× ^10-3 (S) SL×SC/RT=42×1× ^10-3 /(14× ^10-3 )=3dB. For release (attenuation), system clock 1
By applying 3dB of attenuation to each point, a 14ms release can be created. Therefore, it is sufficient to select a value necessary for changing by -3 dB and give it as a displacement value. In this case, the displacement value is
It is expressed as an exponent of 000 and a mantissa of 100. This value does not correspond to Table 1. Here, the calculation for forming the envelope of the present invention will be explained. As mentioned above, for decay and release, the mantissa part is down-counted and the exponent part is up-counted. For example, if the current value is 0 dB, the exponent part is 000 and the mantissa part is 000. Assuming that 3 dB of attenuation is given in the release section as described above, the displacement value is calculated as shown in Table 2, with the exponent part being 000 and the mantissa part being 100.

[Table] In Table 2, the mantissa 100, which is converted into a two's complement in the quantile mantissa part, is added to the mantissa part 000 of the current value.
At this time, since no carry occurs from the mantissa part, it is determined that this is a borrow during subtraction, and 1 is added to the exponent part. 001 with the result of addition of the exponent part of the current value and displacement value and the borrow
becomes. Therefore, the calculation result has an exponent part of 001 and a mantissa part of 100, which is 1.5 x 2 ^-1 from Table 1, which is about -3 dB. Next, in the case of attack, if the current value is -39 dB, the exponent part is 111 and the mantissa part is 100. When increasing this by 9 dB, the displacement value is set to exponent part 001 and mantissa part 100, and calculations are performed as shown in Table 3.

[Table] In Table 3, if you add 111, which is the two's complement of the quantile index part 001, from the current value index part 111, it becomes 110.
becomes. (The carry of this result is rounded down.) Next, the mantissa part is obtained by adding the current value 100 and the displacement value 100.
000, resulting in a carry. The mantissa part of this attack is treated as a carry by addition, and the exponent part is subtracted by 1. Therefore, 110 minus 1 equals 101.
From Table 1, the exponent part 101 and the mantissa part 000 are 1.0×2 ^-5 , which is -30 dB. As described above, attack and
Calculations are performed to form a release envelope. FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention, and is a block diagram of an envelope generation circuit in which the above-mentioned speed parameter is applied to the above-mentioned floating point arithmetic circuit. In the same figure, in response to input of key data, the phase initial value generation circuit 11 generates the initial value of the phase of ADSR of the envelope explained in FIG. Used for control. Here, when the envelope phase is 1 to 8, when key-off data is input, the phase initial value generating circuit 11 is forcibly set to phase 9 and starts releasing whatever the current phase is. The value of this phase is determined by the phase decoder ADSR.
It is decoded by the control circuit 12 and used for phase transition control of required circuits within the system. One of them is a phase end value prediction circuit 19, into which sustain level data is input, and the predicted value of each phase end value is sent to a comparator 18, where it is compared with a value from an arithmetic unit (described later), and when they match, a match signal is output. It is sent to the phase decoder ADSR control circuit 12, 1 is added to the phase adder 13, and stored in the phase memory 10. It is sent to the phase decoder ADSR control circuit 12 via the phase initial value generation circuit 11, and is used for the next phase. Transition. Here, the sustain level data input to the phase closing price prediction circuit 19 is as follows:
This is variable data input from the outside, and the closing price of each phase in decay and release changes depending on this value. On the other hand, the part where the fall time changes in the release part or decay part is discretely divided into, for example, 32 parts, each position is represented by a 5-bit speed parameter, and the speed parameter at the desired position is input into the speed parameter decoder 23 and decoded. generates a displacement value of . This decoder 23 and the next binary shift circuit 20 are controlled by the phase decoder control circuit 12, and in the case of release and decay, the decoder output passes through the binary shift circuit 20 without being shifted and is sent to the addition/subtraction control circuit 21. The phase decoder ADSR control circuit 12 controls addition and subtraction to the arithmetic unit, and in the case of release and decay, it operates to add exponents and subtract mantissas as described above. An adder 16 and an adder 17 in the arithmetic section add and subtract data read from the exponent memory 14 and the mantissa memory 15, which store exponents and mantissas based on Table 1, using data from the addition/subtraction control circuit 21, and add and subtract data read from the mantissa memory 15 and the comparator 18. The data is sent to the data selection circuit 24. The comparator 18 uses the added exponent from the adder 16 and the subtracted mantissa from the adder 17 to the phase closing price prediction circuit 1.
9 and the computation is repeated until they match or exceed the final value. That is, the exponent from adder 16 and adder 1
input the mantissa from 7 to the data selection circuit 24,
This data is stored again in the exponent memory 14 and the mantissa memory 15 by the control signal of the phase decoder ADSR control circuit 12. Here, the phase memory 10, exponent memory 14, and mantissa memory 15 have the same number of words as the sum of the number of tones and the number of amplitude modulation effect envelopes. In this way, calculations are repeated for each phase to form a release or decay of length corresponding to the parameter expressed by the 5 bits described above. Note that as a function of the data selection circuit 24, for example, when the adder 16 overflows, the overflow is detected by the overflow detection circuit 28, and the data is transferred to the exponent memory 14.
Instead of sending this to the mantissa memory 15, control is performed to select the memory output or to select and send the initial amplitude value in the next phase from the phase initial amplitude value generating circuit 22. There are two cases of this overflow. One is when it becomes larger than the maximum value in attack calculation, and the other is when it becomes smaller than the minimum value in decay and release calculation. In the case of attack, the current value is -3dB exponent part 001 and mantissa part 100, and the displacement value exponent part 010 corresponds to 12dB.
If the mantissa part is 000, the current value + displacement value is -3 + 12
=9dB exceeds the maximum value of 0dB. Two's complement 110 of quantile exponent part 010 and current value exponent part
Adding 001 gives 111, where the exponent part is 111 and the mantissa part is 100.
According to Table 1, the value is approximately -39dB. Therefore, if no carry occurs from the exponent part at the time of attack, it is treated as an overflow. Similarly, if the current value is -3dB and the quantile exponent part is 001 and the mantissa part is 000, which corresponds to 6dB, then adding the two's complement of the quantile exponent part 111 and the current value 001 becomes 000, which causes a carry. However, the calculation result is exponent part 000 and mantissa part 100, and the maximum value is 0dB exponent part 000.
Since the definition of the mantissa part 000 is exceeded, this is also detected as an overflow and processed. Next, in the case of Decay and Release, the current value is approximately -
Considering the case where the exponent part 111 and the mantissa part 100 are 39 dB, and the displacement value exponent part 001 and the mantissa part 000 correspond to 6 dB, the current value minus the displacement value is -39-6=-45 dB, which is smaller than the minimum value. When the current value exponent part 111 and the displacement value exponent part 001 are added, it becomes 000 and a carry occurs. The result of this calculation is approximately +3 dB with an exponent part of 000 and a mantissa part of 100. Therefore, the exponent carry in Decay and Release is treated as an overflow. Next, in the case of an attack, the decoded data from the speed parameter decoder 23 is sent to the binary shift circuit 20. If the binary shift circuit 20 shifts the data to increase in accordance with the phase, a good attack shape can be obtained. for example,
During phase 1, the data from the speed parameter decoder 23 is shifted to the left by 2 bits, that is, shifted to quadruple. Next, in phase 2, the data is shifted to the left by 1 bit, that is, shifted to double the data. When phase 3 is reached, the data is sent without being shifted, and in phase 4, the data is set to be shifted to the right by 1 bit, that is, set to 1/2.
For example, if the quantile exponent part is 001 and the mantissa part is 000, which corresponds to 6 dB, when the phase is 1, the exponent part is 100 and the mantissa part is 000.
24dB at 000, exponent part 010 mantissa part in case of phase 2
000 is 12dB, phase is 6dB, phase 4 is the exponential part
000 and the mantissa part is 100, resulting in a displacement value of 3 dB. The same applies to other displacement values. Here, the comparison values from the phase closing price prediction circuit 19 are as follows: phase 1-12 dB exponent part 010 mantissa part 000, phase 2-6 dB exponent part 110 mantissa part 000, phase 3-
3dB exponent part 001 mantissa part 100, phase 4 exponent part 000
When the mantissa part is 000, an attack having the shape shown in FIG. 1 is formed. The envelope thus formed
The amplitude of each phase of the ADSR is sent to the decoder 25 and the binary shift circuit 26 as output data of the exponent memory 14 and the mantissa memory 15, and the floating point data in Table 1 is converted to normal fixed point digital data. An analog envelope waveform can be obtained from this using the DA converter 27. As explained above, according to the present invention, the attack, decay, and release of the envelope are set by speed parameters expressed as digital values, which are decoded and applied to any calculation means. This eliminates the need for multiple oscillators and accumulators to set the attack, decay, and release speeds as in the past, allowing the number of input terminals to be significantly reduced and making it compatible with integrated circuits. . Furthermore, according to the method of creating an envelope by setting speed parameters, decoding and calculating them, various envelopes can be created, such as envelopes with different shapes, envelopes for sliding formant filters, and envelopes for amplitude modulation. It has the advantage that envelopes etc. can be easily generated. By storing these parameters in an external storage device and reading and setting them appropriately, it is possible to form many types of envelopes, so only a very small amount of storage space is required, and many types of envelope control can be performed internally. requires only a small storage device. In addition, this speed parameter is suitable for time-division calculation means, and is suitable for calculation devices using floating point numbers, and can be used for multiplication with amplitude modulated waves, volume control by keyboard position, and envelope for sliding formant filters. Another advantage is that it is extremely easy to combine with various functions and effects such as amplitude control.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, and FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention. In the figure, 10 is a phase memory, 11 is a phase initial value generation circuit, and 12 is a phase decoder ADSR control. circuit, 1
3 is a phase adder, 14 is an exponent memory, 15 is a mantissa memory, 16 and 17 are adders, 18 is a comparator, 19 is a phase closing price prediction circuit, 20 is a binary shift circuit, 21 is an addition/subtraction control circuit, and 22 is a A phase initial amplitude value generation circuit, 23 a speed parameter decoder, 24 a data selection circuit, 25 a decoder, 26 a binary shift circuit, 27 a DA converter, and 28 an overflow detection circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] An envelope that should be generated in response to a key press in an envelope generator for an electronic musical instrument that divides the attack, decay, and release of an envelope into multiple phases and forms an envelope waveform through calculations at predetermined timings. speed parameter generating means for generating an envelope speed parameter made of digital binary numbers for speed control corresponding to attack, decay, and release speeds of the speed parameter generating means; decoding means for generating numeric data with a number of bits greater than the number of bits; when the envelope is in the attack phase, the numeric data from the decoding means is sequentially shifted according to the phase state, and the envelope is in the decay and release phases; A binary shift control means for fixing the shift of the data; and an arithmetic means for accumulating the data from the binary shift control means, and forming an envelope waveform whose speed is controlled by a speed parameter. Envelope generator for electronic musical instruments.