JPH01140722A - Formation of pattern - Google Patents

Formation of pattern

Info

Publication number
JPH01140722A
JPH01140722A JP62297570A JP29757087A JPH01140722A JP H01140722 A JPH01140722 A JP H01140722A JP 62297570 A JP62297570 A JP 62297570A JP 29757087 A JP29757087 A JP 29757087A JP H01140722 A JPH01140722 A JP H01140722A
Authority
JP
Japan
Prior art keywords
pattern
resist
photoresist layer
developing solution
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62297570A
Other languages
Japanese (ja)
Inventor
Akimasa Onozato
小野里 陽正
Takao Mori
孝夫 森
Kenichi Mizuishi
賢一 水石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62297570A priority Critical patent/JPH01140722A/en
Publication of JPH01140722A publication Critical patent/JPH01140722A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To form a high-accuracy pattern by a method wherein an exposure operation is executed in a developing solution by making use of a patterned light-shielding layer on a photoresist layer as a mask so that an amount of an undercut can be reduced even in a thick photoresist layer. CONSTITUTION:An LSI substrate 101 is immersed in a resist developing solution 106; a beam 107 is irradiated simultaneously. During this process, because a resist 102 to be used is of a positive type, only a part irradiated with the beam 107 is dissolved in the developing solution 106. While an exposure operation and a developing operation are repeated continuously, a pattern 108 for electrode formation use is formed with reference to the thick-film resist 102. That is to say, a light-shielding layer on a photoresist layer acts as a mask during the exposure operation, and only the part of the resist 102 irradiated with the beam 107 is dissolved by the developing solution. In addition, because the exposure operation is executed in the developing solution, the exposure operation and the developing operation are executed continuously. By this setup, even when the thick photoresist layer 102 is used, exposure to light is suppressed sharply in a transverse direction of a pattern edge part; accordingly, it is possible to form a high-accuracy pattern whose amount of an undercut is small.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は感光性レジストのパターン形成方法に係9%特
に10μmを越えるような厚いレジスト膜のパターン加
工を高精度で行うのに好適な露光及び現像方法を用いた
パターン形成方法に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for forming a pattern on a photosensitive resist. and a pattern forming method using a developing method.

〔従来の技術〕[Conventional technology]

従来は時開l1854−92061に記載のように、フ
ォトレジスト上に遮光層を設け、露光、現像を逐次行う
方法となっていた。これらは通常、レジスト膜厚が数ミ
クロンの範囲で行われている。10μm以上の厚膜パタ
ーン形成については電子材料。
Conventionally, as described in JPO 1854-92061, a light shielding layer is provided on a photoresist, and exposure and development are sequentially performed. These are usually performed with a resist film thickness in the range of several microns. Electronic materials for thick film pattern formation of 10 μm or more.

1985年10月号35頁から39頁に記載されている
ように、ドライフィルムレジストが多く便用されている
As described on pages 35 to 39 of the October 1985 issue, dry film resists are often used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術はフォトレジスト層の厚膜化に対する配慮
がなされておらず、10μmを越えるようなフォトレジ
スト層の高精度なバター二/グが困難であった。すなわ
ち、従来の露光、現像方式では厚膜レジスト全体を感光
させるために長時間の露光が必要となる。この時、パタ
ーンの横方向への光の拡がシによシマスフ端近傍も感光
するために、現像後はアンダーカット量の極めて大きな
パターンとなる。
The above-mentioned conventional technology does not take into consideration the thickening of the photoresist layer, and it is difficult to perform highly accurate butter ni/gu of a photoresist layer having a thickness exceeding 10 μm. That is, the conventional exposure and development method requires long exposure to expose the entire thick film resist to light. At this time, since the light spreads in the lateral direction of the pattern and the vicinity of the edge of the strip is also exposed to light, the pattern after development becomes a pattern with an extremely large amount of undercut.

本発明の目的は、厚いフォトレジスト層においてもアン
ダーカット量が小さく、高精度のパターン加工が可能な
パターン形成方法を提供することにある。
An object of the present invention is to provide a pattern forming method that has a small amount of undercut even in a thick photoresist layer and allows highly accurate pattern processing.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、フォトレジスト層上にパターン形成した遮
光層をマスクとして、現@液中で露光を行うことによシ
、達成される。
The above object is achieved by exposing the photoresist layer to light in a liquid using a patterned light shielding layer formed on the photoresist layer as a mask.

〔作用〕[Effect]

フォトレジスト層上の遮光層は露光時のマスクとして作
用し、光を照射したレジスト部のみが現像液で溶解する
。さらに、現像液中で露光を行うために露光と現像が連
続的に進行する。これにより厚いフォトレジスト層を用
いてもパターンエッヂ部横方向の感光が大幅に抑えられ
るため、アンダーカット量の小さな高精度のパターン加
工が可能となる。
The light-shielding layer on the photoresist layer acts as a mask during exposure, and only the resist portions irradiated with light are dissolved by the developer. Furthermore, since exposure is performed in a developer, exposure and development proceed continuously. As a result, even if a thick photoresist layer is used, exposure to light in the lateral direction of the pattern edge portion can be significantly suppressed, allowing highly accurate pattern processing with a small amount of undercut.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図(a)〜(f)により
説明する。
An embodiment of the present invention will be described below with reference to FIGS. 1(a) to 1(f).

第1図はCCB (Controlled Co11a
pseBond ing )実装用バンプ電極形成プロ
セスの工程図である。まず、第1図(a)に示すように
LSI基板101上にポジ型しジス)102 (例えば
、シブレイ社製、TF−20を塗布した。突起電極の高
さにより塗布膜厚を制御し、ここでは20〜150μm
の範囲に設定した。次いで、フォトレジスト膜102上
に光遮蔽膜103として厚3000人のAA蒸看膜を被
着した。さらに光遮蔽膜103をバターニングするため
に厚さ1μmのフォトレジスト膜104を形成した。こ
のフォトレジスト族104のパターン加工は第1図(b
)に示すように通常のホトリングラフィ加工に従って行
い、バンプ電極形成用パターン105t−形成し′fc
。この光遮蔽膜のパターン加工は化学エツチング(エツ
チング液ニリン酸、硝酸、酢酸、水 混a)によシ実施
した。次に、第1図(C)に示すように、LSI基板1
01をレジスト現像液106に浸漬し、同時に光107
を照射した。ここで使用したレジストはポジ型のため、
光が照射された部分のみが現像液106中に溶解する。
Figure 1 shows CCB (Controlled Co11a)
FIG. 3 is a process diagram of a mounting bump electrode formation process (pseBonding). First, as shown in FIG. 1(a), a positive type film 102 (for example, TF-20 manufactured by Sibley) was coated on an LSI substrate 101.The thickness of the coating film was controlled by the height of the protruding electrode. Here, 20-150μm
The range was set to . Next, a 3000 thick AA vapor film was deposited on the photoresist film 102 as a light shielding film 103. Further, in order to pattern the light shielding film 103, a 1 μm thick photoresist film 104 was formed. The pattern processing of this photoresist group 104 is shown in FIG.
) As shown in FIG.
. The patterning of this light shielding film was carried out by chemical etching (etching solution containing diphosphoric acid, nitric acid, acetic acid, and water). Next, as shown in FIG. 1(C), the LSI board 1
01 is immersed in a resist developer 106, and at the same time exposed to light 107.
was irradiated. The resist used here is positive, so
Only the portion irradiated with light is dissolved in the developer 106.

このような露光、現像を連続的に繰り返すことによシ第
1図(d)に示すような厚膜レジストに対し電極形成用
ノくターフ108の加工を行った。次にtN法(選択電
気めっき)により第1図(e)に示すようにバンプ電極
109を形成した。さらに不要部レジストを除去し、第
1図(f)に示すようなバンプ電極パターンを形成した
By continuously repeating such exposure and development, a turf 108 for forming electrodes was formed on the thick film resist as shown in FIG. 1(d). Next, bump electrodes 109 were formed by the tN method (selective electroplating) as shown in FIG. 1(e). Furthermore, unnecessary portions of the resist were removed to form a bump electrode pattern as shown in FIG. 1(f).

本工程ではバンプ電極を電着法で行ったが、蒸着リフト
オフ法を用いても同様の電極ノ(ターン形成が可能であ
る。
In this step, the bump electrodes were formed by electrodeposition, but similar electrode turns can also be formed by vapor deposition lift-off.

通常のフォトリング2フイ工程ではフォトレジスト層の
厚膜化に従ってパターン形成が困難になる。例えば、5
0μmの厚さのフォトレジスト膜のパターン加工を行っ
た場合、そのサイド現像量は15μm以上となる。lた
レジスト膜の厚さに比例してサイド現像量が増加するた
めパターンの高精度加工が不可能となる。
In the normal photoring 2-fi process, pattern formation becomes difficult as the photoresist layer becomes thicker. For example, 5
When patterning a photoresist film with a thickness of 0 μm, the amount of side development becomes 15 μm or more. Since the amount of side development increases in proportion to the thickness of the resist film, high-precision pattern processing becomes impossible.

本実施例によれば、レジスト膜厚が50μmの場合、そ
のサイド現像量は5μm以下であった。
According to this example, when the resist film thickness was 50 μm, the side development amount was 5 μm or less.

また、レジスト膜厚を更に増加(〜150μm)しても
、サイド現像量の増加は僅かであり、厚膜レジスト加工
の高精度化に2いて極めて大きな効果がある。さらに、
アスペクト比(膜厚/パターン加工寸法)の高いパター
ン加工が可能であり。
Moreover, even if the resist film thickness is further increased (up to 150 μm), the amount of side development increases only slightly, and this has an extremely large effect on increasing the precision of thick film resist processing. moreover,
It is possible to process patterns with high aspect ratios (film thickness/pattern processing dimensions).

バンプ電極の高信頼度化に効果がある。また、これらの
パターン加工は他の厚膜パターン加工(例えばメタルマ
スクを用いたCCBバンプ電極形成)に比べて、電極間
のピッチを大幅に短縮できるため、バンプ電極の高密度
化が図れる効果がある。
This is effective in increasing the reliability of bump electrodes. Additionally, compared to other thick film pattern processing (for example, forming CCB bump electrodes using a metal mask), these pattern processing can significantly shorten the pitch between electrodes, which has the effect of increasing the density of bump electrodes. be.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、10μm以上の厚膜レジストにおいて
アンダーカット量の小さな高精度のバターニングができ
るため、加エバターンの高アスペクト比の効果がある。
According to the present invention, high-precision patterning with a small amount of undercut can be performed in a thick film resist of 10 μm or more, resulting in the effect of a high aspect ratio of the patterned pattern.

さらに、ホトリソグラフイを用いた厚膜加工では加エバ
ターンの微細化が容易に行えるため、パターンの高密度
化に対して大きな効果がある。
Furthermore, thick film processing using photolithography can easily miniaturize the processed pattern, which has a great effect on increasing the density of the pattern.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すパターン形成方法の工
程図である。 101・・・LSI基板% 102・・・厚膜レジスト
。 103・・・光遮蔽膜、104・・・薄膜レジス)、1
05・・・開ロバターン、106・・・現像液、107
・・・光。 ゛   108・・・電極形成用パターン、109・・
・突起電極。。 (:甲 代理人 弁理士 小川勝男 ぐ、 第 I 凹 (C) (子)
FIG. 1 is a process diagram of a pattern forming method showing an embodiment of the present invention. 101...LSI substrate% 102...Thick film resist. 103... Light shielding film, 104... Thin film resist), 1
05... Open butter pattern, 106... Developer, 107
···light.゛ 108... Pattern for electrode formation, 109...
・Protruding electrode. . (: Agent A Patent attorney Katsuo Ogawa, Part I (C) (child)

Claims (1)

【特許請求の範囲】 1、感光性レジスト膜のパターン形成方法において、該
レジスト膜のパターン露光を現像液中で行うことを特徴
とする感光性レジスト膜のパターン形成方法。 2、特許請求の範囲第1項において、感光性レジスト膜
上に形成した光遮蔽膜パターンの加工を行い、該パター
ンを露光、現像時のマスクとすることを特徴とする感光
性レジスト膜のパターン形成方法。 3、特許請求の範囲第1項又は第2項に記載のパターン
形成方法において、露光中に現像液の供給及び排出が繰
り返されることを特徴とする感光性レジスト膜のパター
ン形成方法。 4、特許請求の範囲第2項記載のものにおいて、上記光
遮蔽膜はAl、Cr、Tiから選ばれる一種からなるこ
とを特徴とするレジスト膜のパターン形成方法。
[Scope of Claims] 1. A method for forming a pattern of a photosensitive resist film, characterized in that pattern exposure of the resist film is carried out in a developer. 2. A pattern of a photosensitive resist film according to claim 1, characterized in that a light shielding film pattern formed on the photosensitive resist film is processed and the pattern is used as a mask during exposure and development. Formation method. 3. A pattern forming method for a photosensitive resist film according to claim 1 or 2, characterized in that the supply and discharge of a developer is repeated during exposure. 4. A resist film pattern forming method according to claim 2, wherein the light shielding film is made of one selected from Al, Cr, and Ti.
JP62297570A 1987-11-27 1987-11-27 Formation of pattern Pending JPH01140722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62297570A JPH01140722A (en) 1987-11-27 1987-11-27 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62297570A JPH01140722A (en) 1987-11-27 1987-11-27 Formation of pattern

Publications (1)

Publication Number Publication Date
JPH01140722A true JPH01140722A (en) 1989-06-01

Family

ID=17848262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62297570A Pending JPH01140722A (en) 1987-11-27 1987-11-27 Formation of pattern

Country Status (1)

Country Link
JP (1) JPH01140722A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258267A (en) * 1989-12-22 1993-11-02 Fujitsu Limited Process for forming resist pattern
US6093520A (en) * 1994-09-09 2000-07-25 Board Of Supervisors Of Louisiana State University And Agricultural And Mechanical College High aspect ratio microstructures and methods for manufacturing microstructures
WO2005081063A1 (en) * 2004-02-20 2005-09-01 Daikin Industries, Ltd. Resist laminate used for immersion lithography
JP2011238589A (en) * 2010-04-14 2011-11-24 Tokyo Ohka Kogyo Co Ltd Method of producing comb-shaped electrode

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258267A (en) * 1989-12-22 1993-11-02 Fujitsu Limited Process for forming resist pattern
US6093520A (en) * 1994-09-09 2000-07-25 Board Of Supervisors Of Louisiana State University And Agricultural And Mechanical College High aspect ratio microstructures and methods for manufacturing microstructures
WO2005081063A1 (en) * 2004-02-20 2005-09-01 Daikin Industries, Ltd. Resist laminate used for immersion lithography
JP2011238589A (en) * 2010-04-14 2011-11-24 Tokyo Ohka Kogyo Co Ltd Method of producing comb-shaped electrode

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