JPH01135071A - Insulated-gate bipolar transistor - Google Patents
Insulated-gate bipolar transistorInfo
- Publication number
- JPH01135071A JPH01135071A JP29378387A JP29378387A JPH01135071A JP H01135071 A JPH01135071 A JP H01135071A JP 29378387 A JP29378387 A JP 29378387A JP 29378387 A JP29378387 A JP 29378387A JP H01135071 A JPH01135071 A JP H01135071A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- source
- gate
- resistance
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
゛産業上の利用分野〕
本発明は、電力用スイッチング素子として用いられる絶
縁ゲート型バイポーラトランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate bipolar transistor used as a power switching element.
近年、電力用スイッチング素子として導電変調を利用し
たＭＯ３電界効果トランジスタ、いわゆる絶縁ゲート型
バイポーラトランジスタが注目されている。この絶縁ゲ
ート型トランジスタはＭＯ８電界効果トランジスタと同
様に入力インピーダンスが高く、またバイポーラトラン
ジスタと同様にオン抵抗が低くできる。第２図はその基
本的な構造を示し、Ｐ゛基板ｌの上に低不純物濃度のｎ
−層２が形成され、このｎ−層２の表面にｐベース層３
と、さらにその中にソース層４とが形成されている。ｐ
ベース層３のｎ−層２とソース層４ではさまれた表面部
分はチャネル領域５となる部分で、その上にゲート絶縁
膜６を介してゲート電極７が形成される。そして、ソー
ス層４上にはベース層３と同時に接触するソース電極８
が、またＰ゛基板１の裏面にはドレイン電極９が設けら
れている。In recent years, MO3 field effect transistors that utilize conduction modulation, so-called insulated gate bipolar transistors, have attracted attention as power switching elements. This insulated gate transistor has a high input impedance like an MO8 field effect transistor, and can have a low on-resistance like a bipolar transistor. Figure 2 shows its basic structure.
- layer 2 is formed, and a p base layer 3 is formed on the surface of this n-layer 2.
Further, a source layer 4 is formed therein. p
A surface portion of the base layer 3 sandwiched between the n- layer 2 and the source layer 4 becomes a channel region 5, and a gate electrode 7 is formed thereon with a gate insulating film 6 interposed therebetween. A source electrode 8 is disposed on the source layer 4 and is in contact with the base layer 3 at the same time.
However, a drain electrode 9 is provided on the back surface of the P substrate 1.
このような絶縁ゲート型パイポーラトランジス夕では、
ゲート、ソース間の電圧印加によりソース層４からチャ
ネル領域５を通ってｎ−層２に注入される電子電流に対
して、Ｐ゛基板１からｎ−層２への正孔の注入がおこり
、この結果ｎ−層２において導電変調がおこる。ｎ″層
２注入された正孔電流はｐベース層３のソース層４直下
を通り、ソース電極８へ抜ける。ソース電極８はｐベー
ス層３とｎ０ソ一ス層４を短絡しているので、Ｐ゛層１
＋ｎ−層２．９層３．ｎ°層４からなる４層のサイリス
ク動作を阻止し、ゲート・ソース間電圧をゼロにするこ
とで素子をターン・オフできる。In such an insulated gate type bipolar transistor,
In response to an electron current injected from the source layer 4 through the channel region 5 into the n-layer 2 by applying a voltage between the gate and the source, holes are injected from the P'substrate 1 to the n-layer 2, As a result, conductivity modulation occurs in the n-layer 2. The hole current injected into the n'' layer 2 passes directly under the source layer 4 of the p base layer 3 and exits to the source electrode 8. Since the source electrode 8 short-circuits the p base layer 3 and the n0 source layer 4, , P layer 1
+n- layer 2.9 layer 3. The device can be turned off by blocking the silica operation of the four layers consisting of the n° layer 4 and reducing the gate-source voltage to zero.
この絶縁ゲート型バイポーラトランジスタは、従来のパ
ワーＭＯ３ＦＥＴのドレイン領域に逆の導電型層のＰ゛
層１設けて導電変調をおこしている点が異なる。This insulated gate bipolar transistor differs from the conventional power MO3FET in that a P' layer 1 of the opposite conductivity type is provided in the drain region to cause conductivity modulation.
この絶縁ゲート型バイポーラトランジスタは、素子を流
れる電流密度が大きくなると、ソース層４の下の横方向
抵抗による電圧降下が大きくなる。In this insulated gate bipolar transistor, as the current density flowing through the device increases, the voltage drop due to the lateral resistance under the source layer 4 increases.
そしてｐベース層３とｎ９ソ一ス層４の間の接合が順バ
イアスされるとサイリスタ動作を起こし、ゲート・ソー
ス間電圧をゼロにしても素子がターン・オフしないラッ
チング状態になる。この問題を解決するために、大電流
を外部回路で検出してゲート・ソース間電圧をゼロにす
る保護法が一般に用いられるが、雑音による誤動作をふ
せぐため、大電流を検出してから保護動作を行なうまで
に１０μ３程度の時間が必要である。しかし、素子自身
には電流を制限することができないために、保護機能が
動作する前に素子がラッチングしてしまう危険性があっ
た。Then, when the junction between the p base layer 3 and the n9 source layer 4 is forward biased, a thyristor operation occurs, resulting in a latching state in which the device does not turn off even when the gate-source voltage is reduced to zero. To solve this problem, a protection method is generally used in which large currents are detected by an external circuit and the voltage between the gate and source is reduced to zero.However, in order to prevent malfunctions due to noise, protection is activated after detecting large currents. It takes about 10μ3 time to complete the process. However, since the element itself cannot limit the current, there is a risk that the element may latch before the protection function operates.
本発明の目的は、上記の欠点を除去し、素子に大電流が
流れたときに直ちにゲート・ソース間電圧を制限するこ
とで、素子自身でラッチング状態になることを阻止でき
る絶縁ゲート型バイポーラトランジスタを提供すること
にある。The purpose of the present invention is to eliminate the above drawbacks and to provide an insulated gate bipolar transistor that can prevent the device from becoming latched by immediately limiting the gate-source voltage when a large current flows through the device. Our goal is to provide the following.
ｃ問題点を解決するための手段〕
上記の目的を達成するために、本発明は、第一導電型の
半導体基板と、この基板上に形成された低不純物濃度の
第二導電型の半導体層と、この半導体層の表面に形成さ
れた第一導電型のベース層と、このベース層表面にその
端部にチャネル領域が残るように形成された第二導電型
のソース層と、前記チャネル領域上にゲート絶縁膜を介
して形成されたゲート電極と、チャネル領域外の前記ベ
ース層領域および前記ソース層に接触するソース電極と
、前記基板下面に接触するドレイン電極を有する絶縁ゲ
ート型バイポーラトランジスタにおいて、ソース電極の
反接触面側に抵抗層が積層されたものとする。Means for Solving Problems] In order to achieve the above object, the present invention provides a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type with a low impurity concentration formed on the substrate. a base layer of a first conductivity type formed on the surface of this semiconductor layer; a source layer of a second conductivity type formed on the surface of this base layer so that a channel region remains at its end; and the channel region. In an insulated gate bipolar transistor having a gate electrode formed thereon via a gate insulating film, a source electrode in contact with the base layer region outside the channel region and the source layer, and a drain electrode in contact with the lower surface of the substrate. , a resistance layer is laminated on the side opposite to the contact surface of the source electrode.
本発明による絶縁ゲート型バイポーラトランジスタのソ
ース、ドレイン電極下に大電流が流れたときにゲート・
ソース間電圧は抵抗体における電圧降下分だけ差し引か
れた値になるため、ゲート・チャネル領域間の電圧が低
く抑えられ、素子を流れる電流密度が小さくなってラッ
チング状態がおこりにく（なる。When a large current flows under the source and drain electrodes of the insulated gate bipolar transistor according to the present invention, the gate
Since the voltage between the sources is a value subtracted by the voltage drop across the resistor, the voltage between the gate and channel regions is kept low, and the current density flowing through the device is reduced, making it difficult for a latching state to occur.
第１図は本発明の一実施例を示し、第２図と共通の部分
には同一の符号が付されている。第２図と異なる点は、
ベース層３およびソース層４に接触するソース電極８を
形成したのちに、その上に抵抗層ｌＯを形成したことで
ある。この抵抗層は、例えば１〜２＃１ｍの厚さの多結
晶シリコンからなり、不純物濃度を調整して５〜５０ｍ
Ω程度の抵抗値となるようにする。あるいは非晶質シリ
コンによって形成してもよい、さらにソース端子Ｓとの
接続のために金属電８ｉ１１を抵抗層１０の上に積層す
る。FIG. 1 shows an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. The difference from Figure 2 is that
After forming the source electrode 8 in contact with the base layer 3 and the source layer 4, the resistance layer 10 is formed thereon. This resistance layer is made of polycrystalline silicon with a thickness of, for example, 1 to 2 #1 m, and is made of polycrystalline silicon with a thickness of 5 to 50 m by adjusting the impurity concentration.
The resistance value should be approximately Ω. Alternatively, it may be formed of amorphous silicon. Furthermore, a metal electrode 8i11 is laminated on the resistance layer 10 for connection to the source terminal S.
今、この絶縁ゲート型バイポーラトランジスタに、例え
ば１００ Ａの電流が流れたとすると抵抗層１０の両面
間における電圧降下は０．５〜５ｖになる。Now, if a current of, for example, 100 A flows through this insulated gate bipolar transistor, the voltage drop between both surfaces of the resistance layer 10 will be 0.5 to 5 V.
抵抗層１０はゲート回路にも含まれるため、ゲート・ソ
ース間電圧は０．５〜５ｖ低くなり、通常１５Ｖ程度の
ゲート電圧が効果的に抑えられて電流が制限され、ソー
ス層４の下の横方向抵抗による電圧降下が小さくなる。Since the resistance layer 10 is also included in the gate circuit, the gate-source voltage is lowered by 0.5 to 5V, which effectively suppresses the gate voltage, which is usually about 15V, and limits the current. Voltage drop due to lateral resistance is reduced.
その結果ラッチングの危険性が少なくなる。抵抗層１０
は、接続されるソース端子Ｓからドレイン端子りに流れ
る電流を制限してうソチング現象を防止するためのもの
で、マルチエミッタパワトランジスタの各エミッタ電極
上の抵抗層のようにエミッタ電流のバランスをとる目的
ではないので、一つの半導体チップに一つのソース電極
より有しない絶縁ゲート型バイポーラトランジスタ素子
に対しても有効である。そしてその抵抗値は多結晶Ｓｔ
あるいは非晶質シリコンの不純物濃度あるいは厚さを変
えることにより任意の値に設定することができる。As a result, the risk of latching is reduced. resistance layer 10
This is to limit the current flowing from the connected source terminal S to the drain terminal to prevent the floating phenomenon, and it is used to balance the emitter current like a resistive layer on each emitter electrode of a multi-emitter power transistor. It is also effective for insulated gate bipolar transistor elements in which one semiconductor chip does not have more than one source electrode. And its resistance value is polycrystalline St
Alternatively, it can be set to an arbitrary value by changing the impurity concentration or thickness of amorphous silicon.
本発明によれば、ソース電極上に抵抗層を形成しソース
電極から半導体素体内に流れこむ電流が大きくなったと
きの抵抗層内の電圧降下により、ゲート電圧を小さくし
て電流を制限し、ラッチングのおこりにくい絶縁ゲート
型バイポーラトランジスタが得られる。According to the present invention, a resistance layer is formed on the source electrode, and when the current flowing from the source electrode into the semiconductor body becomes large, the voltage drop in the resistance layer is used to reduce the gate voltage to limit the current. An insulated gate bipolar transistor that is less susceptible to latching can be obtained.
第１図は本発明の一実施例の絶縁ゲート型バイポーラト
ランジスタの要部断面図、第２図は従来の絶縁ゲート型
バイポーラトランジスタの要部断面図である。
ｔ：ｐ”ｓｔ基板、２：ｎ−層、３：ｐベース層、４：
ｎ“ソース層、５：チャネル領域、６：ゲート絶縁膜、
７：ゲート１ｉ極、８：ソース電極、９ニドレイン電極
、ｌＯ：抵抗層、１１：電極。FIG. 1 is a sectional view of a main part of an insulated gate bipolar transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view of a main part of a conventional insulated gate bipolar transistor. t: p''st substrate, 2: n-layer, 3: p base layer, 4:
n" source layer, 5: channel region, 6: gate insulating film,
7: Gate 1i electrode, 8: Source electrode, 9 Nidrain electrode, IO: Resistance layer, 11: Electrode.
Claims (1)
れた低不純物濃度の第二導電型の半導体層と、該半導体
層の表面に形成された第一導電型のベース層と、該ベー
ス層表面にその端部にチャネル領域が残るように形成さ
れた第二導電型のソース層と、前記チャネル領域上にゲ
ート絶縁膜を介して形成されたゲート電極と、チャネル
領域外の前記ベース領域および前記ソース層に接触する
ソース電極と、前記基板下面に接触するドレイン電極を
有するものにおいて、ソース電極の反接触面側に抵抗層
が積層されたことを特徴とする絶縁ゲート型バイポーラ
トランジスタ。(1) a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer with a low impurity concentration formed on the substrate, and a first conductivity type base layer formed on the surface of the semiconductor layer; a second conductivity type source layer formed on the surface of the base layer so that a channel region remains at its end; a gate electrode formed on the channel region via a gate insulating film; An insulated gate bipolar transistor having a base region and a source electrode in contact with the source layer, and a drain electrode in contact with the lower surface of the substrate, characterized in that a resistance layer is laminated on the side opposite to the contact surface of the source electrode. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29378387A JPH01135071A (en) | 1987-11-20 | 1987-11-20 | Insulated-gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29378387A JPH01135071A (en) | 1987-11-20 | 1987-11-20 | Insulated-gate bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01135071A true JPH01135071A (en) | 1989-05-26 |
Family
ID=17799118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29378387A Pending JPH01135071A (en) | 1987-11-20 | 1987-11-20 | Insulated-gate bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01135071A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5032880A (en) * | 1989-05-23 | 1991-07-16 | Kabushiki Kaisha Toshiba | Semiconductor device having an interposing layer between an electrode and a connection electrode |
-
1987
- 1987-11-20 JP JP29378387A patent/JPH01135071A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5032880A (en) * | 1989-05-23 | 1991-07-16 | Kabushiki Kaisha Toshiba | Semiconductor device having an interposing layer between an electrode and a connection electrode |
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