JPH01134548A - Memory device - Google Patents

Abstract

PURPOSE:To simplify the constitution of a memory device by inhibiting a multi- step shift register holding various data on partial writing jobs from holding the partial write data. CONSTITUTION:For the partial write data DP, a check bit is first produced to a part related to the corresponding write data DP via a partial check bit production part 3. The data DP is set at a write data register 7 and only the partial write position information BM and a partial check bit CHP are shifted by shift registers 4 and 5 respectively. With output of the read data, a check bit is produced by the data which is not to be rewritten out of those read data. This check bit is combined with said partial check bit for production of a check bit for the new write data. This produced check bit is set at the register 7 together with the data not to be rewritten.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a storage device having a configuration for partial write access of data in a storage device having a large number of memory banks and accessed at high speed by pipeline control. The purpose is to provide a storage device that simplifies the circuit configuration by preventing partially written data from being held in a multi-stage shift register. Partial write data and partial write position information given by a partial rewrite command of stored data in a storage device that is accessed multiple times through individual pipeline control and stores data with check bits added for error detection and correction. a register that receives
a partial check bit creation unit that creates partial check bits based on partial write data and partial write position information; a shift register that holds the partial check pits and partial write position information until the original data is read;
The present invention includes a check bit synthesis unit that synthesizes a check bit of data after rewriting using a check bit generated for data at a position that cannot be rewritten according to partial write position information among the original data read from a storage device and the partial check pit. Configure.

[Industrial Field of Application] The present invention relates to a storage device that includes a large number of memory banks and is accessed at high speed through pipeline control, and has a configuration for partial data write access.

In recent years, storage devices have made remarkable progress, and efforts are being made to increase the capacity and speed of semiconductor memories.

However, since the speed of a memory storage element is slower than the speed of a processor (central processing unit), techniques have been adopted to effectively speed up memory access time. Among these techniques, there is a method in which a plurality of memory banks are provided and memory access is performed using an interleave method (a method in which memory addresses are sequentially assigned to different memory banks) using a pipeline control method.

When performing an operation to rewrite part of the stored data on such a storage device, first read the corresponding data from the storage device (READ).
Part of the read data is replaced with partial write data given by the command, check bits for error correction and detection are created from the replaced data, and are written to the storage device along with the write data (write data). :WRITE) operation is being performed, and it has been desired to improve the configuration for generating a check bit when performing an operation of rewriting a portion of the data.

[Conventional technology] FIG. 3 shows a block configuration of a conventional example.

In FIG. 3, reference numeral 30 denotes a write data register in which partial write instruction data consisting of a large number of data is set;
1-1 to 31-m each have the same storage capacity as the register 30, and together constitute a shift register.
32 is a partial write data combination circuit, 33-1.33-
2 is a check bit creation circuit, 34-1 to 34-n are write data selection circuits, 35-1 to 35nh are memory write data registers, and 36-1 to 36n are memory banks 1 to 34-n.
n, 37-1 to 37-n are memory read registers, 38
3 represents a read data selection circuit, and 39 represents an error detection and correction circuit.

A partial write operation using the configuration shown in FIG. 3 will be explained below.

First, when a partial write access occurs from the central processing unit via the memory control device (not shown), the write data register 30 stores partial write data Dp (including parity bit) and write position information BM (n in one access). When reading and writing byte data, an n-bit byte mark (information called an n-bit byte mark that indicates the effectiveness of some byte positions that are subject to rewriting and an invalid indication of other byte locations), and an n-bit parity bit P is set.

At this time, the address system [1 (not shown) and the read control line of the storage device are driven, and the read operation of the original data (data to be rewritten) is started for the memory bank at the corresponding address.

On the other hand, since the memory cycle of the storage device is slower than the cycle time of the central processing unit, the central processing unit must access the memory one after another until the read access to the storage device is started and the read data is output. It will be done. For this purpose, the storage device includes n(l!) memory banks, and an interleaving method is adopted, so that access operations are performed simultaneously and in parallel between different memory banks.

Each data set in the register 30 by partial rewriting access is stored in shift registers 31-1 to 31-m in parallel (by inputting multiple bits sequentially) in the central processing unit cycle, since the original data is not read out immediately from the memory bank. One of the memory banks 36, for example memory bank 1 (36-1), functions as a shift and delay circuit.
When read data is output and set from memory read register l (37-1>), partial rewrite data is set to shift register 31-m at that timing.

The contents of the memory read register 1 (37-1) are passed through the read data selection circuit 38 to the error detection and correction circuit 39.
, performs error detection and correction operations using check bits, supplies correct data Da to the partial write data coupling circuit 32, and reads out the read data D based on the partial write position information BM from the shift register 31-m.
a and partial write data Dp are combined.

In this case, the byte of the data Da at the byte position indicated as invalid by the partial write position information BM is used as new data as is, and the partial write data Dp is incorporated into the new data at the byte position indicated as valid.

This combined rewritten data is supplied to the check bit creation circuit 33-1 to create a check bit,
The data is passed through the write data selection circuit 34-1 (for memory bank l) to the memory write data register 3.
5 cents and a write operation is performed. Note that the check bit creation circuit 33-2 is used when rewriting the entire data to be accessed (when there is no need to read it).

[Problems to be Solved by the Invention] According to the configuration of the conventional example, partial write access processing requires holding partial write data until the memory read access and correction of the read data are completed.

However, as mentioned above, various types of partially written data (
Partial write data Dp, partial write position information BM,
For example, in the case of an 8-byte storage device, the partial write data Dp is 8 bytes maximum, the partial write position information BM is 8 bits, and the parity bit is 8 bits, for a total of 10 bytes (80 bits). ,
The amount of circuitry in the register that shifts it is true.

In addition, as machine clock speeds have increased due to improvements in semiconductor technology and system performance in recent years, there has been a tendency for the need to further increase the number of shift register stages, resulting in the problem of larger and more complex circuit configurations.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device that simplifies the circuit configuration by preventing a multi-stage shift register that holds various types of partial write data from holding partial write data.

[Means for solving problems] The basic configuration of the present invention is shown in FIG.

In FIG. 1, l is a register where partial write position information is set, 2 is a register where partial write data is set, 3 is a partial check bit creation unit, and 4-1 to 4
-6 is a multistage (6 stages in the figure) shift register that shifts and holds the contents of register l, 5-1 to 5-6 are multistage shift registers that shift and hold the partial check bit (CHp), and 6 is write data. A selection circuit, 7 a write data register, 8 a memory bank, 9 a read data register, 10 a read data selection circuit, 11 an error detection and correction circuit, and 12 a check bit synthesis section.

Although not shown in FIG. 1, there are many other structures related to memory banks.

Regarding partial write data, the present invention first creates a check bit for the part related to the write data by the partial check bit creation section 3, sets the partial write data Dp in the write data register, and then Only the write position information BM and the partial check bit CHp are shifted by each shift register 4.5, and when the read data is output, a check bit is created from the data that is not subject to rewriting and the check pit is A check bit of new write data is synthesized by combining the check bit and the partial check bit, and is set in the write data register together with the data not to be rewritten.

[Operation] Partial write position information is input to terminal X and set in register 1, and partial write data is input to terminal y and set in register 2. In this case, the human input data is sent in parallel from the bus.

Further, read access to the data to be rewritten (original data) is performed in a circuit (not shown) (which drives the read control line of the corresponding address as in the conventional case).

Partial check bit creation unit 3 creates check bits for partial write data immediately after data is sent to register 1.2 (combines information at each bit position of multiple bytes according to a specific pattern to create multiple check pits). create.

However, at this time, only the partial write data designated by the partial write position information BM is treated as valid data, and the data at other byte positions are treated as invalid data (all "0's").

The created partial check bit CHp is set in parallel in the shift register 5-1, and at the same time, the partial check bit CHp is set in the shift register 5-1.
Together with the partial write position information BM set to 1, it is sequentially shifted by the machine cycle of the processing device.

In parallel with the partial check bit creation operation, the partial write data Dp is selected by the write data selection circuit 6 according to the instruction of the partial write position information BM, and is set in a part of the write data register.

The continuous output of the original data is sent to the read data register 9 and input to the error detection and correction circuit 11 via the read data selection circuit 10, where error detection and correction operations are performed using check pits in the read data to detect errors. Data (referred to as Da) without a check bit is supplied to the check bit synthesis unit 12 and also to the write data selection circuit 6.

Partial write position information BM and partial check pit t-CHp are shifted to the final stage 4-6.5-6 of shift register 4.5 at the timing when the original data is read from the memory bank, and partial write position information BM is subjected to check bit synthesis. It is input as a control signal to the valid data selection circuit 121 of the section 12, and selects the data in the position that cannot be rewritten in the original data Da (the byte position indicated as invalid by the position information BM is the position where the original data remains as is) and checks the data as a check bit. It is output to the creation circuit 122.

The check bit creation circuit 122 creates check bits only from the portion of the original data that cannot be rewritten, and supplies the result to the check bit synthesis circuit 123. At this time,
The check bit synthesis circuit 123 receives partial check bits CHp from the final stage register 5-6 of the shift register 5.
is input, the two check pits are exclusive-ORed to synthesize and output the check pits (referred to as CH) of the entire data after rewriting.

This check bit CH is stored in a predetermined check bit position of the write data register 7 via the write data selection circuit 6. Further, the original data Da supplied to the write data selection circuit 6 is transferred to the shift register 4-6.
The partial write position information BM outputted from the partial write position information BM is selected based on the inverted information, and data at positions other than the part to be rewritten is set as valid in the write data register.

As a result, new data that has partially rewritten the original data is added to the write data register 7 along with the check bit.
and its contents are written to the original address.

In this configuration, each stage of the shift register 4.5 has the number of bits to hold partial write position information (when reading or writing 8 bytes, the position can be specified with 8 bits).
The capacity of the partial check bits (for example, 8 check bits for 8 bytes of data) is sufficient, and the conventional shift register for shifting multi-byte (for example, 8 bytes) data is no longer necessary. Ta.

[Embodiment] The configuration of an embodiment of the present invention is shown in FIG. 2 (al), the configuration of a partial check bit synthesis section thereof is shown in FIG. 2 (bl), and the configuration of the error check and check bit synthesis section is shown in FIG. Figure 2 (shown in C1).

In Figure 2 (al), 21 to 29 correspond to the numbers 1 to 9 in Figure 1 above, 21 is a register in which partial write position information is set, and 22 is a register in which write data including partial write data is set. 23 is a partial check bit creation unit, 24-1 to 24-m are multistage (6 stages in the figure) shift registers that shift and hold the contents of register 1, and 25-1 to 25-m are partial check registers. A multi-stage shift register for shifting and holding bits (CHp), 26-1 to 26-n are write data selectors, 27-
1 to 27-n are write data registers, 281 to 28-
n represents a memory bank, 29-1 to 29-n read data registers, 40 a read data selector, and 41 an error check/check bit generator.

The basic operation of FIG. 2+8) is the same as the explanation of the operation of the basic configuration shown in FIG.

To explain the outline of the operation, when a partial write is instructed, read access to the original data is performed, and partial write position information (8 bits) BM and partial write data (including parity bit) are respectively stored in the register 21. Enter .22.

Then, in the partial check bit creation section 23, a partial check bit (CHp) is created, and a partial check bit (CHp) is created.
Hp is sent to the first stage of the shift register 25, and partial write position information is sent to the first stage of the shift register 24.

Also, the partial write data is stored in the check bit creation unit 23.
The partial write position information BM is specified by the write data selector 26 and set at the position of the write data register 27.

The configuration of the partial check bit creation unit 23 is shown in FIG. The data for each byte of write data and the valid position indication bit are input to data fixing circuits 61-1 to 61-n provided corresponding to the same byte. The data fixing circuits 6i-t to 61-n all generate a byte output of all "0" when the valid position instruction bit is "01" (in the case of a byte position where partial write data is not given). , when the valid position indication bit is "1", the input write data byte is output as is.

The check bit generation circuit 62 in FIG. 2 (bl) generates a predetermined combination of bit patterns (
A check bit is generated using an error detection/correction code algorithm).

However, in this case, a check bit is generated for specific partial write data.

Next, returning to the explanation of the operation shown in FIG. The data register 29 is selected (by another bank selection signal not shown) and the read data is checked for error.
It is supplied to the check bit creation section 41.

The configuration of the error check/check bit creation section 41 is shown in FIG. 2(C).

In this configuration, 50 is a check bit synthesis unit;
1 represents a syndrome generation circuit, 52 an error detection/correction circuit, 53 a data fixing circuit, 54 a partial check bit generation circuit, and 55 a total check bit generation circuit.

To explain the operation of FIG. 2(C), the check bit creation circuit 50 receives the output data from the read data selector 40 of FIG. The generated check bits are supplied to the syndrome generation circuit 51. In the syndrome generation circuit 51, the check bits in the read data (the check bits stored together with the data in the memory) are inputted from the line 410, and based on both check bits, Create a syndrome (a bit pattern used to correct known error bits) and use the output for error detection and
By supplying the read data to a correction circuit 52, errors in read data are corrected in this circuit 52.

On the other hand, each byte of read data passing through the check bit creation circuit 50 from the line 400 is supplied to the corresponding input of the data fixing circuits 53-1 to 53-8. This data fixing circuit 53 has the same function as the data fixing circuit shown in FIG.

The other inputs of each circuit of the data fixing circuit 53 are fat as shown in FIG.
These are valid position indication bits O to 7 which are the output of the partial write position information BM output from the final stage 24-m of the shift register 24. Therefore, this data fixing circuit 53-1
From 53-8, data at byte positions that are not subject to partial writing in the read data (original data) is output, and then supplied to the partial check bit generation circuit 54.

The partial check bit creation circuit 54 creates check bits for input partial data (data not affected by partial writing) (actually all byte data is input, but some of the byte data are all "O"). .

Note that the output from the syndrome generation circuit 51 is supplied to a partial check bit creation circuit 54, which is used to correct data at byte positions that are input from the fixed data circuit 53 and are not subject to partial writing. .

The output of the partial check bit creation circuit 54 is shown in FIG.
It is input to the full check bit generation circuit 55 together with the partial check bit of the write data which is the output of the final stage 25-m of the shift register 25, and an exclusive OR (EXOR) operation of both is performed by a logic circuit. A check bit for the data after partial writing (write data) is created, and the write data selector 26 in FIG.
The data is stored in the write data register 27 via the write data register 27. At this time, the corrected read data (all bytes) which is the output of the error detection/correction circuit 52 is also input to the write data selector 26 in FIG. Only data at byte positions other than those to be written is stored in the write data register 27.

When the rewritten data and its check bit are stored in the write data register, all the data is written to the original address of the memory bank.

[Effects of the Invention] According to the present invention, a large number of shift registers for delaying partial write data during partial write access can be omitted, and the number of circuits in the configuration of a storage device can be significantly reduced. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 (al is a diagram showing the configuration of an embodiment of the present invention, FIG. Figure 2 (C1 is a diagram showing the configuration of the error check/check bit creation section,
FIG. 3 is a diagram showing the configuration of a conventional example. In Figure 1, 1: Register (for partial write position information) 2: Register (for partial write data) 3: Partial check bit creation section 4-1 to 4-68 Shift register 5-1 to 5-6: Shift register 6: Write data selection circuit 7: Write data register 8: Memory bank 9: Read data register 10: Read data selection circuit 11: Error detection and correction circuit 12: Check pit synthesis section

Claims (1)

[Claims] A plurality of memory banks are provided for reading and writing n-byte data as a unit of access, and multiple accesses are performed by pipeline control, and check bits for detecting and correcting errors are added and stored. In a storage device, a register (2, 1) receives partial write data and partial write position information given by a partial rewrite command of stored data, and a part creates a partial check bit from the partial write data and partial write position information. A check bit creation unit (3), and a shift register (4, 5) that holds the partial check bit and partial write position information until the original data is read.
), and a check bit synthesis unit ( 12) A storage device comprising: