JP3117096B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to, for example, loading data into a microprocessor or data from the microprocessor, which is suitable for use in the field of data input / output processing of a microprocessor. The present invention relates to a microprocessor that processes data when storing data.

In recent years, the amount of data that can be processed by a microprocessor has been dramatically increased, and the capacity and speed of an external storage device have been increased. For example, DSP
LSI (Large) such as (Digital Signal Proceser)
When data is loaded or stored in a Scale Integrated circuit, only a plurality of latches for adjusting to an address from another LSI are prepared and timing adjustment is performed, and the same applies to a microprocessor.

[0003] That is, in the case of a microprocessor that performs vector processing, the processing performance is improved if the data is arranged so as to be easily processed. However, if the data is input as it is, the processing speed may be reduced depending on the instruction. May be invited. Therefore, when a microprocessor is a type of processor in which a data register is built in an LSI and performs processing using the data, a large amount of data is loaded into the data register from an external storage device at a high speed, and the data is transferred at a high speed. It is necessary to process a large amount of data in an external storage device at high speed.
Today, with the speeding up of external storage devices and the ease of accessing one clock even at high frequencies, it is required to improve the processing speed inside the processor.

Further, in this case, it is necessary to immediately detect a failure of a circuit composed of a plurality of stages of latches.

[0005]

2. Description of the Related Art As a conventional microprocessor of this kind, for example, there is a microprocessor having an input / output device as shown in FIG. I / O device 3 of this microprocessor
Are a load pipeline LP provided between the external storage device 1 and the data register 2, and a store pipeline S
P, and each of the pipelines LP and SP is composed of a plurality of latches L.

In the above configuration, when loading,
For example, in order to synchronize with an address, data output from the external storage device 1 is delayed by a plurality of stages of latches L in the load pipeline LP so that appropriate load timing is obtained.
, Data loading is performed. Similarly, in the case of store, the data output timing is adjusted by a plurality of stages of latches L in the store pipeline SP, and data storage is performed.

Hereinafter, the operation example will be described in detail. FIG.
FIG. 6 is a diagram for explaining an operation example of the input / output device of the conventional microprocessor. As shown in FIG. 17, four pipelines (MLT, ADD, DIV, L / S pipeline) are operated in parallel. Data register 2 to 4
This is a bank configuration. In addition, in FIG.
It is assumed that 64-bit data is used as V7 data.

In this case, the data register 2 has four bank slot signals a,
The read / write slot of each pipeline is fixed for b, c, and d, that is, the bank slot coincides with the timing at which each pipeline accesses the first element of the vector operand. FIG. 17 shows the operation of the bank slot and the data register on the bank and the relationship between the banks accessed by each pipeline,
Table 1 and FIG. 18 show the relationship between each pipeline and available bank slots.

[0009]

[Table 1]

That is, for example, as a read port of the MLT pipeline, a slot is used,
The operation starts when the slot a is in the bank 0 of the data register, and the bank access of the data register is performed in the order of 0 → 1 → 2 → 3. As described above, when the starting point of the bank access is fixed (in this case, bank 0), as shown in FIG. 16, since there are four banks, four banks are continuously accessed from the start of the access.

As described above, at the timing when a predetermined bank slot signal is in bank 0, the address generation unit controls so that the address is output from latch 0, and latch 1 is supplied to latch 1, latch 2 and latch 3 every cycle. Latched, and the data of 4 banks are stored in V0, V1, V
2 and V3 are output. If the data length to be read is greater than 4, the address is incremented and V4, V
5, V6, and V7 are sequentially output, and the same operation as that described above is performed.

As described above, when accessing a data register divided into banks by giving an address, data corresponding to the number of banks is output from the fixed bank access start point. One or two
For example, if access is performed from bank 0, access to bank 1 is attempted, and access is to be started from bank 2 in the next access, other pipelines operating in parallel Since it is necessary to output data of bank 2 while checking whether or not bank 2 is using bank 2, data conflict occurs. Therefore, it always monitors which pipeline is using which bank. This is because the necessity complicates the circuit and makes the control difficult.

Here, as a data conversion instruction to the microprocessor, for example, 32-bit floating-point data
It is assumed that there is an instruction for converting to 4-bit floating point data. Then, when data is stored in the data register 2 from the external storage device 1, for example, as shown in FIG.
Data stored as a pair of D0 and D1 is D0, D4
The data stored in the pair of D2 and D3 is D1,
Loading is performed by rearranging the data into D5 and so on.

Next, the reason why the 32-bit floating point data is rearranged will be described with reference to FIG. Incidentally, in the configuration of the data register 2 in FIG.
Is assumed to be 64 bits. However, in the input / output device of FIG.
32 in data register 2 having a register length of 4 bits
It is assumed that a total of eight pieces of bit floating point data are stored, two each.

FIG. 20 is a diagram equivalent to storing the 32-bit continuous data stored in the external storage device 1 shown in FIG. 19 in the data register 2 as it is, that is, the stored data is loaded as it is. It is an example. First, when a data conversion instruction for converting 32-bit floating point data to 64-bit floating point data is executed using the stored data shown in FIG.
Is executed by the ADD pipeline shown in FIG.

In the ADD pipeline, Table 1 and FIG.
As shown in FIG. 8, data is sequentially read from the bank 0 at the timing of the slot b. At the timing shown in FIG. 21, the data of S0 is first, then S2, S4, and S6. The minute data is read, the data is input to the ADD pipeline, and the 64-bit converted data is output from the ADD pipeline.

Since only one conversion is performed in one cycle in the ADD pipeline, only half of the 64-bit width data, that is, 32 bits are processed at a time. That is, the reason why two 32-bit data are stored in the 64-bit width is to effectively use the data register.

For the data processed by the conversion instruction as described above, the starting point of the bank access is fixed also in the writing for the same reason as in the reading of the bank, and the data for four banks are written continuously every cycle. Then, as shown in FIG. 22, since the data is stored in the data register 2, the converted data is written to the data register 2 in the order of S0, S2, S4, and S6.

FIG. 23 is a block diagram showing a test configuration in an input / output device of a conventional microprocessor.
Conventionally, when testing a plurality of registers in a microprocessor, a latch L in each pipeline LP, SP is usually used.
Are connected to each other by a scan path to read the data, thereby checking the contents of the register.

[0020]

However, in such a conventional microprocessor, when data is stored in the data register 2 from the external storage device 1,
Since the processing result after the data conversion processing is written in the data register 2 as it is, there are the following problems.

That is, if the processing result is written to the data register 2 as it is, when the data value of the data register 2 is stored in the external storage device 1, the order of the processed data and the data arranged in the external storage device 1 Is different from the order, when the bank is read for storage, S0, S2, S4, and S6 are read in every cycle, and S1, S3, S5, and S7 are read thereafter.

Here, S0, S1, and S are stored in the external storage device 1.
If the store is to be performed with S2,..., S7, it is necessary to rearrange the order in a store pipeline in a complicated manner, and there is a problem that wasteful processing time is spent for the rearrangement. Further, when executing a data conversion instruction in the ADD pipeline, if data to be processed is to be executed in the same order as the data arrangement in the external storage device 1, first, access is started from the bank 0 and S0 in the bank 0 is started. reading,
Next, when S1 is processed, there is a limited condition that one data is input to the ADD pipeline in one cycle. Therefore, even if S1 is read simultaneously with S0, it cannot be input to the ADD pipeline. If the same bank access is performed again without updating the address after performing the bank access and S1 is read and input to the ADD pipeline, the processing can be realized in the same order as the external storage device 1.

However, while data is read from the banks 1, 2, and 3 until the processing of S0 is performed until the processing of S1, the processing is not performed during that time. There is a new problem of deteriorating the performance. Further, in the conventional test method, all registers are checked using a scan path, and the test time becomes longer in proportion to the bit length of the register. In today's growing length, there has been a problem that the test time has become longer and the test cost has increased.

[Object] Accordingly, the present invention provides a microprocessor that rearranges data to be loaded or stored in a data register to optimize a processing procedure for all instructions and to shorten a test time. It is an object.

[0025]

SUMMARY OF THE INVENTION A microprocessor according to the present invention achieves the above object and has the features as set forth in claim 1.
Is a microprocessor for exchanging data with an external storage device, comprising: a data holding unit having m (m is a positive integer) bit width for holding data from the external storage device; Data input means for loading data into the data storage means; and data output means for storing data from the data storage means into the external storage device, wherein the data input means includes m / n (n Is a positive integer, and m ≧ n) bits of data is stored in k data storage units (k is a positive integer) .
Integer) from the m-bit side of each m-bit width or the 0-bit side
K data are successively stored in each m / n bit part from
And then from the m-bit side of each of the k m-bit widths or
In each of the second m / n bits from the 0-bit side, k
Stores data continuously and repeats storing similar data
From the m-bit side of each of the k m-bit widths or 0 bits
K data in the last m / n bits from the
After successive storage, the same applies to each of the next k m-bit widths.
When loading data by storing the data in
In both cases, the data output means is connected to the data holding means.
Data stored continuously in a predetermined order is
The external storage devices are stored in the order stored in the external storage device.
It is characterized in that it is stored in a store.

The invention described in claim 2 is the first invention.
The microprocessor of any of the preceding claims, wherein said data entry means is
Each of the stage and the data output means is provided with an upper side of data or
Characterized by having a plurality of selectors for selecting the lower side
are doing. The invention described in claim 3 is the same as the invention described in claim 1.
LSI external pins are set in the microprocessor
The data input means and the data
A latch connected to the output of the output means;
By providing an input / output switching signal to the
Control input and output of test data to
I have. The invention described in claim 4 is the same as the invention described in claim 3.
In the microprocessor, the data input means and the
Each of the data output means is connected to an arithmetic unit and a selector via a selector.
And connected to the data holding means.
You.

The invention described in claim 5 is the same as the invention described in claim 3.
The microprocessor of any of the preceding claims, wherein said data entry means is
The output of the stage and the input of the data output means are connected via a selector.
It is characterized by being connected. Claim 6
The invention described in (3) provides the microprocessor according to claim 3
Wherein a latch is provided at the last stage of the data input means,
The first data input to the input means is stored in the latch as the first data.
The data is fixed and output to the computing unit as
Data input to the data input means for the second operation
It is characterized in that it is sequentially output as data to the arithmetic unit .
You. Further, the invention according to claim 7 is a method according to claim 3.
In the microprocessor, the data input means
Of the data in the selector based on the test code
Test the operation of the selector by performing a wap process
It is characterized by doing.

[0028]

According to the present invention, data input means and data output means are provided.
The stage, when loading data from the external storage device to the data holding means, and load continuously in a predetermined order suitable data of m / n-bit width from the external storage device in pipeline processing, data retention When storing data from the means to the external storage device, data stored continuously in a predetermined order suitable for pipeline processing is stored in the order stored in the external storage device, and rearrangement of the data arrangement is performed. Done.

That is, since a data array that is optimal for the instructions of the microprocessor is obtained, the performance of the processor is sufficiently exhibited, and the processing procedure is optimized for every instruction. Also, at the time of testing, a latch is provided for connecting the input of the data input means and the output of the data output means, and the input / output of test data to / from the latch is controlled by a switching signal provided via an external pin. The test inside the processor is easily performed in a short cycle, and the test time is shortened.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 3 are diagrams showing an embodiment of a microprocessor according to the present invention, and FIG. 1 is a block diagram showing a main part configuration of the present embodiment. First, the configuration will be described.

In FIG. 1, the same reference numerals as those of the conventional example shown in FIG. 15 indicate the same parts. The microprocessor of this embodiment is roughly divided into an external storage device 1, a data register 2 as data holding means, and a data input / output device.
Input / output device 3 as input means and data output means , terminal 4
The input / output device 3 includes a load pipeline LP,
It comprises a store pipeline SP and a control circuit CC.

FIG. 2 is a diagram showing a schematic configuration of the load pipeline of FIG. As shown in FIG. 2, the load pipeline LP includes a plurality of latches R1, R2, R3U, R3.
L, R4U, R4L, R5U, R5L, R6 and a plurality of selectors S1 to S8. In the figure, LL is a latch of the I / O unit, and DI is a latch LL.
The data output from the DIU is the upper side (MSB)
, And DIL is the lower-order (LSB) 32-bit data.

D is 64-bit data output from S1 and S2, DU is 32-bit data on the upper side (output of MSB and S1), and DL is lower side (LSB and LSB).
S2 output) 32-bit data. Table 2 shows the selection conditions of the selector in the load pipeline LP. The load store flag described below is
Sort data when loading or storing data
Means an internal signal to perform. For example, in this embodiment,
As shown, the internal registers of the microprocessor
If the data is divided into four groups, four consecutive data
Data is grouped into 4
Need to be handled. For this reason, the fourth data
The first data is A, the second data is B, the third data
Data with C and the fourth data with D
To distinguish between the four data
For distinguishing between four sets of data
It is. Thus the load store flag stride
Direction, the form of the beginning of data (in this embodiment,
And misalignment).
In both cases, load pipeline LP or store pipeline
This is one of the selection conditions of the selector in the SP.

[0034]

[Table 2]

That is, the condition that the selector S1 selects the DIL is that the 32-bit stride = −1, or that the 32-bit width data exists discontinuously at the lower side of the 64-bit width and that the lower side Is valid, or the load pipeline test code is “1”, otherwise the DIU is selected. Similarly, the condition for the selector S2 to select the DIU is that the 32-bit stride = −1, or that the 32-bit width data exists discontinuously on the upper side of the 64-bit width and that the data on the upper side Is valid, or when the load pipeline test code is “1”; otherwise, DI
Select L.

Hereinafter, the conditions for selecting DU by the selector S3 are as follows: 32-bit stride = ± 1, 32-bit aligned and load / store flag = B, or 32-bit stride = ± 1, and 32 Bit misalignment and load store flag = C or load pipeline test code '8'. On the other hand, the conditions for selecting DL are 32 bit stride = ± 1 and 32 bit alignment. And when the load store flag = A, or when the 32-bit stride = ± 1 and the 32-bit misalignment and the load store flag = B, or when the load pipeline test code is “9”. Yes, otherwise select the output of the previous stage latch. Here, the load store flag signal is a signal for controlling the load pipeline LP,
As will be described in detail later, when a data load instruction of the microprocessor is activated and the load pipeline starts, signals A, B, C, and D representing four conditions are generated based on a clock inside the microprocessor, and the load pipe is generated. This is used for line control.

The condition for selecting the DU by the selector S4 is 6
In the case of 4-bit data, in the case of non-consecutive 32 bits, or in the case of 32 bits stride = ± 1 and 32
If bit-aligned and load-store flag = A, or 32-bit stride = ± 1 and 32
Bit misalignment and load store flag = B, or load pipeline test code '6'. On the other hand, the condition for selecting DL is that 32 bit stride = ± 1 and 32 bit miss Alignment and load store flag = A, or load pipeline test code '7', otherwise select output of previous latch.

The condition that the selector S5 selects the DU is the case of indirect load (32, 64 bits) or the case of the load pipeline test code '4' or '5'. Select output. In addition,
Indirect loading refers to a case where an address having actual data is stored in data at a specified address. The conditions for selecting DU by the selector S6 are as follows: 32-bit stride = ± 1 and 32-bit aligned and load store flag = D, or 32-bit stride = ± 1 and 32-bit misaligned and , Load store flag = B, or load pipeline test code '5'. On the other hand, the conditions for selecting DL are as follows: 32-bit stride = ± 1, 32-bit aligned, and load store When the flag = C, or when the 32-bit stride = ± 1 and the 32-bit misalignment and the load / store flag = D,
Or, it is the case of the load pipeline test code '4', otherwise, the output of the preceding stage latch is selected.

The condition for selecting the DU by the selector S7 is the data register test, the operation pipeline test, or the load pipeline test codes '0', '1', '2', '3'. Or the case of all of the store pipeline test codes, and otherwise, selects the output of the pre-stage latch. The conditions under which the selector S8 selects a DU are as follows: 32-bit stride = ± 1, 32-bit aligned and load store flag = C, or 32-bit stride =
± 1 and 32-bit misalignment and load store flag = D or load pipeline test code '3'. On the other hand, the condition for selecting DL is 32-bit stride = ± 1. , And a 32-bit misalignment and the load store flag = C,
Or, in the case of a data register test, in the case of an arithmetic pipeline test, in the case of any of the load pipeline test codes '0', '1', '2', or in the case of all store pipeline test codes Is the case,
Otherwise, select the output of the preceding latch.

Selector S * of load pipeline LP
Works under the above conditions, and the load pipeline L
All the P latches R * operate with an interlocked clock. Here, the clock with an interlock is
Microprocessor separately from clock supplied from outside
This is a clock generated inside the server. As shown in FIG.
In addition, the interlocked clock
Data access end signal (DC # X)
You. That is, the data access end signal (DC # X)
When not returning (in FIG. 12, DC # X is High)
), An interlocked clock is generated
Absent. FIG. 3 is a diagram showing a schematic configuration of the store pipeline of FIG. The store pipeline SP includes a plurality of latches R11, R12U, R12L, R1 as shown in FIG.
3U, R13L, R14U, R14L, R15U, R1
5L, R16, R17 and a plurality of selectors S11-S2
And 2.

In the figure, DS is 64-bit data from the data register 2, and DSU is on the upper side (MS
B) 32-bit data, DSL is the lower side (LS
B) is 32-bit data. DS5U is the output of latch R15U, DS5L is the output of latch R15L,
DSI is the output of the selector S19, DSJ is the selector S2
The output of 0 and DS7 are the outputs of the latch R17, each of which is 32-bit data.

Table 3 shows the selection conditions of the selector in the store pipeline SP.

[0043]

[Table 3]

That is, the condition that the selector S11 selects the DSL is a case where the 32-bit data (other than the indirect load) and the load / store flag = C or a case where the store pipeline test code is “8”. Otherwise, select the output of the pre-stage latch. Hereinafter, S12 is DS
The condition for selecting U is when 32-bit data (other than indirect load) and load store flag = A, or
This is the case of the indirect store or the case of the store pipeline test code '7'. In other cases, the output of the preceding stage latch is selected.

The condition for selecting DSL in S13 is that 32-bit data (other than indirect load) and load store flag = D, or indirect store, or
This is the case of the hard pipeline test code '7', and otherwise, the output of the preceding stage latch is selected. S14 is DS
The condition for selecting U is when 32-bit data (other than indirect load) and load store flag = C, or
For 64-bit data (other than indirect load), or
This is the case of the store pipeline test code '5' or '6'; otherwise, the output of the previous stage latch is selected.

The condition for selecting DSU in S15 is a case where 32-bit data (other than indirect load) and the load / store flag = B or a case where the store pipeline test code is “6”. The condition to be selected is the case of 64-bit data (other than indirect load) or the store pipeline test code '5'. Otherwise, the output of the preceding latch is selected.

The condition for selecting the DSU in S16 is the case of the store pipeline test code '3' or '4', and otherwise selects the output of the preceding latch. S17
Selects DSL when 32-bit data (other than indirect load) and the load / store flag = D, or when the store pipeline test code is “3” or “4”. Select the output of the preceding latch.

The condition for selecting DS in S18 is the case of operation by one clock operation signal (signal generated due to delay of DC # X signal (end signal of data access from memory)) or the non-continuous operation of 32 bits. Or
Store pipeline test code '0', '1', '2'
Is the case of all of the load pipeline test codes, and otherwise selects the output of the preceding stage latch. The condition for selecting DS5U in S19 is the case of the operation based on the one-clock operation signal or the case of the store pipeline test code '4'. In other cases, the output of the pre-stage latch is selected.

The condition for selecting DS5L in S20 is the case of operation by one clock operation signal or the case of store pipeline test code '4'.
Select the output of the preceding latch. The condition for selecting DSJ in S21 is the case of 32-bit stride = −1 and 32-bit alignment, or the case of store pipeline test code '1'. On the other hand, the condition for selecting DS7 is 32 bits. This is the case of stride = + 1 and 32-bit misalignment, or the case of store pipeline test code '2'. Otherwise, the output of the preceding latch is selected.

The condition for selecting DSJ in S22 is that the condition is non-consecutive 32 bits, or that the condition of 32 bits stride = +
1 and 32-bit misalignment, or 3
In the case of 2-bit stride = −1 and 32-bit alignment, or store pipeline test code “1”
On the other hand, the condition for selecting DS7 is a condition in which 32-bit stride = + 1 and 32-bit misalignment, or store pipeline test code '2'
Otherwise, the output of the preceding latch is selected.

The selector of the store pipeline functions under the above conditions, and all the latches R ** of the store pipeline SP except the latch R17 operate with the interlocked clock, and only the latch R17 operates as the master clock. Works with Next, the operation will be described.

The basic operation of the microprocessor according to the present embodiment is as shown in FIG. 4 when data is loaded from the external storage device 1 to the data register 2 in advance by loading the data with the image shown in FIG. . FIG. 5 shows an operation in which bank access is performed by data storage as shown in FIG. 4 and processing is performed by the ADD pipeline.

In the data register, as shown in FIG.
Data is stored in the external storage device 1 in an order that can be stored as it is. When data is loaded from the external storage device 1 to the data register 2 of the microprocessor, 32-bit data must be arranged so that the performance is improved for all instructions. It is desirable that the data is replaced and loaded and stored in the data register 2, which is considered to lead to an improvement in the performance of the processor.

When the data of the data register 2 after processing is stored in the external storage device 1, the 64-bit data need only be stored as it is in the above-described data conversion instruction. However, the 32-bit data must be rearranged. Then, an operation of restoring the data sorted and rearranged at the time of loading is performed. Therefore, in the present embodiment, as shown in FIG. 19, data is recombined and loaded or stored from the external storage device 1 to the data register 2 of the microprocessor.

First, the operation of rearranging data will be described with reference to an example of continuous loading of 32-bit data (8 data items). There are various methods for storing data stored in the external storage device 1, and the data array stored in the external storage device 1 may be, for example, an array as shown in FIG.

However, in this embodiment, data of 32 bits continuous data is stored as shown in the image of the data register 2 in the microprocessor shown in FIG. 8 regardless of the data arrangement. Note that loading of a non-continuous data array of 32-bit data or a 64-bit data array requires
The data is directly loaded into the data register 2 in the microprocessor except for the bit misaligned data.

Hereinafter, an operation example at the time of loading data will be described in detail. The data to be loaded is, for example, data of 32 bits, stride + 1, and misalignment as shown in FIG. 7, the external storage device 1 is a device capable of accessing 0 wait (no wait), and a bus of the microprocessor. The timing method employs a method in which data can be accessed in one clock after executing two clocks in the basic cycle.

First, as shown in FIG. 1, the data is rearranged in the load pipeline LP and output to the data register 2. A signal from the control circuit CC of the input / output device 3 is used for control. FIG. 9 is a timing chart showing a data flow in the load pipeline.

A main signal for controlling the load pipeline LP is a load store flag signal. As shown in FIG. 9, the load store flag signal is generated by detecting the rising edge of the clock at which the data load instruction of the microprocessor is activated and the start signal is asserted to the load pipeline LP. A, B, C, D, A, B, C,
.., And signals A, B, C, and D representing four conditions are generated as internal signals for rearranging data at the time of data loading from the clock with an interlock inside the microprocessor. And load pipeline LP
Is used for the control of

Note that information on the alignment / misalignment of the data used for control of the select signal and information on 32 bits and some stride are received from other units in the microprocessor. Therefore, X-0, 1-2, 3-4, which are input to the load pipeline LP,
The data of 5-6 and 7-X are latches R of 32 bits width.
1, R2, R3U, R3L, R4U, R4L, R5U,
0-4,1-5,2-6,3-7 via R5L, R6
In other words, a data arrangement that is converted and is optimal for the instructions of the microprocessor is obtained.

Next, an operation example when data is stored will be described in detail. The data to be stored is the same as the data used in the description of the operation at the time of loading, and is stored under the same conditions. When the data is stored from the data register 2 to the external storage device 1, the image shown in FIG. 10 is obtained.
FIG. 11 is a timing chart showing a data flow in the store pipeline.

0-4 output from the data register 2,
The data of 1-5, 2-6, and 3-7 are stored in latches R11, R12U, R12L, and R13 of the store pipeline SP.
U, R13L, R14U, R14L, R15U, R15
It is controlled by L, R16, R17 and selectors S11 to S22, and is output in a format stored in the external storage device 1.

That is, as in the case of loading, by detecting the rising edge of the clock in which the start signal is asserted in the store pipeline SP, the data is stored as an internal signal for rearranging the data when storing the data.
Signals A, B, C, and D representing four conditions are generated and used for controlling the store pipeline SP. Note that, for example, information such as the type of data is provided from another unit in the same manner as the control of the load pipeline LP. However, at the time of data storage, a one-clock operation signal is generated, and the control of the store pipeline SP is performed. Used.

The one-clock operation signal at the time of data storage is used to prevent a delay in data supply to the external storage device due to a delay in the DC # X signal (end signal of data access from the memory).

FIG . 12 illustrates one clock operation.
It is a timing chart. Note that in FIG.
3 shows R15U and R15L in FIG.
R16 in the middle is shown.

In FIG . 12, zero wait of 64-bit data
(No weight) A store that assumes a storage device
However, as for the data, the basic cycles T ₁ and T ₂ P1 are executed.
Before entering pipeline mode (1 clock access)
Address and data are transferred to the microprocessor every clock.
Output from Sessa.

Next, load pipeline LP and store
The test of the pipeline SP will be described. Selector and
In case of LSI test including latch, read scan path
Failure analysis is often performed by using a selector or latch.
As the number of test items increases, the test time becomes longer.
There is a need for a test that can detect a failure between the two.

The input / output device of the present invention stores a test code in a cash register.
By setting the value and decoding the value
Opens and closes the path selector and stores it in the register as usual.
And read the test data immediately via the data bus.
I try to make it.

For the data to be provided, a dedicated terminal 4 for applying an input / output switching signal to an external pin of the LSI is provided.
When asserted, data can be given the same state as when loading, that is, externally given data, and if it is negated, data can be given the same state as when storing, that is, data can be output from the processor. I do.

FIG. 13 is a block diagram for explaining the operation at the time of testing in this embodiment. Specifically, taking the load pipeline LP as an example, the operation during the test will be described with reference to FIG. 2 and Table 2 (selection conditions of the load pipeline LP). First, when the test code “0” of the load pipeline LP is set, the data of the latches R5U and R5L on the most output side of the load pipeline LP are input, and are transmitted via the latch R16 on the most output side of the store pipeline SP. Thus, data is read from the input / output latch 5.

Next, when the test code "1" of the load pipeline LP is set, the data is swapped by the selector S1 of the load pipeline LP, and the output signal is output as in the case of the test code "0". Side latch R5U, R
Data is input at 5L, latched one stage by latch R16 of store pipeline SP, and read from input / output latch 5.

That is, whether or not the selector S1 of the load pipeline LP has failed is checked by the test code '1'. As described above, since the test code is entangled in the selection conditions of all the selectors S1 to S8 of the load pipeline LP, arbitrary data is input by changing the test code, and the load pipe is read by reading this data. It is possible to check all the latches and selectors of the line LP.

The same is true not only for the load pipeline LP but also for the store pipeline SP. The test code of the store pipeline SP is set, and the latches of the store pipeline SP are passed through the load pipeline LP one stage. And selectors can be tested. In addition, as shown in FIG.
A selector 6 and a TS selector 7 are provided.
The two selectors 6 and 7 are for selectively coupling the load pipeline LP and the store pipeline SP when testing the load pipeline LP and the store pipeline SP.

That is, normally, the path from the load pipeline LP to the data register 2 is selected, and the data input to the store pipeline SP is selected from the data register. When a test is performed on each operation unit (not shown) in the microprocessor, a path for directly supplying operation data for testing from the load pipeline LP to the operation unit is provided in the TL selector, and a test of each operation unit is performed. A path through which the operation result can be read from the store pipeline SP is also provided.

As described above, data is directly supplied to the arithmetic unit,
And the reason for storing directly, as in normal operation,
The arithmetic unit performs an operation by supplying data from the data register 2 loaded with predetermined data, and the operation result is stored again in the data register 2 and the result of the data register 2 is stored. When,
This is because a long time is required for the test time, and if a failure occurs in the data register 2, the test of the arithmetic unit becomes impossible at all.

Therefore, in this embodiment, at the time of testing, data is input by an input / output switching signal, and two pieces of data to be operated and operation data are generated as operation data and supplied to the operation pipeline. After the data calculated by the arithmetic unit passes through the TS selector 7, the data is stored in the store pipeline SP.
Is output to the outside through one step.

Incidentally, the latch R6 in FIG. 2 is a latch used only at the time of the operation unit test. After the input / output switching signal is input and the data is latched one stage by the latches R5U and R5L, the latch R6 is the first data. Is latched by the latch R6 , and the data input after the first data is latched by the latches R5U and R5L and output to the normal data register 2 path. Therefore, in the case of the test of the operation pipeline, it is possible for the TL selector 6 to select the two paths described above as the data to be operated and the operation data and supply the data to the operation pipeline. The data referred to here is 64
The data has a bit width, and may be two data of 64-bit data or 32-bit data.

The means for outputting the operation test result to the outside by the store pipeline SP via the TS selector 7 is the same as that at the time of testing the load pipeline LP, except that the data selected by the TS selector is different. FIG. 14 is a timing chart showing the operation of the input / output device when testing an ADD pipeline having two pipeline stages.

Here, the data to be operated is latched once by the latch R6 and fixed, but may be switched every cycle similarly to the latch R5. This allows the arithmetic unit to:
You can check the result with the stored data that is operating normally. As described above, in the present embodiment, data is loaded into the data register 2 or stored in the data register 2 without wasting the performance of the processor with all instructions in the microprocessor.

Further, a fault location can be detected in a short cycle at the time of a test, and a test can be easily performed by providing a path through which a result can be read in a short cycle even in a test inside the processor.

[0081]

According to the present invention, data input means and data
When data is loaded from the external storage device to the data holding device by the output unit , m / n-bit-width data from the external storage device is continuously loaded in a predetermined order suitable for pipeline processing. When storing data from the holding unit to the external storage device, data stored continuously in a predetermined order suitable for pipeline processing is stored in the order stored in the external storage device, and rearrangement of the data arrangement is performed. It can be performed.

Therefore, by rearranging the data to be loaded or stored in the data register, it is possible to obtain a data arrangement that is optimal for the instructions of the microprocessor. Thus, the performance of the processor can be sufficiently exhibited. Further, at the time of testing, since test data is input / output via the load pipeline LP and the store pipeline SP of the data input / output device, the internal test of the processor can be easily performed in a short cycle, and the test time can be reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a main part of the present embodiment.

FIG. 2 is a diagram showing a schematic configuration of a load pipeline of FIG. 1;

FIG. 3 is a diagram showing a schematic configuration of a store pipeline of FIG. 1;

FIG. 4 is a diagram for explaining writing to a data register in the embodiment.

FIG. 5 is a diagram showing read and write timings in the embodiment.

FIG. 6 is a diagram illustrating a data array stored in a data register according to the present embodiment.

FIG. 7 is a diagram showing various data arrays.

FIG. 8 is a diagram illustrating a data image stored in a data register according to the present embodiment.

FIG. 9 is a timing chart showing a data flow in the load pipeline.

FIG. 10 is a diagram illustrating an image when data is stored from a data register to an external storage device.

FIG. 11 is a timing chart showing a flow of data in a store pipeline.

FIG. 12 is a timing chart for explaining one-clock operation.

FIG. 13 is a block diagram for explaining an operation at the time of a test in this embodiment.

FIG. 14 is a timing chart showing the operation of the input / output device when testing an ADD pipeline having two pipeline stages.

FIG. 15 is a block diagram showing an input / output device of a conventional microprocessor.

FIG. 16 is a diagram illustrating an operation example of an input / output device of a conventional microprocessor.

FIG. 17 is a diagram illustrating an operation example in a bank slot and an operation pipeline.

FIG. 18 is a diagram for explaining access timing to a data register.

FIG. 19 is a diagram showing an image when data is loaded from an external storage device to a data register.

FIG. 20 is a diagram for explaining writing to a data register in a conventional example.

FIG. 21 is a diagram showing read and write timings in a conventional example.

FIG. 22 is a diagram showing a data array stored in a conventional data register.

FIG. 23 is a block diagram showing a test configuration in an input / output device of a conventional microprocessor.

[Explanation of symbols]

 Reference Signs List 1 external storage device 2 data register (data holding means) 3 input / output device (data input means, data output means) 4 terminal 5 input / output latch 6 TL selector 7 TS selector LP load pipeline LP SP store pipeline SP CC control circuit LL latch L latch

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiroyuki Fujiyama 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kenji Shirasawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited ( 56) References JP-A-59-75365 (JP, A) JP-A-3-28962 (JP, A) JP-A-1-84339 (JP, A) JP-A-58-145233 (JP, A) 63-650738 (JP, A) JP-A-1-1050 (JP, A) JP-A-3-34138 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12 / 04 G06F 9/38 G06F 15/78

Claims (7)

(57) [Claims] 1. A microprocessor for exchanging data with an external storage device, comprising: a data holding means having an m (m is a positive integer) bit width for holding data from the external storage device; Data input means for loading data into the data holding means; and data output means for storing data from the data holding means in the external storage device, wherein the data input means includes an m / m from the external storage device. n
(N is a positive integer and m ≧ n) bit width data
Each of the k (k is a positive integer) m bit
M / n bits from the m-bit side or 0-bit side of the
K data are successively stored in the
From the m-bit side or 0-bit side of each m-bit width
K data are successively provided in each second m / n bit portion
And repeats storage of the same data to obtain the k
Last bit from the m-bit side or 0-bit side of the bit width
K data are continuously stored in each m / n bit portion
Thereafter, data is similarly stored in the next k m-bit widths.
Data loading means, and the data output means transmits the data to the data holding means in a predetermined order.
Data stored consecutively in the order
The external storage device is stored in the order stored in the storage device.
A microprocessor. 2. The microprocessor according to claim 1, wherein each of said data input means and said data output means has a plurality of selectors for selecting an upper side or a lower side of data. 3. An LSI external pin is provided.
Output and the contact of the input and the data output means over data input means
Connected to input / output switching signals
Input of test data to the latch.
2. The microphone according to claim 1, wherein output is controlled.
Processor. 4. The data input means and the data output means
Are each provided with an arithmetic unit and the data holding through a selector.
4. The microphone according to claim 3, wherein the microphone is connected to a device.
Cloprocessor. 5. An output of said data input means and said data output.
The input of the force means is connected via a selector.
4. The microprocessor according to claim 3, wherein 6. A latch is provided at the last stage of said data input means.
The first data input to the input means to the latch.
The data is fixedly output as the first operation data and output to the operation unit, and the subsequent data input to the data input means is output as the second data.
It is characterized in that it is sequentially output to the arithmetic unit as arithmetic data
4. The microprocessor according to claim 3, wherein: 7. The method according to claim 7, wherein said data input means includes a test code.
Swaps data in the selector based on the
Test the operation of the selector.
4. The microprocessor according to claim 3, wherein