JPH01133735U - - Google Patents
Info
- Publication number
- JPH01133735U JPH01133735U JP2925488U JP2925488U JPH01133735U JP H01133735 U JPH01133735 U JP H01133735U JP 2925488 U JP2925488 U JP 2925488U JP 2925488 U JP2925488 U JP 2925488U JP H01133735 U JPH01133735 U JP H01133735U
- Authority
- JP
- Japan
- Prior art keywords
- wire bonding
- pattern
- hybrid integrated
- frequency hybrid
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例の概略図、第２図は
従来の概略図である。
１…基板、２…ボンデイングワイヤ、３…搭載
部品、４…導体パターン、５…導体パターン上の
切欠き。
FIG. 1 is a schematic diagram of an embodiment of the present invention, and FIG. 2 is a conventional diagram. DESCRIPTION OF SYMBOLS 1... Board, 2... Bonding wire, 3... Mounted component, 4... Conductor pattern, 5... Notch on conductor pattern.
Claims (1)
デイングで電気的接続を行う高周波混成集積回路
において、導体パターン上の一部にワイヤボンデ
イング位置を示す目安となるパターンを設け、そ
れを目安にワイヤボンデイングすることを特徴と
する高周波用混成集積回路。 In high-frequency hybrid integrated circuits that use wire bonding to electrically connect components mounted on a board and conductor patterns, a pattern is provided on a portion of the conductor pattern to indicate the wire bonding position, and wire bonding is performed using that pattern as a guide. A high frequency hybrid integrated circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2925488U JPH01133735U (en) | 1988-03-04 | 1988-03-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2925488U JPH01133735U (en) | 1988-03-04 | 1988-03-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01133735U true JPH01133735U (en) | 1989-09-12 |
Family
ID=31253303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2925488U Pending JPH01133735U (en) | 1988-03-04 | 1988-03-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01133735U (en) |
-
1988
- 1988-03-04 JP JP2925488U patent/JPH01133735U/ja active Pending