JPH01133240U - - Google Patents
Info
- Publication number
- JPH01133240U JPH01133240U JP2468688U JP2468688U JPH01133240U JP H01133240 U JPH01133240 U JP H01133240U JP 2468688 U JP2468688 U JP 2468688U JP 2468688 U JP2468688 U JP 2468688U JP H01133240 U JPH01133240 U JP H01133240U
- Authority
- JP
- Japan
- Prior art keywords
- field
- forming
- mentioned
- scanning line
- diagram showing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000003550 marker Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Description
第1図はトラツキングモニタ全体の構成を表わ
すブロツク図を、第2図は2チヤンネル分離切換
え回路例を示す図、第3図は分離表示のタイミン
グチヤート(クロツク源4fsc)、第4図はフ
イールド毎の切換えイメージを示す図、第5図は
2画面分離回路の構成を示すブロツク図、第6図
は他の実施例における分離表示のタイミングチヤ
ート、第7図はその場合のフイールド毎の切換え
イメージを示す図、第8図は1画面表示モードお
よびA,Bチヤンネル分離モードにおけるモニタ
表示形式を示す図である。
1……R―DAT駆動機構、2……トラツキン
グ誤差信号、3……増幅器、4……A/D変換器
(86ビツト)、5……記憶装置、6……水平パ
ルス発生器、7……分離―非分離切換え回路、8
……マーカミキサ、9……同期信号ミキサ、10
……ビデオ駆動器、11……モニタ、12……ブ
ランキング信号(BLK)、13……トリガ用
HD(HD′)、14……クロツク 4fsc,
2fsc、15……FLD、16……HD、17
……1/2HD、18……水平パルス、C1,C
2……バイナリ計数器、FF1,FF2……フリ
ツプフロツプ、MPX……マルチプレクサ。
Figure 1 is a block diagram showing the overall configuration of the tracking monitor, Figure 2 is a diagram showing an example of a 2-channel separation switching circuit, Figure 3 is a timing chart for separate display (clock source 4fsc), and Figure 4 is a field diagram. 5 is a block diagram showing the configuration of a two-screen separation circuit, FIG. 6 is a timing chart of separate display in another embodiment, and FIG. 7 is an image of switching for each field in that case. FIG. 8 is a diagram showing the monitor display format in the single screen display mode and the A and B channel separation mode. DESCRIPTION OF SYMBOLS 1...R-DAT drive mechanism, 2...Tracking error signal, 3...Amplifier, 4...A/D converter (86 bits), 5...Storage device, 6...Horizontal pulse generator, 7... ...Separation-non-separation switching circuit, 8
... Marker mixer, 9 ... Synchronous signal mixer, 10
...Video driver, 11...Monitor, 12...Blanking signal (BLK), 13...For trigger
HD (HD'), 14...clock 4fsc,
2fsc, 15...FLD, 16...HD, 17
...1/2HD, 18...Horizontal pulse, C1, C
2...Binary counter, FF1, FF2...Flip-flop, MPX...Multiplexer.
Claims (1)
示可能部を形成し、1フイールドを作成する手段
、 (b) 1ラインの走査線の後半部のみに第2の表
示可能部を形成し、他の1フイールドを作成する
手段、 (c) 上記1フイールドと他の1フイールドを交
互に加えて、1フレームを形成する手段、 (d) 上記第1の表示可能部に一方のヘツドに対
応する誤差信号を加える手段、および (e) 上記第2の表示可能部に他方のヘツドに対
応する誤差信号を加える手段。 を含むことを特徴とするトラツキングモニタ2
チヤンネル分離表示装置。[Claims for Utility Model Registration] (a) Means for forming a first displayable portion only in the first half of one scanning line to create one field; (b) Only the second half of one scanning line (c) means for forming one frame by alternately adding the above-mentioned one field and another one field; (d) the above-mentioned first field; and (e) means for applying an error signal corresponding to the other head to the second displayable portion. Tracking monitor 2 characterized by including
Channel separation display device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2468688U JPH01133240U (en) | 1988-02-25 | 1988-02-25 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2468688U JPH01133240U (en) | 1988-02-25 | 1988-02-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01133240U true JPH01133240U (en) | 1989-09-11 |
Family
ID=31244753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2468688U Pending JPH01133240U (en) | 1988-02-25 | 1988-02-25 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01133240U (en) |
-
1988
- 1988-02-25 JP JP2468688U patent/JPH01133240U/ja active Pending
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