JPH011325A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a three-state output semiconductor device used in an interface between devices.

[Conventional technology]

FIG. 5 is a circuit diagram showing the input and output sections of a conventional semiconductor device with three-state output using the 0M08 circuit.

In the figure, reference numeral 1 denotes an inverter constituting an input section, and a high-potential power supply voltage V serving as a first power supply. 1 in series between the power supply terminal 2 to which 0 is supplied and the GND window 3 which is the second power supply.
It consists of a P-channel MOS transistor Q1 and an N-channel MOS transistor Q2 which are connected in parallel, and these two M
A common connection point between the gates of the OS transistors Q and Q2 is connected to a data input terminal 5 via a human power protection resistor 4. Input protection diodes 6 and 7 for surge absorption are connected between the data input terminal 5 and the power supply terminal 2 and between the data input terminal 5 and the GNDra element 3, respectively.

On the other hand, between the power supply terminal 2 and the GND terminal 3 are P-channel MOS transistors Q3 and N-7- which constitute the output section.
Janel MOS transistors Q4 are connected in series, and the connection point between these MOS l-transistors Q3 and Q4 is an output terminal 8. 9 is an internal circuit provided between the input section and the output section, which controls each M of the output section based on the output signal of the inverter 1 and the signal applied to the output enable terminal 10.
O8l - configured to control transistors Q, Q4. An example of a specific configuration of the internal circuit 9 is shown in FIGS. 6 and 7.

The input/output section of the conventional semiconductor device with three-state output is configured as described above, and when a predetermined signal level is applied to the output enable terminal 10 and the output section is enabled,
A signal according to the signal applied to the data input terminal 5 is derived to the output terminal 8. For example, “
When the H" level signal is applied, the output of the inverter becomes the "L" level, and in response, the internal circuit 9 outputs the output section MOS transistor Q3. A gate voltage of ``L'' level is applied to Q4, and thereby M
OS I - transistor Q3 is on, MOS.

Transistor Q4 turns off and output terminal 8 becomes “H”.
Conversely, when a signal of "L" level is applied to the data input terminal 5, the output of the inverter becomes "H" level, and in response, the internal circuit 9 outputs a signal of "H" level. A gate voltage of "H" level is applied to each of the MOS transistors Q and Q4 in the output section, which turns MOS transistor Q3 off, turns MOS transistor Q4 on, and outputs a signal of "L" level to output terminal 8. Ru.

On the other hand, when the signal level applied to the output enable terminal 10 is reversed and the output section becomes disabled, a gate voltage of 1H'' level is applied from the internal circuit 9 to the MOS transistor Q3, and a low level is applied to the MOS transistor Q4. The gate voltages of the same level are respectively applied, and the MOS transistor Q304 is turned off at 6, and the output terminal 8 is placed in a high impedance state.

[Problem that the invention seeks to solve]

In the conventional semiconductor device with three-state output as described above, the output section includes P-channel and N-channel MOS transistors Q3. Since Q4 is used, parasitic diodes 11° and 12 are installed between the output terminal 8 and the power supply terminal 2 and between the output terminal 8 and the GND terminal 3, respectively, as shown in the cross-sectional view of the output section in FIG. will be formed. Therefore, the output terminal 8 of this semiconductor device with 3-state output is supplied with another power supply voltage (2) as shown in FIG. 0' is connected to the input terminal 15 of the system 14 having the power supply terminal 13 supplied with 0', when the power supply to the semiconductor device with 3-state output is stopped and only the system 14 is operated, the system 14 is When the input terminal 15 becomes "H" level, current flows into the power supply terminal 2 side via the parasitic diode 11, and the power supply terminal 2 is raised to "H" level.
There is a problem in that a semiconductor device with a 3-state output operates even though the power is off.

Further, as shown in FIG. 10, another power supply voltage V is applied to the data input terminal 5 of the semiconductor device with three-state output. o
When the power supply to the semiconductor device with 3-state output is stopped and only the system 17 is operated while the output terminal 18 of the system 17 having the electric FA terminal 16 to which `` is supplied is connected, the system 17 When the output terminal 18 of the output terminal 18 becomes "H" level, a current flows into the power supply terminal 2 side through the input protection diode 6, and the semiconductor device with the 3-state output operates. Although this problem can be solved on the input side by removing the input protection diode 6, the input electrostatic breakdown voltage is significantly lowered, which is inconvenient.

This invention was made to solve these problems, and has a 3-state output that does not have a current path from another connected system to the high potential power supply side and has a high electrostatic breakdown voltage. The purpose is to obtain a semiconductor device.

[Means for solving problems]

A semiconductor device according to the present invention is a conductor device with a 3-state output whose output terminal is a connection point of two transistors connected in series between a first power source with a high potential and a second power source with a low potential, Of the two transistors, the transistor connected to the first power supply side is an NPN bipolar transistor, and the N-channel M transistor has a drain connected to the input terminal and a source and gate connected to the second power supply.
It is equipped with an OS transistor.

[Effect]

In this invention, since the transistor connected to the high potential power supply side of the output section is an NPN bipolar transistor, no output parasitic diode is formed between the high potential power supply and the output terminal, and no output parasitic diode is formed between the input terminal and the high potential power supply. There is no need to provide an input protection diode between the Therefore, when the power is turned off, there is no path for current to flow from another system to the high potential power supply side via the output terminal or input terminal. Further, a surge applied to the input terminal is absorbed by the action of an N-channel MOS transistor connected between the input terminal and the low potential power supply.

(Embodiment) FIG. 1 is a circuit diagram showing the input and output parts of a semiconductor device with a 3-state output according to the present invention.
10. Q, Q2. Q4 is the same as the above conventional device. Here, instead of the P-channel MoS transistor Q3 in the conventional device, an NPN bipolar transistor Q3 is used.
5 is connected in series with the MOS t-transistor Q4. The collector of the NPN bipolar transistor Q5 is connected to the power supply terminal 2 via a resistor 19, and the emitter of the NPN bipolar transistor Q5 and the MOS transistor Q
The connection point with 4 is an output terminal 8. Further, one output terminal of the internal circuit 9 is connected to an NPN bipolar transistor Q via an inverter 20 consisting of a P channel MOS transistor Q6 and an N channel MOS transistor Q1.
It is connected to the base of 5.

On the other hand, in the input section, the input protection diode 6.7 for surge absorption in the conventional device is omitted, and instead, an N-channel MOS transistor Q8 is provided between the data input terminal 5 and the GND terminal 3.

The drain of MOS transistor Q8 is connected to data input terminal 5.
The source and gate are connected to the GND terminal 3.

In the semiconductor device with a three-state output configured as described above, when a predetermined signal level is applied to the output enable terminal 10 and the output section is enabled, a signal according to the signal applied to the data input terminal 5 is output. Output terminal 8
It is derived from For example, when an “H” level signal is applied to the data input terminal 5, the output of the inverter 1 is 11 L.
" level, and in response, the internal circuit 9 outputs "L l?" to the next stage inverter 20. A level signal is applied to the MOS transistor Q4 of the output section, and a signal of the "L II level" is applied to the output section MOS transistor Q4.
A signal of "H++ level" is output from "H++ level", and the NPN bipolar transistor Q5 receiving this signal at its base turns on, while the "M" signal receiving a gate voltage of "Let level"
The OS transistor Q4 is turned off and the output terminal 8
An "H" level signal is output. Conversely, when a “L” level signal is applied to the data input terminal 5,
The output of the inverter 1 becomes "H" level, and in response, an "H" level signal is sent from the internal circuit 9 to the next stage inverter 20, and an "H" level signal is sent to the output section MOS transistor Q4.
"L" level signals are respectively applied. As a result, the inverter 20 outputs a "L" level signal, which is received by the NPN bipolar transistor Q5 at its base.
is in the off state, while the MOS transistor Q4 receiving the gate voltage of the bias voltage is in the on state, and a signal at the L II level is outputted to the output terminal 8.

On the other hand, when the signal level applied to the output enable terminal 10 is reversed and the output section becomes disabled, the internal circuit 9 transmits the Is level to the next stage inverter 20.
A signal of "L° level" is applied to each of the MOS transistors Q4, and as a result, an L level signal is output from the inverter 20, and the NPN bipolar transistor Q5 receiving this signal at its base is turned off.
The MOS transistor Q4 receiving the gate voltage at the 'L' level is also turned off, and the output terminal 8 is placed in a high impedance state.

In this semiconductor device with a 3-state output, an NPN bipolar transistor Q5 is connected to the high potential power supply side of the output section, so as shown in a cross-sectional view of the output section in FIG. No parasitic diode is formed between the emitters. Therefore, another power supply voltage V is applied to the output terminal 8 of the semiconductor device with three-state output, as shown in FIG. 0' is connected to the input terminal 15 of the system 14 having the power supply terminal 13 supplied with 0', when the power supply to the semiconductor device with 3-state output is stopped and only the system 14 is operated, the system 14 is Even if the input terminal 15 reaches the 'l-1' level, there is no path for current to flow towards the power supply terminal 2, so at this time the power supply terminal 2 will not be raised to the 'H° level', and therefore when the power is off Therefore, there is no problem that the semiconductor device with the 3-state output operates erroneously.

In addition, in this semiconductor device with a 3-state output, an N-channel MOS t-transistor Q8 is connected to the input section, and like the MOS transistor Q4 in FIG.
Since the substrate region where the OS t-transistor Q8 is formed is connected to the GND terminal 3, the drain of this MOS l-transistor Q8 and the GND terminal are connected as shown in FIG.
A parasitic diode 21 is formed between the I elements 3. Therefore, when a negative surge is applied to the data input terminal 5, a current-carrying path is created between the data input terminal 5 and the GNDra element 3 via the parasitic diode 21, and the surge is absorbed through this current-carrying path. That is, the parasitic diode 21 in this case plays the same role as the input protection diode 7 in the conventional device. On the other hand, if a positive surge is applied to the data input terminal 5, the MOS transistor Q8
The drain depletion layer expands due to the drain voltage (surge voltage) and overlaps the source depletion layer, and electrons are directly injected from the source into the depletion layer and returned to the drain. Therefore, a current flows between the drain and source and the surge is absorbed. That is, the MOS transistor 08 itself plays the same role as the input protection diode 6 in the conventional device. Due to the above-described action of the MOS transistor Q8, a high electrostatic wave WI withstand voltage is given to the input section.

Furthermore, in this case, data input terminal 5 and power supply terminal 2
Since there is no need to connect an input protection diode between them, the data input terminal 5 of the 3-state output "f = 1m conductor is connected to a power supply supplied with another power supply voltage V.rr as shown in FIG. Output terminal 1 of system 17 for terminal 16
When the power supply to the semiconductor device with 3-state output is stopped and only the system 17 is operated with 8 connected, even if the output terminal 18 of the system 17 reaches the 11 H11 level, the power is not supplied to the power supply terminal 2. There is no path for current to flow, and electricity is flowing! The A'18 child 2 is never raised to the H'' level, and therefore, there is no problem such as the semiconductor device with the 3-state output being erroneously operated when the power is turned off.

In the above embodiment, the MOS transistor Q4 is used as a transistor connected to the low potential power supply side in the output section, but the same effect can be obtained by using a bipolar transistor instead.

〔Effect of the invention〕

As described above, according to the present invention, an NPN bipolar transistor is used as the transistor connected to the high potential power supply side of the output section, and an N-channel M transistor is used, with the drain connected to the input terminal, and the source and gate connected to the low potential power supply.
Since an OS transistor is provided, no parasitic diode is formed between the output terminal and the high potential power supply, and there is no need to provide an input protection diode between the input terminal and the high potential power supply. Even if other systems connected to the output section or input section are operated in this state, no current will flow from the system to the high potential power supply side via the output section or input section, thereby preventing malfunctions. Also regarding electrostatic breakdown voltage,
A high breakdown voltage can be achieved due to the surge absorption effect of the N-channel MOS transistor connected to the input terminal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of the output section of the semiconductor device, and FIG. 3 shows a state in which another system is connected to the output section of the semiconductor device. 4 is a circuit diagram showing a state in which another system is connected to the input section of the semiconductor device, FIG. 5 is a circuit diagram showing a conventional semiconductor device, and FIGS. 6 and 7 are diagrams of the semiconductor device. A circuit diagram showing a specific example of the internal circuit of the device, FIG. 8 is a sectional view of the output section of the semiconductor device, FIG. 9 is a circuit diagram showing a state in which another system is connected to the output section of the semiconductor device, and FIG. FIG. 10 is a circuit diagram showing a state in which another system is connected to the input section of the semiconductor device. In the figure, 2 is a power supply terminal, 3 is a GND terminal, 8 is an output terminal P, Q4 . Q8 is an N-channel V channel MOS transistor, Q
5 is an NPN bipolar transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) In a semiconductor device having a 3-state output section whose output terminal is a connection point of two transistors connected in series between a first power source having a high potential and a second power source having a low potential,
Among the two transistors, the transistor connected to the first power supply side is an NPN bipolar transistor, and an N-channel MOS transistor is provided whose drain is connected to the input terminal and whose source and gate are connected to the second power supply. semiconductor devices. (2) The semiconductor device according to claim 1, wherein the transistor connected to the second power supply side of the two transistors is an N-channel MOS transistor.