JPH01130395A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To use a device as a SRAM as well as a ROM by using one of two power terminals as the power terminal through which a voltage is given to the whole of a circuit and using the other as a switching terminal which is used to select the memory cell state. CONSTITUTION:A second power terminal 8 is added to a conventional device. One of two power terminals 7 and 8 is used as the power terminal through which a voltage is given to the whole of the circuit, and the other is used as the switching terminal, and two power lines connected to these power terminals are connected to one-side ends of two high resistance load elements 15 and 16 in a memory cell. Thus, the device is used as a normal SRAM when the high level is given to the switching terminal, and it is used as a preliminarily determined ROM when the low level is given there.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to its memory cell and power supply terminal.

[Conventional technology]

FIG. 3 shows a general configuration of a semiconductor memory device including a static random access memory (hereinafter referred to as SRAM). In this figure, 31 is an input/output circuit, 32 is a row decoder, 33 is a memory cell array,
34 is a column decoder, 35 is an address input line, 36 is a data input/output line, 37 is a power supply terminal, and 38 is a ground terminal.

In the case of SRAM, the memory cells making up the memory array 33 generally have the configuration shown in FIG. In this figure, 41 to 44 are NMOS transistors;
5.46 is a high resistance load element.

In an SRAM with this kind of configuration, memory cells can be written/written.
It operates only as a normal readable static type memory cell, and cannot hold data in the memory unless power supply VCE is supplied from the power supply terminal 37.

Note that the basic operation of SRAM and the operation of static memory cells are well known to those skilled in the art, and therefore detailed explanation thereof will be omitted.

[Problem that the invention seeks to solve]

Conventional SRAM is configured as described above, so it cannot retain data when the power is turned off.
Generally known ROM (Re-ad only)
There were problems such as not having the characteristics of memory.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor memory device that can be used both as an SRAM and as a ROM.

[Means for solving problems]

A semiconductor memory device according to the present invention includes two power supply terminals as external terminals, two power supply lines connected to the power supply terminals inside the memory cell, and two high-resistance load elements within the memory cell. One end is connected to a first power supply line or a second power supply line, respectively, and one of the above two power supply terminals is used as a power supply terminal that applies voltage to the entire circuit, and the other is a switch for selecting the state of the memory cell. It is used as a terminal.

[Effect]

In this invention, one of the two power supply terminals is used as a power supply terminal that applies voltage to the entire circuit, the other is used as a switching terminal, and two power supply lines connected to this power supply terminal are connected to two high voltage terminals in the memory cell. By connecting one end of each resistive load element, the memory can be used as a normal SRAM when "H" is applied to this switching terminal.
If L'' is given, it can be used as a predetermined ROM.

〔Example〕

An embodiment of the present invention will be described below.

In FIG. 1, 1 is an input/output circuit, 2 is a row decoder, and 3 is a row decoder.
is a memory cell array composed of memory cells described below,
4 is a column decoder, 5 is an address input line, 6 is a data input/output line, 7 is a first power supply terminal, 8 is a second power supply terminal, and 9 is a ground terminal.

This configuration differs from the configuration of conventional devices in that a second power supply terminal is added.

Next, referring to FIG. 2, the memory cells constituting the memory array 3 of this embodiment will be explained. In Figure 2, 1
1 to 14 are 8MO3) transistors, and 15 and 16 are high resistance load elements. Furthermore, within the memory cell, there is a first . Two power supply lines Vccl and Vcc2 connected to the second power supply terminal 7.8 pass through, and the node a on one side of the high resistance load element 15 is connected to Vccl.
The node b on one side of the high resistance load element 16 is connected to V
Connected to cc2.

The operation of the memory cell shown in FIG. 2 will be explained by dividing it into the following four states.

(1) When Vccl = Vec2 '@H''' As in the case of the conventional example, it operates as a normal static type memory cell that can be written/read.

(2) Vccl=”H”+vcc2-”L
”, Vcc2 is s L I”, so node b
, the node f becomes L'', and the transistor 14 becomes non-conductive. Therefore, the node C is pulled up to Vccl, that is, the "H" level 5, the NMOS transistor 13 becomes conductive, and the node C becomes conductive. At "H" level, node d becomes latched at "L3 level".

In this state, when a read operation is performed on the memory cell, that is, when the word line WL is turned on, the bit line BL is 1H", and the bit line B
Information of "L" appears in L. In other words, this memory cell stores rlJ.

(3) In the case of Vcd-“L”, Vcc2-“H” (
The operation described in 2) is reversed, that is, this memory cell stores "0".

(4) In the case of Vccl-“L” and Vcc2-“L'”, the read operation from the memory cell cannot be performed.

The states (1) to (4) above correspond to case 1 of the memory cell state table shown in FIG. Case 2 is
Complementary to case 1, one end of two high resistance load elements are connected to Vce1, 2, and in case 3 and case 4, one end of two high resistance load elements are connected to Vea.
1, connected to Vce2.

In FIG. 5, the state of the - line is a state in which normal writing and reading cannot be performed, and it is prohibited in principle to put the memory cell into this state. Here, for example, Vccl is the power supply that applies voltage to the entire semiconductor integrated circuit using the memory according to this embodiment, and Vce2 is the power supply that applies voltage to the entire semiconductor integrated circuit using the memory according to this embodiment, and Vce2 is the power supply that applies voltage to the entire semiconductor integrated circuit using the memory according to this embodiment.
When set as a ROM switching terminal, the state of the memory cell can be changed within the range shown by the broken line in FIG.

In FIG. 6, the memory cell array 3 shown in (a) is A
It is assumed that the memory cells in the f+I area are connected as shown in Case 1 or 2 in FIG. 5 depending on arbitrary data, and the memory cells in the B area are connected as shown in Case 3.

When using the above semiconductor integrated circuit, if Vec2 is set to "H", the memory array 3 operates as an SRAM cell in both the A area and the B area as shown in (b), and the memory array 3 operates as a normal SR
It can be used in the same way as AM.

Also, if ■0,2-“L”, then A as shown in (C).
The memory cells in area 81 can be used as preprogrammed ROM cells, and the memory cells in area B can be used as ordinary SRAM cells.

It goes without saying that if the entire memory cell array is configured with memory cells of case 1 or case 2, the entire memory cell array can be used as RAM or ROM' by switching Vce2. Further, the power supply line of the peripheral circuit is naturally connected to Vccl (always given H'').

Note that the present invention applies not only to standalone SRAMs and ROMs, but also to RAMJs used as core cells in microprocessors, for example. This embodiment can also be applied to 3ROM, and produces the same effects as the above embodiment.

〔Effect of the invention〕

As described above, according to the semiconductor memory device according to the present invention,
Two power supply terminals are provided, one of which is set to “H”.
” or “L”, and connect the two power supplies connected to these power supply terminals to the two in the memory cell.
Since the memory array is connected to one end of two high resistance load elements, the memory array can be configured to operate as either an SRAM or a ROM, which has the effect of providing a memory with a wide range of applications.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a memory cell according to an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a conventional semiconductor memory device. FIG. 4 is a diagram showing the configuration of a conventional memory cell.
FIG. 5 is a diagram for explaining the state of a memory cell according to the present invention, and FIG. 6 is a diagram for explaining an example of use of the semiconductor memory device according to the present invention. 2 is a row decoder, 3 is a memory cell array, 4 is a column decoder, 5 is an address input line, 6 is a data input/output line, 7 is a first power supply terminal, 8 is a second power supply terminal, 15.16 is a high resistance load element. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A semiconductor memory device comprising two power supply terminals, a memory cell array, row and column decoders, data input/output lines, and address input lines, wherein each memory cell constituting the memory cell array is , through which two power lines are routed from the above two power supply terminals and respectively connected to one ends of the two high resistance load elements constituting the memory cell, and one of the above two power supply terminals is passed through. 1 is a power supply terminal for applying a voltage to the entire circuit, and the other is a switching terminal for selecting the state of the memory cell by switching between "H" and "L".