JPH01130250A - Memory transfer system - Google Patents

Abstract

PURPOSE:To eliminate the need of a ROM of a sub-CPU side and to reduce a cost by placing the program of the sub-CPU side in the ROM of a main CPU side and operating the sub-CPU by a start from the main CPU. CONSTITUTION:A main CPU 1 transfers the contents of a program of a sub-CPU side 5 to a 2-port RAM 8 from the ROM 2 of the CPU 1 side. When the transfer is all ended, the CPU 5 is started. When the sub-CPU 5 is started, a strobe signal is outputted to the T terminal of a D latch 19 by executing an access to an address conforming to the decoding condition of an address recorder 18, and by setting a Q terminal to 'H', the reset of the sub-CPU 5 is released. In such a way, the sub-CPU 5 can start its operation. The sub-CPU 5 whose reset is released starts a fetch from '0' address. While the sub-CPU 5 is executing a transfer, the main CPU 1 is in a stand-by state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory transfer method in a multiprocessor system constituting an electronic computer.

[Prior Art] FIG. 6 is a block diagram showing a schematic configuration of a multiprocessor system constituting a conventional electronic computer. In the figure, 28 is the main CPU (main central processing unit);
9 is R2 on the main CPU 2B side is the sub CPU, 33 is the ROM on the sub CPU 32 side, and 34 is R on the sub CPU 32 side.
AM, 35 is each 110 port, 36 on the sub CPU 32 side
is a 2-port RAM.

FIG. 7 is an explanatory diagram showing software of the multiprocessor system of FIG. 6. In the figure, 37 is the main C
ROM area on the PU28 side (8 bytes), 38 is the RAM area on the main CPU2B side (8 bytes), 39
is the I10 port area on the main CPU 2B side, 40 is the ROM x 7 (8 bytes) on the sub CPU 32 side, 41 is the RAM area on the sub CPU 32 side (8 bytes), 42
is an I10 port area on the sub CPU 32 side, and 43 is a 2-port RAM area (4 bytes).

Next, the operation of the conventional multiprocessor system shown in FIG. 6 will be explained. Main CPU28 and sub C
After turning on the power, the PU 32 starts fetching from address 0, completes predetermined initialization, and executes the program. At that time, programs etc. are stored in the ROM29 on the main CPU2B side.
．． It is placed in the ROM 33 on the sub CPU 32 side.

The relevant programs are installed on the main CPU2B and sub-C, respectively.
The system operates when the PU 32 executes the command.

[Problems to be Solved by the Invention] In the conventional multiprocessor system as described above, the ROM 29 and ROM 33 are connected to the main CPU 2B and the sub CPU 32, respectively. ROM33 could not be read. Therefore, there was a problem in that efficiency was low in developing, unpacking, and maintaining programs for the 32 sub-CPUs.

This invention was made to solve this problem, and the program on the sub CPU side is transferred to the RO on the main CPU side.
By placing it in M, a ROM on the sub-CPU side becomes unnecessary, reducing costs, and making it easier to develop, depack, and maintain programs on the sub-CPU side, thereby obtaining a highly flexible memory transfer method in a multiprocessor system. With the goal.

[Means for Solving the Problems] The memory transfer method according to the present invention transfers programs on the sub CPU side to the main CPU in a multiprocessor system.
The program is stored in the ROM on the PU side, the sub CPU is operated by a start signal from the main CPU side, and the program on the sub CPU side stored in the ROM is transferred to the RAM on the sub CPU side via the 2-bit RAM. It was designed to be transferred.

[Function] In the memory transfer method of the present invention, a sub-CPU side program stored in a ROM on the main CPU side is transferred to a two-bit RAM, and the sub-CPU is operated by a start signal from the main CPU side. Since the contents of the two-port RAM that have been transferred are transferred to the RAM on the sub-CPU side, development, depacking, and maintainability of programs on the sub-CPU side can be improved.

[Embodiment] FIG. 1 is a block diagram showing a schematic configuration of a multiprocessor system constituting an electronic computer to which a memory transfer method is applied, which is an embodiment of the present invention. In the figure, 1 is the main CPU, 2 is the ROM on the main CPU side, 3 is the RAM on the main CPU 1 side, and 4 is the I side on the main CPU l side.
10 ports, 5 is sub CPU, 6 is R on sub CPU 5 side
AM, 7 is an I10 port on the sub CPU 5 side, 8 is a 2-bot RAM, and 9 is an activation signal for starting the sub CPU 5.

FIG. 2 is an explanatory diagram showing software of the multiprocessor system of FIG. 1. In the figure, 10 is the main C
This is a ROM area on the PU i side, and corresponds to ROM2 on the main CPU I side shown in FIG. 11 is 2 port RA
The M area 12 is a RAM area on the main CPU side, and corresponds to the RAM 3 on the main CPU I side in FIG.

13 is the I10 port area on the main CPUI side,
This corresponds to I10 port 4 on the main CPU l side in FIG. 14 is a RAM area on the sub CPU 5 side, and the first
This corresponds to the RAM 6 on the sub CPU 5 side in the figure.

15 is an I10 port area on the side of the sub CPU 5, which corresponds to the I10 port 7 of the example of the sub CPU 5 in FIG.

FIG. 3 is a circuit configuration diagram for explaining the activation signal for the sub CPU in the multiprocessor system of FIG. 1. In the figure, 1 is the main CPU, 17 is the address bus of the main CPU 1, 18 is the address recorder,
19 is a D latch, and 5 is a sub CPU.

FIG. 5 is a flowchart showing the memory transfer procedure of the multiprocessor system of FIG. In the figure, 21
-27 are steps showing the transfer process.

Next, the operation of the multiprocessor system configuring the electronic computer to which the memory transfer method, which is an embodiment of the present invention shown in FIG. 1, is applied will be explained. In this system configuration, at the same time as the power is turned on, the main CPUI starts fetching from address θ and performs a predetermined initialization. on the other hand,
The sub CPU 5 has the configuration shown in Figure 3, and when the power is turned on, the R terminal of the D latch 19 is connected to the power-on reset of the main CPU, so the Q terminal outputs "L" and the sub CPU 5 is reset. It becomes a story. Therefore, the sub CPU 5 cannot perform any operation.

As shown in the flowchart of the memory transfer procedure in FIG.
The contents of the side program are transferred from the ROM2 on the main CPU1 side to the two-bottom RAM8. Next, step 22
The end of the transfer is determined at step 21, and if the transfer is not completely completed, the process returns to step 21 and continues the transfer. When all transfers are completed, the sub CPU 5 is activated in step 23. The sub CPU 5 is activated by accessing the address that meets the decoding conditions for one day in the address recorder shown in FIG. 3, outputting a slope signal to the T terminal of the D latch 19, and setting the Qi pin to "H". Release the reset of the sub CPU 5. This allows the sub CPU 5 to start operating. Sub CPU5 whose reset has been canceled
starts fetching from address 0. If the sub CPU 5 starts the transfer in step 26, the main CPU 5 waits in step 27 until the sub CPU 5 completes the transfer. 2000 from address θ as shown in Figure 2.
Since the address is assigned to the two-vote RAM area 11, the sub CPU 5 executes the data transferred from the main CPU.

Again, as shown in the flowchart of the transfer procedure in Figure 5,
In step 24, the sub CPU 5 transfers the contents of the 2-bot RAM 8 to the RAM 6 on the sub CPU 5 side. Step 25
The end of the transfer is determined at , and when all transfers are completed, the main CPU 1 is notified of the completion of the transfer.

In the above embodiment, the case where the latch 19 as shown in FIG. 3 is used as the circuit configuration for explaining the activation signal to the sub CPU 5 has been explained, but the case where the latch 19 as shown in FIG. 4 is used is used. A circuit configuration using the tap 20 may also be used.

[Effects of the Invention] As explained above, the present invention provides a multiprocessor system in which a program on the sub CPU side is transferred to the main CPU.
It is stored in the ROM on the U side, the sub CPU is operated by a start signal from the main CPU side, and the program on the sub CPU side stored in the ROM is transferred to the RAM on the sub CPU side via the 2-port RAM. This configuration eliminates the need for a ROM on the sub-CPU side, which reduces costs, and allows development of programs on the sub-CPU side.

This has the excellent effect of providing a highly flexible multiprocessor system that is easy to pack and maintain.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a multiprocessor system constituting an electronic computer to which a memory transfer method is applied, which is an embodiment of the present invention, and FIG. 2 is an explanation showing the software of the multiprocessor system shown in FIG. Figure, 3rd
4 and 4 are respectively circuit configuration diagrams for explaining the activation signal for the sub CPU in the multiprocessor system of FIG. 1, FIG. 5 is a flowchart showing the memory transfer procedure of the multiprocessor system of FIG. 1, and FIG. The figure is a block diagram showing a schematic configuration of a multiprocessor system constituting a conventional electronic computer, and FIG. 7 is an explanatory diagram showing software of the multiprocessor system of FIG. 6. In the figure, 1,28...main CPU, 2.29...
・ROM, 3, 6, 30, 34...RAM, 4,7゜3], 35...I10 port, 5, 32...Sub C
PU, 8, 3B...2-bot RAM, 9...Start signal, 10, 37. 40...ROM area, 11
, 43...2-bottom RAM area, 12. 14.
38. 41...RAM area 5.13. 15.
39. 42...■10 port area, 17...
Address bus, 18...Address recorder, 19...
・D latch, 20...Flip-flop to J-, 21
~27...step. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a multiprocessor system that constitutes a computer, there are two ports R that can be accessed by both processors.
AM, a means for transferring the contents of the ROM on the main CPU side to the two-port RAM, and a means for operating the sub-CPU side by a start signal from the main CPU side, and transferring the transferred contents of the two-port RAM to the two-port RAM. A memory transfer method characterized by having means for transferring data to RAM on the CPU side.