JPH01130232A - Microcomputer - Google Patents

Abstract

PURPOSE:To facilitate the detection of a failure by inputting a processing request signal and a set value of a storage means so as to be switchable to an asynchronous operating means, so that its internal state can be outputted to the outside in a real time. CONSTITUTION:To a data bus 200 between an execution unit 120 and a bus control unit 130, a test use register 180 is connected, its test use signal line 181 and 182,and an LDRQ signal 140 and an STRQ signal 141 of the unit 120 are inputted to a selector 131 and 132, and a test use signal line 183 and a QFUL signal 142 of an instruction queue 110 are inputted to a selector 133. In such a state, at the time of a test mode, the signal lines 181-183 are inputted to the unit 130, the unit 130 is operated irrespective of a state of the queue 110 and the unit 120, and its internal state is outputted to the outside in a real time from an output signal 139.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer that includes a test circuit therein.

[Conventional example]

Generally, a microcomputer has a built-in test circuit so that defects occurring during the manufacturing process 1 (assembly process) can be easily detected. Conventionally, when testing a microcomputer, the microcomputer executes instructions and at the same time outputs internal information such as data flowing on the internal data bus from a terminal via a test circuit. A method is used to compare this output value with an expected value.

On the other hand, as demands for the performance of microcomputers become higher, the number of advanced microcomputers that divide the inside of the microcomputer into a plurality of units and use pipeline control has increased in recent years.

The operation of this type of microcomputer will be explained with reference to the block diagram of FIG.

The microcomputer 300 shown in FIG. 3 includes an instruction queue 110 that stores instruction codes read ahead from an external memory, an execution unit 120 that performs data arithmetic and transfer processing based on the instruction codes, and an external memory. and a bus control unit 130 that controls the transfer of data and instruction codes between the microcomputer 300 and the execution unit 120. The bus control units 130 are interconnected by a data bus 200 (hereinafter referred to as D bus) for transferring data associated with memory access.

In addition, the microcomputer 300 has input terminals such as
The microcomputer 300 has an operation mode designation terminal 301 that specifies whether the microcomputer 300 operates in a test mode in which the internal test circuit operates or in a normal mode in which normal instructions are executed. It has an internal status output terminal for outputting data on the 120 internal data buses to the outside. When 0 is input to the operation mode designation terminal 301, the microcomputer 30
0 operates in normal mode, and when 1 is input, it operates in test mode.

The execution unit) 120 uses the bus control unit 1 when reading/writing data from/to external memory in conjunction with instruction execution.
Read/write request signals 140 and 141 (hereinafter referred to as the LDRQ signal and 5TRQ signal, respectively) requesting activation of a bus cycle at 30 are made active, and made inactive when the bus control unit 130 activates the requested bus cycle. Furthermore, the execution unit 120 outputs an instruction code request signal 143 (hereinafter referred to as a QRD signal) to the instruction queue 110 requesting transfer of an instruction code. When the QRD signal 143 becomes active, the instruction queue 110 sends the instruction code to the queue output bus 210 (hereinafter referred to as Q
O Babasu is written. ) to the execution unit ) 120. The instruction queue 110 also outputs a queue full signal 142 (hereinafter referred to as a QFUL signal) to the bus control unit 130 indicating that the instruction codes in the instruction queue 110 are full, and the bus control unit 130
When the L signal 142 is inactive, the instruction code is read ahead and transferred to the instruction queue 110 via the instruction bus 220 (hereinafter referred to as Ebus).

Furthermore, the bus control unit 130 controls the LDRQ signal 140
, 5TRQ signal 141. An arbitration circuit 135 that determines the processing to be performed by the bus control unit 130 based on the state of the QF'UL signal 142. It has a timing generation circuit 136 that generates a bus cycle signal according to the selection by the arbitration circuit 135.

When the LDRQ signal 140 and 5TRQ signal 141 are active or the QFUL signal 142 is inactive, the arbitration circuit 135 reads data from the external memory, writes data to the external memory, and reads instruction codes from the external memory. , MRD processing and MWR, respectively.
The processing is referred to as FET processing. ) Select which one of the three types of processing to perform. 5T if there are multiple requests
RQ signal 141. LDRQ signal 140. QFUL signal 1
42, and select which process to perform. In addition, LDRQ signal 140.5 TRQ signal 141
is inactive and QFUL signal 142 is active, bus control unit 130 does not initiate a bus cycle and remains idle.

Next, the timing chart of FIG. 4 shows the operation of the microcomputer 300 when executing an instruction.

The timing chart in FIG. 4 shows the operation when the microcomputer 300 executes instructions 1 to 6. Note that instructions 1 and 5 are instructions for writing to memory, instructions 2 and 6 are instructions for reading from memory, and instructions 3 and 6 are instructions for reading from memory.
4 is an instruction that can be processed only within the execution unit 120.

The arbitration circuit 135 inside the bus control unit 130 operates at timings tl, t2. t6. t7゜t8. In tll,
LDRQ signal 140. STRQ signal 141. Since the QFUL signal 142 is inactive, 0, the arbitration circuit 135 selects the QFUL signal 142, and the timing generation circuit 136 activates a bus cycle for FET processing and pre-reads the instruction code.

At timing t3, 5TRQ signals 141. Since the QFUL signal 142 is active and the LDRQ signal 140 is inactive, the arbitration circuit 135
41, the timing generation circuit 136 starts a bus cycle for MWR processing.

At timing t4, LDRQ signal 140. Since the QFUL signal 142 is active and the 5TRQ signal 141 is inactive, the arbitration circuit 135
40, the timing generation circuit 136 starts a bus cycle for MRD processing.

At timing t9, the LDRQ signal 140, 5TRQ signal 141 is active, and the QFUL signal 142 is inactive, so the arbitration circuit 135 selects the signal with the highest priority among the LDRQ signal 140, 5TRQ signal 141, and QFUL signal 142. 5TRQ signal 141 is selected,
The timing generation circuit 136 starts a bus cycle for MWR processing.

At timing tlo, LDRQ signal 140 is active and 5TRQ signals 141 . Since QFUL signal 142 is inactive, arbitration circuit 135 selects LDRQ signal 140 . Among the QFUL signals 142, the LDRQ signal 140
Since the method has a higher priority, the LDRQ signal 140 is selected, and the timing generation circuit 136 starts a bus cycle for MRD processing.

Also, during the period from timing t5 to t6, LDRQ signal 1
40,5 TRQ signal 141 is inactive, QFU
Since the L signal 142 is active and there is no request to start a bus cycle, no bus cycle is started.

In this way, the bus control unit, ) 130 samples the input request signal at the end of the bus cycle or when the bus is idle, and selects the request with the highest priority, regardless of the instruction timing. and perform the corresponding processing.

Next, a case in which a test is performed using the microcomputer 300 described above will be described.

First, the operating mode designating terminal 301 is input to 1 to put the microcomputer 300 into test mode. While causing the microcomputer 300 to execute instructions in this state, the data on the bus inside the execution unit 120 that is output to the internal status output terminal is observed externally and compared with the expected value, thereby controlling the operation of the microcomputer 300. Perform a check.

However, instruction queue 110. Since the bus control unit 130 operates asynchronously with instruction execution, during instruction execution, the LDRQ signal 140.5TRQ signal 141 . Q
The state of FUL signal 142 cannot be directly controlled. For this reason, it is extremely difficult to cover all combinations of conditions necessary for testing the bus control unit 130 in the conventional instruction execution test described above.

[Problems to be solved by invention C] As mentioned above, when testing a microcomputer in which each internal unit operates asynchronously, each unit operates asynchronously with respect to instruction execution. It is not possible to directly control the operation of each unit. For this reason, the conventional testing method of having a microcomputer execute an instruction, outputting the internal state flowing on the internal data bus at that time to an external terminal, and observing it externally, does not cover all the conditions that need to be checked. It is very difficult to generate this by executing an instruction, and as a result, it has the disadvantage that there is a possibility that a defect may be overlooked.

[Differences between the invention and the prior art]

In contrast to the conventional microcomputer test circuit method 2 described above, in the present invention, various signals input to the unit under test, which operate asynchronously with instruction execution, are input from test registers that can be set by instruction execution in the microcomputer test mode. The microcomputer has the function of switching to the supplied signal and the function of outputting the internal state of the unit to an external terminal. As a result, the signal values input to the unit under test can be directly controlled, making it extremely easy to set the conditions that need to be checked. This makes it easy to detect defects that occur inside the unit.

[Means for solving problems]

In the microcomputer according to the present invention, the asynchronous operating means that operate asynchronously with each other mutually output processing request signals accompanying instruction execution, and the plurality of asynchronous operating means process a predetermined instruction according to the state of the processing request signal, Furthermore, this microcomputer has storage means that can be set by executing instructions, selection means that selects a processing request signal to be input to the asynchronous operation means, and status output means that outputs the internal state of the asynchronous operation means to an external terminal. The selection means switches the processing request signal input to the asynchronous operation means with an output signal for outputting the set value of the storage means, and the state output means outputs the internal state of the asynchronous operation means to an external terminal in real time. It is characterized by things.

[Example 1] Next, a first example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of a microcomputer including a test circuit according to the present invention.

A microcomputer 100 shown in FIG. 1 includes a test register 180 that can be set via a D bus 200 by executing instructions in a conventional microcomputer 300.
Test signal lines 181 and 1 that output the input signal to the bus control unit 130 and the set value of the test register 180
82, 183 etc. LDRQ signal 140, 5 TRQ signal 14
1. Selector 13 to select between QFUL signal 142
1.132, 133, arbitration circuit 13 in test mode
5. An internal state output signal 139 is added that outputs the internal state of the timing generation circuit 136 to an external terminal.

Further, when executing normal instructions, the microcomputer 300 performs the same operation as the conventional microcomputer 300.

In addition, the selectors 131, 132, and 133 select the LDRQ signal 140, 5TRQ signal 141°QFUL signal 142, respectively, in the normal mode in which normal instructions are executed, and select the test signal lines 181, 1, and 142 in the test mode.
82 and 183 are selected and supplied to the bus control unit) 130.

Next, a test method for the microcomputer 100 of this embodiment will be described.

First, in the normal mode, by executing an instruction, the test register 180 is set with data that will become the input signal value to the bus control unit 130 when the test mode is entered.

Next, 1 is input to the operation mode designation terminal 101 to shift to the test mode. In this state, selector 131,1
32, 133 select test signals 181, 182, 183 as input signals to the bus control unit 130, the bus control unit 130 is separated from the instruction queue 110 and execution unit 120, and The operation is performed according to the set value of the test register 180 regardless of the state.

As a result, the value of the input signal to the bus control unit 130 can be easily set to an arbitrary value, and at this time, the value of the input signal to the bus control unit 135. By comparing the internal state output signal 139, which outputs the internal state of the timing generation circuit 136, with an expected value externally, the bus control unit 130 can be easily tested.

[Embodiment 2] Next, a second embodiment based on the present invention will be described with reference to the block diagram of FIG. 2.

In the microcomputer shown in FIG. 2, the test register in the first embodiment is an NX3-bit shift register 28.
0-1,280-2,280-3,...,28
0-(N-1), 280-N, and a test signal 281 that outputs the set value of the shift register 280-1.
, 282, 283 are input to the selectors 131, 132, 133, and the test shift register 280-
1°280-2. The structure is the same as that of the first embodiment except that a shift timing designation signal 290 is input from an external terminal as a signal designating the shift timing of . . . , 280-N. In addition, N-stage shift register 2
80-1, 280-2, 280-3, ..., 2
80-(N-1) and 280-N can be written by executing a command, and the shift timing designation signal 29
When 0 becomes active, the contents of shift register 280-2 are transferred to shift register 280-1, the contents of 280-3 are transferred to shift register 280-2, ..., the contents of 280-N are transferred to 2.
80-(N-1), a shift operation is performed.

In the microcomputer of this embodiment, in the test mode, the input signals to the bus control unit 130 are the test signals 281, 282, which are the set values of the test shift register 280-1, by the selectors 131, 132, 133.
, 283 are selected, the bus control unit 130 operates according to the output value of the test shift register 280-1, regardless of the states of the instruction queue 110 and execution unit 120.

Therefore, by executing the instruction in advance, the test shift registers 280-1, 280-2, 280-3, . . .
Bus control unit 1 on 280-(N-1) and 280-H
Set the input signal value for checking for 30,
After that, the mode shifts to the test mode, and by activating the shift timing designation signal 290 from the outside at an appropriate timing, the values of the test signals 281, 282, 283 are transferred to the shift registers 280-1, 280-2, 280-.
3,..., 280-(N-1), 280-H can be changed in order to the initial settings, and while dynamically changing the input to the bus control unit, arbitrary settings can be made. You can give input.

At this time, the arbitration circuit 135 in the bus control unit 130
．． By observing the internal state of the timing generation circuit 136 being output to the external terminal via the internal state output signal 139, it is possible to test the bus control unit 130 very easily and with a large degree of freedom. becomes.

〔Effect of the invention〕

As explained above, in the present invention, in order to test a unit that operates asynchronously with instruction execution, a microcomputer is provided with a test register that can be set by instruction execution, and a unit to be tested in test mode. It has a function of switching the input signal value to the set value of the test register, and a function of outputting the internal state of the unit under test to an external terminal during testing, which provides the following effects.

(1) Data set in the test register in advance by executing an instruction becomes the input signal value to the unit under test in test mode, so it is difficult to control the input signal value to the unit under test, which is difficult with normal instruction execution. This is easy to perform, and since the internal state of the unit under test can be observed in real time during the test mode, abnormalities inside the unit under test can be easily detected. As a result,
Units that operate asynchronously with instructions can be easily tested.

(2) Since test registers can be set by executing instructions, there is no need for external terminals to set data in test registers, and compared to conventional tests by executing instructions, there is no need to increase the number of test terminals. Testing can be facilitated.

In this way, in the present invention, a test register is provided in the microcomputer, and the input signal to the target unit is supplied from this test register in the test mode, and at the same time, the internal state of the test target unit can be directly observed externally. By adding , it is possible to easily test the microcomputer, and as a result, it is possible to improve the defect detection rate due to the test, which is of high practical importance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer according to the first embodiment based on the present invention, FIG. 2 is a block diagram of a microcomputer according to the second embodiment, FIG. 3 is a block diagram of a conventional microcomputer, and FIG. 3 is a timing chart of the operation of a conventional microcomputer. 100.300...Microphone computer, 1
01.301...Operating mode input terminal, 110
...Instruction queue, 120...Execution unit, 130...Bus control unit, 131,
132゜133...Selector, 135...
... Arbitration circuit, 136 ... Timing generation circuit, 139 ... Internal state output signal, 140 ...
...LDRQ signal, 141...5TRQ signal, 142...QFUL signal, 143...
・QRD signal, 180...Test register,
181, 182, 183...Test signal, 2
00...D bus, 210...QD bus 220...Ebus, 280-1. 280-
2°280-3. ......, 280-(N-1)
280-N...Test shift register, 28
1,282゜283...Test signal, 290
...Shift timing designation signal. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Scope of Claims] A plurality of asynchronous operation means that operate asynchronously with each other mutually output processing request signals associated with instruction execution, and the plurality of asynchronous operation means process a predetermined instruction according to the state of the processing request signal. In the microcomputer, the microcomputer includes a storage means that can be set by executing instructions, a selection means that selects the processing request signal to be input to the asynchronous operation means, and an internal state of the asynchronous operation means that is transmitted to an external terminal. the selection means switches the processing request signal input to the asynchronous operation means with an output signal for outputting a setting value of the storage means, and the state output means switches the processing request signal input to the asynchronous operation means to output a setting value of the storage means; A microcomputer characterized in that the internal state of the means is output to the external terminal in real time.