JPH01128604A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve a PSRR (Power Supply Rejection Ratio) characteristic as an operational amplifier circuit by providing a capacitor for coupling, which has prescribed electrostatic capacity, in an interval with the power source voltage or grounding potential of a circuit. CONSTITUTION:A capacitor C1 for coupling is provided between the gate of an MOSFET Q2 and the power source voltage of the circuit. Noise to be overlapped to a power source voltage Vcc of the circuit by some causes is alternately transmitted through the capacitor C1 to the gate of the driving MOSFET Q2. Namely, for the noise to be overlapped to the power source voltage Vcc of the circuit, the gate potential of the driving MOSFET Q2 is almost in-phase- changed in a high frequency area. Accordingly, although the noise is overlapped to the power source voltage Vcc of the circuit, the voltage between source and gate of the driving MOSFET Q2 goes to be a constant value. Thus, the value of an operating current, which is supplied to differential MOSFETs Q3 and Q4, is stabilized and the PSRR characteristic of an operational amplifier circuit OA1 is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is a technology that is effective when applied to an operational amplifier circuit included in a codec (CODEC: kneader/decoder), etc. It is related to.

[Conventional technology]

There are codecs provided for subscriber lines of digital telephone switching systems. These codecs incorporate an A/D conversion circuit combined with several operational amplifier circuits.

Codecs incorporating A/D conversion circuits are described, for example, in "Integrated Circuit Application Handbook" published by Asakura Shoten, June 30, 1981, pages 593 to 600.

[Problems to be Solved by the Invention] The A/D conversion circuit built in the codec as described above is, for example, an operational amplifier circuit OA2 as shown in FIG.
including.

In FIG. 2, the operational amplifier circuit OA2 has a basic configuration of a pair of P-channel MO3FETs Q3 and Q4 which are in a differential configuration. A driving MO3FET Q2 is provided between the commonly coupled sources of the differential MOSFETs Q3 and Q4 and the circuit power supply voltage Vcc. Drive MOSFET Q2
is a MO3FET with its gate commonly coupled to the drain and gate of the P-channel MO3FET QI.
Q1 and current mirror form. An N-channel MO3FET Q6 whose gate receives a bias voltage Vb1 is provided between the commonly coupled drain and gate of the MO3FET QI and the ground potential of the circuit. Drive MOSF
The operating current supplied to the differential MO3FETQ3 and Q4 via the ETQ2 is determined by the voltage at the gate of the MO3FETQ2, that is, at the node n2. The voltage at node n2 is determined by the drain current flowing through MO3FETQI and Q6, in other words, by the bias voltage Vbl supplied to the gate of MOSFETQ6. As a result, a predetermined operating current according to the bias voltage vbt is supplied to the differential MO3FETs Q3 and Q4.

However, the inventors of the present application have discovered that the above-mentioned operational amplifier circuit has the following problems. That is, in the operational amplifier circuit OA2 of FIG. 2, if noise is superimposed on the power supply voltage Vcc of the circuit for some reason,
The gate-source voltage of the drive MO3FET Q2 is directly changed.

For this reason, the operating current supplied to the differential MO3FETs Q3 and Q4 fluctuates unexpectedly, causing the PSR as an operational amplifier circuit to
R(Poe<er 5uply Rejection
nRatto) characteristics deteriorate.

An object of the present invention is to provide an operational amplifier circuit with improved PSRR characteristics.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the gate of the drive MO3FET provided between the commonly coupled sources of the differential MO3FETs constituting the operational amplifier circuit and the power supply voltage or ground potential of the circuit and its source, that is, the power supply voltage or ground potential of the circuit. A capacitor having a predetermined capacitance is provided between them.

[For production]

According to the above means, the noise superimposed on the power supply voltage is transmitted to the gate of the driving MO8FET via the capacitor in an alternating current manner, so that fluctuations in the gate-source voltage of the driving MO3FET are suppressed and the differential The PSRR of the operational amplifier circuit is improved by stabilizing the value of the operating current supplied to the MO3FET.
Characteristics can be improved.

〔Example〕

FIG. 1 shows an operational amplifier circuit OAI to which this invention is applied.
A circuit diagram of one embodiment is shown.

The operational amplifier circuit OAI of this embodiment is included in an A/D conversion circuit of a codec provided corresponding to a subscriber circuit of a digital telephone exchange system, although it is not particularly limited thereto.

Each circuit element in the figure, along with circuit elements constituting other blocks of the codec, is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques. Ru. In the figure, the MOSFET whose channel (back gate) part is marked with an arrow is a P-channel MO3FET, which is distinguished from the N-channel MO8FE'r, which is not marked with an arrow.

In FIG. 1, the operational amplifier circuit OAI is a P-channel type differential MO3FETQ3 (first MOSFET).
- The basic configuration is Q4 (f52 MOSFET).

The gates of the differential MO3FETs Q3 and Q4 are connected to the inverting input terminal in- and the non-inverting input terminal i of this operational amplifier circuit OAI.
n0, respectively.

Between the drains of the differential MO3FETs Q3 and Q4 and the circuit ground potential (second
O3FETQ7 (first load means) and Q8 (second
load means) are provided respectively.

The drain and gate of MO3FETQ7 are commonly coupled and further coupled to the gate of MOSFETQB. This allows MO3FETQ? and Q8 act as an active load element for the differential MO3FETs Q3 and Q4.

difference! ! A drive MO3FET Q2 (third MOSFET) is provided between the commonly coupled sources of the JMO8FETs Q3 and Q4 and the circuit power supply voltage Vcc (first power supply voltage). Drive? The gate of JOSFETQ2 is the P channel 03FETQI (4th
are commonly coupled to the train and gate of the MOSFET. The source of MO3FETQI is connected to the circuit power supply voltage V
Connected to cc. This allows MOS FETQ
1 and drive MO3FETQ2 are in a current mirror configuration.

A compensating capacitor C1 having a predetermined capacitance is provided between the gate of the driving MO8FET Q2 and its source, that is, the power supply voltage VCC of the circuit.

Between the commonly coupled drain and gate of MO3FETQI and the circuit ground potential, an N-channel MO3FE
TQ6 (517th) MOSFET) is provided. M
A predetermined bias voltage Vbl (second bias voltage) is supplied to the gate of the O3FET Q6 from a constant voltage generation circuit (not shown) of the codec.

The value of the drain current of MO3FETQ6 is determined according to the bias voltage Vbl.
The drain current is passed through MO3FETQI as it is, and determines the source-to-gate voltage of MO3FETQI, that is, the source-to-gate voltage of drive MO3FETQ2, in other words, the bias voltage (first bias voltage) at node n1. The drain current of MO3FETQ2 is
Its value is determined according to the source-gate voltage of MO3FETQ2. As a result, the differential MO3FETQ3・Q
4 is supplied with a predetermined operating current according to the bias voltage vbt.

The drain voltage of MO3FETQ4 is N-channel MO
It is supplied to the gate of 3FETQIO (seventh MOSFET). The source of MO3FETQI O is coupled to the ground potential of the circuit, and its drain is connected to this operational amplifier circuit OAI.
is coupled to the output terminal out of. MO3FET QI G
, that is, the output terminal out and the circuit power supply voltage V
A P-channel MO3FETQ5 (sixth MOSFET) is provided between the MOSFET and cc. The gate of MO3FETQ5 is commonly coupled to the gates of MO3FETQI and Q2. As a result, MO3FETQ5 functions as a load element, and MO3FETQIO
An output amplifier circuit with ETQ5 as a load is constructed.

MO3FETQI O drain or output terminal ou
A capacitor C2 and an N-channel MO3FET Q9 are provided in series between t and its gate. MO3
FETQ9 has a predetermined bias voltage Vb2 on its gate.
is supplied, it functions as a load element with a predetermined conductance. Therefore, the output level of the output terminal out, that is, the drain voltage of MO3FETQIO is
MO through the capacitor C2 and MO3FETQ9
Negative feedback is provided to the gate of 3FET0.10. This makes it possible to prevent the operational amplifier circuit OAI from unintentionally oscillating.

The operational amplifier circuit OAI, which has differential MO3FETs Q3 and Q4 as its basic configuration, performs a differential amplification operation on a pair of input signals supplied to the non-inverting input terminal in+ and the inverting input terminal in-, that is, the inverting input terminal in - If the input pressure of - is higher than the input voltage of non-inverting input terminal in+, MO
The conductance of 3FETQ3 is reduced, and conversely the MO
The conductance of 3FETQ4 is increased. Thereby, the drain voltage of MOS FETQ4 is increased according to the amplification factor of differential MO3FETQ3 and Q4.

When the drain voltage of MO3FETQ4 is increased, the MO3FETQ4
The conductance of the 3FET QIO increases, and its drain voltage, that is, the output level of the output terminal out, is lowered. On the other hand, when the input voltage of the inverting input terminal in- becomes lower than the input voltage of the non-inverting input terminal in+, MO5F
The conductance of ETQ3 is increased and the MO
The conductance of 3FETQ4 is made small (as a result, the drain voltage of MOSFE 'I' is lowered according to the amplification factor of differential MOSFETQ3 and Q4). The conductance of Q10 becomes smaller, and its drain voltage, ie, the output level of the output terminal out, becomes higher.

By the way, 1. The output output from the output terminal OUT of the tA# amplifier circuit OAI (the level of No. 8 is 51#JMO3F
Operating current of ETQ3 and Q4, that is, drive MO3FETQ
It depends on the drain current of 2.

Therefore, in the operational amplifier circuit OAI of this embodiment, as described above, the gate of MO3FETQ2 and the tJ1a of the circuit are
A coupling capacitor C1 is provided between the m pressure and the PSRR characteristic.

In other words, for some reason the circuit power supply voltage Vcc
The noise superimposed on the drive M
It is transmitted in alternating current to the gate of O3FETQ2. In other words, the noise superimposed on the power supply voltage Vcc of the circuit causes the gate potential of the driving MOS FET Q 2 to change in almost the same phase in the high frequency region. Therefore, even though noise is superimposed on the power supply voltage Vcc of the circuit, the drive M
The voltage between the source and gate of O5FETQ2 becomes a constant value. As a result, the value of the operating current supplied to the differential MOSFETs Q3 and Q4 is stabilized, and the operational amplifier circuit OAI
This improves the PSRR characteristics of .

As described above, the operational amplifier circuit OA1 of this embodiment has a basic configuration of a pair of differential MO3FETs Q3 and Q4. Between the commonly coupled sources of these differential 10SFETs CA3 and Q4 and the power supply voltage Vcc of the IiM path,
! A dynamic MOS FETQ 2 is provided.

rJA dynamic MOSFETQ 2 is MO3FET
QI and current mirror configuration. A MO3FETQ6 whose gate receives a predetermined bias voltage Vbl is provided between the MO3FETQI and the ground potential of the circuit. As a result, a predetermined constant voltage according to the bias voltage Vbl is supplied to the gate of the drive MO3FET Q2, and a predetermined operating current according to this constant voltage is supplied to the differential @MO8FETQ3 and Q4. In the operational amplifier circuit OAI of this embodiment, a coupling capacitor C1 having a predetermined capacitance is further provided between the gate of the drive MO3FET Q2 and the circuit power supply voltage VCC. This capacitor C1 transmits the noise superimposed on the '#1 source voltage Vcc of the circuit to the gate of the driving MO3FET Q2 in an alternating current manner. Therefore, even though noise is added to the power supply voltage Vcc of the circuit, the source-gate voltage of the driving MO3FETQ2 is stabilized, and the differential MO3FETQ3 and Q4
The value of the operating current supplied to is constant. This improves the PSRR characteristics of the operational amplifier circuit OAI.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to an operational amplifier circuit included in a codec or the like of a digital telephone exchange device. That is, <1) The gate and source of the drive MOSFET provided between the commonly coupled sources of the differential MO3FETs constituting the operational amplifier circuit and the circuit power supply voltage or ground potential, that is, the circuit power supply voltage. or between ground potential,
By providing a compensating capacitor with a predetermined capacitance, the noise superimposed on the circuit's power supply voltage or ground potential can be transmitted to the gate of the driving MO5FET in alternating current and in phase, thereby eliminating the noise accompanying the noise. Drive MOS F
This provides the effect of suppressing fluctuations in the gate-source voltage of the ET.

(2) According to the above (1), the differential MO8 of the operational amplifier circuit
An effect can be obtained in that the value of the operating current supplied to the FET can be prevented from being fluctuated by noise superimposed on the power supply voltage.

(3) According to the above (11) and (2), it is possible to improve the PSRR characteristics of an operational amplifier circuit such as a codec in which a digital circuit is embedded without changing its amplification characteristics.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. 0 For example, in the circuit diagram of FIG. 1, the differential MOSFETs Q3 and Q4 and other MOSFETs are connected to the 'i!' of the circuit. By replacing the i source voltage Vcc and the ground potential, it is possible to replace the P-channel MO5FET and the N-channel MO3FETt. Moreover, in this embodiment, MOS FET
A predetermined constant voltage is applied to the gate of the drive MO3FET Q2 by using Ql and the drive MO3FET Q2 in a current mirror configuration, but without providing a current mirror circuit! ! lJIMO
A predetermined bias voltage can also be applied directly to the gate of 3FETQ2. The capacitor C1 may be realized by connecting a plurality of capacitors in parallel. Furthermore, the output amplification circuit can take any configuration, and the specific circuit configuration of the operational amplifier circuit OAI can take various embodiments.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to an operational amplifier circuit included in a codec of a digital telephone exchange device, which is the background of the invention, but it is not limited to this, and for example, The present invention can also be applied to operational amplifier circuits used in digital communication devices and various A/D-D/A conversion circuits. A drive M provided between
The present invention can be widely used in operational amplifier circuits including OS FETs and semiconductor devices incorporating such operational amplifier circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the differential MOS F constituting the operational amplifier circuit
A driving MOS F provided between the commonly coupled sources of the ET and the circuit power supply voltage or ground potential. By providing a capacitor for compensating, the noise superimposed on the power supply voltage or ground potential of the circuit can be simultaneously transmitted to the gate of the drive MO3FET in an alternating current manner.
It is possible to suppress fluctuations in the gate-source voltage of the O3FET and improve the PSSR characteristics of the operational amplifier circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an operational amplifier circuit to which this invention is applied, and FIG. 2 is a circuit diagram of an operational amplifier circuit developed by the inventors of the present invention prior to this invention. OAI, OA2... operational amplifier circuit, Q1 to Q5...
P-channel MO9FET, Q6 to Q10---N-channel MO3FET, C1, C2... Capacitor.

Claims (1)

[Claims] 1. First and second MOs of a first conductivity type that are in a differential configuration
SFET, and a third MOSFET of a first conductivity type, which is provided between the commonly coupled sources of the first and second MOSFETs and the first power supply voltage, and whose gate receives the first bias voltage.
A semiconductor integrated circuit device comprising an operational amplifier circuit including a MOSFET and a capacitor provided between the gate of the third MOSFET and a first power supply voltage. 2. The first bias voltage is connected to the third MOSFET by having its source coupled to the first power supply voltage and its drain and gate commonly coupled to the gate of the third MOSFET.
a fourth MOSFET of the first conductivity type which is in a current mirror configuration with the MOSFET of the fourth MOSFET; 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed by a fifth MOSFET of the second conductivity type that receives a bias voltage of . 3. The operational amplifier circuit further includes the first and second M
first and second load means respectively provided between the drain of the OSFET and the second power supply voltage; and a gate of the third MOSFET provided between the output terminal and the first power supply voltage. a sixth MOSFET of the first conductivity type that is commonly coupled to the first conductivity type, and a sixth MOSFET that is provided between the output terminal and the second power supply voltage and has a gate that is
a seventh MO of the second conductivity type coupled to the drain of the FET;
A semiconductor integrated circuit device according to claim 1 or 2, characterized in that the semiconductor integrated circuit device includes an SFET. 4. The semiconductor integrated circuit device according to claim 1, 2, or 3, wherein the operational amplifier circuit is included in a codec of a subscriber circuit of a digital telephone exchange.