JPH09130166A - Cmos differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the changes of both gain and phase frequency characteristics and to secure the satisfactory DG(differential gain) and DP(differential phase) characteristics by regulating the larger one of both currents amplified by a 1st or 3rd current mirror circuit by the other smaller current. SOLUTION: When a pair of input signals V (+) and V (-) are set at the same level, the voltage of the same level as these input signals is outputted to an output terminal OUT. If the potential of the signal V (+) rises under such conditions, the current I1 flowing to a MOS transistor TR MN9 increases and the current I2 flowing to a TR MN10 reduces. Therefore, the gate voltage of a MOS TR MP7 placed at the output side of a 1st current mirror circuit 23 rises to try to increase the drain current of the TR MP7. Thus the on- resistance of the TR MP7 reduces. Then the gate voltage of a MOS TR MN13 of a 3rd current mirror circuit 24 drops to try to reduce the drain current of the TR MN13. Thus the on-resistance of the TR MN13 increases. As a result, the output voltage rises.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal amplification technique, in particular a CMOS differential amplifier circuit, for example, an L for video signal processing.
The present invention relates to a technology effectively used in a video buffer circuit required for a character addition function to a video signal in SI, a multiple addition (picture in picture) function of a video signal, an A / D conversion function of a video signal, and the like.

[0002]

2. Description of the Related Art The present inventors have examined a CMOS differential amplifier circuit as shown in FIG. 4 as an amplifier circuit used for video signal processing.

The CMOS differential amplifier circuit shown in FIG. 4 has a differential input stage 11 composed of a pair of differential input MOS transistors MN1 and MN2 whose sources are commonly connected, and a load MOS connected to each drain thereof. Transistor MP
1, MP2, an active load circuit 12, a constant current source 13 made up of a MOS transistor MN3 having a constant voltage V1 applied to its gate, a MOS transistor MN4 receiving at its gate the output potential of the differential input stage 11, and a constant current. MOS
A level shift stage 14 comprising a transistor MN5,
MOS connected in series between the power supply voltage Vcc and the ground point
A push-pull type output stage 15 composed of transistors MP3 and MN6, a resistor R1 and a capacitor C connected in series between the output node n1 of the differential input stage 11 and the output terminal OUT.
1 and a phase compensation circuit Zf.

[0004]

DISCLOSURE OF INVENTION Problems to be Solved by the Invention
We have found the following problems when the MOS differential amplifier circuit is applied to video signal processing.

That is, the amplitude (peak-to-peak) of the video signal is as standard as large as 2V, and the frequency band is 10M.
As wide as Hz. In the CMOS differential amplifier circuit of FIG. 4, by using the level shift circuit 14, DC of the output Vout
The change in the voltage VM of the node n1 due to the voltage can be reduced, and as a result, even if the DC voltage of the output Vout changes, the change in the static gain and phase frequency characteristics can be reduced.

However, when it is used as a video buffer, the output terminal is connected to the input terminal V (-) to form a voltage follower and a large amplitude signal is handled, so that the input terminal V (+ ) And V (-), an input potential difference is generated, and the impedance of the node n1 negatively fed back via the negative feedback circuit Zf changes significantly. Therefore, the frequency characteristics of the gain and the phase change due to the DC voltage of the input signal, and further in the transition period of the voltage change of the input signal. It became clear that there was a problem of getting worse.

Further, not only analog circuits but also digital circuits coexist in the video signal processing LSI, and the digital circuits are connected to the positive power source (Vcc) or the negative power source (GND) on the same chip via the semiconductor substrate. May have noise. In the differential amplifier circuit shown in FIG. 4, the output stage 15 has a source-grounded MOS.
Since a transistor is used, the power supply line (Vcc
There is a problem that noise (ripple) from the digital circuit section enters through the line and the GND line).

An object of the present invention is that the change in the frequency characteristics of the gain and the phase with respect to the change in the DC voltage of the input signal is small, and the DG (differential gain) characteristics and D as a video buffer are obtained.
CMO with good P (differential phase) characteristics and strong against noise from digital circuits coming in through the power supply line
It is to provide an S differential amplifier circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, one differential input M of the differential input stage
The first current mirror circuit that amplifies the current flowing through the OS transistor at a ratio of 1: K (K> 1) and the current flowing through the other differential input MOS transistor at 1: L (L> 1,
A second current mirror circuit for amplifying at a ratio of L ≠ K),
A cascode-type third current mirror circuit for further amplifying the current amplified by the second current mirror circuit at a ratio of 1: M (M = K / L) is provided, and the first current mirror circuit is provided. The amplified current is added and combined with the output current of the third current mirror circuit, and the smaller one of the current amplified by the first current mirror circuit and the current amplified by the third current mirror circuit is the other current. Is regulated to obtain an output voltage.

According to the above configuration, since the third current mirror circuit is of the cascode type, the change of the current gain is small with respect to the change of the DC potential of the input signal, and the transition period in which the difference between the positive and negative input signals occurs. However, the change in current gain is small. As a result, when a voltage follower is configured and used as a video buffer circuit required for a character addition function to a video signal in a video signal processing LSI, a multiple addition function of a video signal, and an A / D conversion function of the video signal. , The change in the frequency characteristics of gain and phase is small, and good DG (differential gain) characteristics and DP (differential phase) characteristics can be obtained.
Moreover, since the current mirror circuit has a good ripple removal rate of the power supply voltage, it is possible to realize a CMOS differential amplifier circuit that is resistant to noise from the digital circuit that enters through the power supply line.

The phase compensation is performed by connecting a capacitor between the output terminal and the current input node of the third current mirror circuit. In this case, the impedance of the input node of the third current mirror circuit changes little,
There is little change in the negative feedback characteristic due to the phase compensation capacitance.

Further, the differential input stages are operated by independent current sources, and MO having a dimensional ratio of 1: a and a: 1, respectively.
It may be replaced with two sets of differential input stages composed of S transistors. With this configuration, the output current of the differential input stage becomes 1 / (a + 1) of the current flowing to the constant current source, and the two differential input stages have a difference between positive and negative input signals. In such a case, since alternating currents having opposite phases are output, the operation of the output circuit is a class AB amplifying operation, and the current consumption can be reduced.

Further, the differential input stage may be replaced with two sets of differential input stages each composed of a P-channel MOS transistor pair and an N-channel MOS transistor pair which operate by independent current sources. As a result, the allowable input voltage range for linear operation can be expanded.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of a CMOS differential amplifier circuit according to the present invention.

In the CMOS differential amplifier circuit of this embodiment, a differential input stage 22 composed of a pair of differential input MOS transistors MN9 and MN10 whose sources are commonly connected, and a differential input stage 22 connected in series between the common source and a ground point. MO for connected constant current
A current source 21 composed of S transistors MN7 and MN8,
Of the first and second current mirror circuits 23 connected between the drains of the differential input MOS transistors MN9 and MN10 and the power supply voltage Vcc (for example, 5 V), and the first and second current mirror circuits 23. Cascode type third current mirror circuit 24 connected to the output side
And a phase compensation circuit Zf.

In the first current mirror circuit, one load MOS transistor MP4 of the differential input stage 11 and a MOS transistor M whose gate is commonly connected to this load MOS transistor MP4.
P7 and the ratio of the W / L (gate width / gate length) value of MP4 to the W / L value of MP7 is set to 1: K (K> 1), so that the differential input MOS transistor MN
The current flowing through 9 is amplified K times. The second current mirror circuit is an MO transistor whose gate is commonly connected to the other load MOS transistor MP5 of the differential input stage 11.
Consisting of S-transistor MP6 and W / L value of 1: L
By setting (L> 1, L ≠ K), the differential input M
The current flowing through the OS transistor MN10 is amplified L times.

The third current mirror circuit 24 is an N-channel MOS transistor MN1 connected in series between the drain of the P-channel MOS transistor MP6 forming the second current mirror circuit (23) and the ground point.
1, MN12, and an N-channel MOS connected in series between the drain of the P-channel MOS transistor MP7 forming the first current mirror circuit (23) and the ground point.
MOS transistors MN11 and MN13 have their gates connected in common, MN12 and MN14 have their gates connected in common, and MN11 and MN13, MN12 and MN1.
The W / L values of 4 are formed to have a ratio of 1: M (M = K / L), respectively, so that the current amplified by the second current mirror circuit is further amplified by M times. .

In this embodiment, a P-channel MOS transistor MP7 which constitutes the first current mirror circuit described above.
The output terminal OUT is connected to a connection node n2 between the drain of the N-channel MOS transistor MN13 and the drain of the N-channel MOS transistor MN13 forming the third current mirror circuit 24.

The phase compensation circuit Zf includes the MOS transistors MP6 and MP7 forming the first and second current mirror circuits 23 and the third current mirror circuit 2.
4 is constituted by a capacitance C2 connected between connection nodes n2 and n3 with the MOS transistors MN11 and MN13 constituting the capacitance No. 4, and this capacitance C2 acts as a negative feedback element. The gate capacitance of the MOS transistor can be used as the capacitance C2. However, MOS
When the gate capacitance of a transistor is used, the capacitance value depends on the voltage. Therefore, depending on the process technology used, for example, an interlayer insulating film that does not depend on the voltage is used as a dielectric, and a polysilicon layer is used for the upper and lower electrodes. Alternatively, it is appropriate to use a capacity using a metal layer.

In the CMOS differential amplifier circuit of this embodiment, when a pair of input signals V (+) and V (-) is input, the input signal V (is input to the MOS transistors MN9 and MN10 of the differential input stage 22. Currents I1 and I2 corresponding to +) and V (-) are output. These currents I1 and I2 are respectively amplified by K times and L times by the first and second current mirror circuits 23, respectively. Further, the current I4 on the output side of the second current mirror circuit is amplified by M times by the cascode type third current mirror circuit 24. At this time, since M is set to M = K / L, the current I5 flowing through the MOS transistor MN13 is L · M · I2 = L
(K / L) I2 = Current I2 flowing in the MOS transistor MN10 of the differential input stage 22 as shown by K · I2
Will be L times.

In this embodiment, a pair of input signals V
When (+) and V (-) are at the same level, the current I3 amplified by the first current mirror circuit and flowing through the MOS transistor MP7 and the current I5 amplified by the third current mirror circuit 24 through the MOS transistor MN13 are detected. Is
The voltage is the same and a voltage of the same level as the input signal is output to the output terminal OUT (in this embodiment, the pair of input signals V (+) and V (-) is Vcc / 2 = 2.5V). In this case, the output voltage will be 2.5V).

In this state, when the potential of the input signal V (+) rises, the current I1 flowing in the MOS transistor MN9
Increases, and the current I2 flowing through MN10 decreases. As a result, the MOS on the output side of the first current mirror circuit
The gate voltage of the transistor MP7 rises to decrease its on-resistance in order to increase its drain current, and the MOS transistor MN13 of the third current mirror circuit 24 drops its gate voltage to decrease its drain current in order to decrease its on-resistance. Becomes higher. As a result, the output voltage Vout increases.

On the other hand, from the above-mentioned balanced state, the input signal V (+)
When the potential of the voltage drops, the current I1 flowing through the MOS transistor MN9 decreases and the current I2 flowing through MN10 increases. As a result, the gate voltage of the MOS transistor MP7 on the output side of the first current mirror circuit drops to reduce its drain current and the ON resistance increases, and the MOS transistor MN of the third current mirror circuit 24 increases.
In No. 13, the gate voltage rises and the on-resistance decreases in order to increase the drain current. As a result, the output voltage Vo
ut goes down.

Further, the differential amplifier circuit of this embodiment has the first
Even when the currents on the output side of the current mirror circuit and the output current of the third current mirror circuit do not match, the change in the impedance of the node n3 is small, and therefore, the change in the negative feedback characteristic by the phase compensation circuit is small.

Further, in the CMOS differential amplifier circuit of this embodiment, the constant current source of the differential input stage 21 is composed of MOS transistors MN7 and MN8 connected in series, the gates of which are biased by constant voltages V3 and V4. Therefore, the transistor MN7 operates so that the drain current of the MN8 is not affected by the DC voltage fluctuation of the input signal, so that the differential input stage can be biased with a current that is less affected by the input voltage. MOS transistor MN7
As the bias voltages V3 and V4 applied to the gates of, the constant voltage such that V3 is 1.2V and the constant voltage such that V4 is 2.8V are selected.

The values of K, L, and M may be values such as "6", "2.5", "2.4". Further, when the CMOS differential amplifier circuit of the above embodiment is formed by a known semiconductor manufacturing technique, if the process technique used is 1 μ process, the size ratios K, L,
Since M becomes the current ratio as it is, there is no problem, but when using processing technologies of different precision, the size ratio does not become the current ratio for K out of K, L, M, so the value of K It has been clarified by simulation that it is necessary to devise a method such as correcting this slightly and determining the value. For example, when using a processing technique such as 0.8 μ process, the MOS transistor MP4
In order to K the current ratio of MP7 and MP7, it is appropriate to set the size ratio to a value slightly larger than the value of the current ratio K.

2 and 3 show second and third embodiments of the CMOS differential amplifier circuit according to the present invention. Of these, FIG. 2 shows an example of a CMOS differential amplifier circuit for lowering the current consumption, and FIG. 3 shows C with an expanded allowable range of the input voltage.
An example of a MOS differential amplifier circuit is shown.

The CMOS differential amplifier circuit of FIG. 2 has a constant voltage V
5, a cascode type constant current source 31 biased by V6,
There are two sets of differential input stages 33 and 34 each independently having 32, and the differential MOS transistors MN19 and MN20 forming the differential input stage 33 have a W / L value ratio of a: 1.
Differential MOS transistor MN that constitutes the differential input stage 34
22 and MN21 have a W / L value ratio of 1: a.
The positive input signal V (+) is input to the gates of MN20 and MN22, and the negative input signal V (-) is input to the gates of MN20 and MN21.

A load MOS transistor MP9 connected to the drain of the differential MOS transistor MN22 constituting the differential input stage 34 and an M having its gate commonly connected.
A load MOS transistor MP8 connected to the drain of the differential MOS transistor MN20 constituting the differential input stage 33 by the OS transistor MP11 and a MOS transistor MP1 having its gate commonly connected.
0 and the first and second current mirror circuits 3
5 are configured. Further, the third side including the MOS transistors MN11, MN13; MN12, MN14 on the drain side of the MOS transistors MP10, MP11.
Current mirror circuit 24 is connected.

The first current mirror circuit is a MOS
The current is amplified K times by setting the ratio of W / L (gate width / gate length) of the transistors MP9 and MP11 to 1: K (K> 1). The second current mirror circuit amplifies the current L times by setting W / L of the MOS transistors MP8 and MP10 to 1: L (L> 1, L ≠ K). Further, in the third current mirror circuit 24, as in the first embodiment, the MOS transistors MN11 and MN13, and MN12 and MN14 are formed to have a size ratio of 1: M (M = K / L). As a result, the current is amplified M times.

In the CMOS differential amplifier circuit of this embodiment, the differential MOS transistor MN1 forming the differential input stage 33 is used.
9 and MN20 have a W / L value ratio of a: 1, and differential MOS transistors MN22 and M constituting the differential input stage 34
N21 has a W / L value ratio of 1: a,
M on the input side of the first and second current mirror circuits 35
The current flowing through the OS transistors MP8 and MP9 is
While the currents flowing through the MOS transistors MP4 and MP5 on the input side of the first and second current mirror circuits 23 in the above embodiment are half the currents flowing through the constant current source 21, respectively, 1 of the current flowing through 32
It can be (a + 1). As a result, the current flowing on the output side of the current mirror circuit can be reduced as compared with the first embodiment, and the current consumption of the entire circuit can be reduced. That is, the CMOS differential amplifier circuit of the second embodiment performs class AB amplification operation. It is to be noted that it is appropriate that the value of the above-mentioned a is about "5" to "10".

The CMOS differential amplifier circuit of FIG. 3 has a constant voltage V
Cascode type constant current source 41 biased by 7, V8
And a differential input stage 43 composed of differential MOS transistors MN25 and MN26 composed of N-channel MOSFETs,
A differential MO composed of a P-channel MOSFET and a cascode type constant current source 42 biased by constant voltages V9 and V10.
The differential input stage 44 includes S transistors MP14 and MP15. The positive input signal V (+) is applied to the gates of the MOS transistors MN25 and MP14.
However, a negative input signal V is applied to the gates of MN26 and MP15.
(-) Is input.

The first to third current mirror circuits 45, 46 and 24, which are constructed in the same manner as in the first embodiment, are connected to 43 of the two sets of differential input stages. Further, in this embodiment, the load MOS transistors MN27 and MN28 of the differential input stage 44 have MOS transistors MN30 and MN29 having a size ratio of 1: 1 with them.
Is provided, and the drains of these MOS transistors MN29 and MN30 are load MOS transistors MP1 on the differential input stage 43 side.
6, connected to the drain (gate) of MP17.
Therefore, a differential MO is applied to the load MOS transistor MP16.
A current obtained by adding the currents flowing through the S transistors MN25 and MP15 flows, and a current obtained by adding the currents flowing through the differential MOS transistors MN26 and MP14 flows through the load MOS transistor MP17.

Thus, the input signals V (+) and V
(-) Becomes relatively small and the MOS transistor MN2
5 and MN26, the output current on the P-MOS differential input stage 44 side is transferred to the MOS transistors MN30 and MN29 by the current mirror circuit 47, so that the N-MOS differential input stage. 43
A constant current flows through the load MOS transistors MP16 and MP17 on the side, and the allowable input voltage range for linear operation is widened.

As described above, in each of the above embodiments, the first current mirror for amplifying the current flowing through one of the differential input MOS transistors in the differential input stage at a ratio of 1: K (K> 1). Circuit, a second current mirror circuit that amplifies the current flowing through the other differential input MOS transistor at a ratio of 1: L (L> 1, L ≠ K), and is amplified by this second current mirror circuit. The current is further 1: M (M = K /
A third cascode current mirror circuit that amplifies at a ratio of L) is provided, and the current amplified by the first current mirror circuit is added and combined with the output current of the third current mirror circuit to obtain the first current mirror circuit. Since the other current is regulated by the smaller one of the current amplified by the current mirror circuit and the current amplified by the third current mirror circuit, the output voltage is obtained. Since the current mirror circuit is a cascode type, the change in the current gain is small with respect to the change in the DC potential of the input signal,
Also, the change in current gain is small even during the transitional period when a difference between the positive and negative input signals occurs. Further, since the phase compensation is performed by connecting a capacitance between the output terminal and the current input node of the third current mirror circuit, the impedance of the input node of the third current mirror circuit is small, and
There is little change in the negative feedback characteristic due to the phase compensation capacitance. As a result, when a voltage follower is configured and used as a video buffer circuit required for a character addition function to a video signal in a video signal processing LSI, a multiple addition function of a video signal, and an A / D conversion function of the video signal. , DG (differential gain) with little change in frequency characteristics of gain and phase
A characteristic and a DP (differential phase) characteristic are obtained. Moreover,
Since the current mirror circuit has a good ripple removal rate of the power supply voltage, there is an effect that it is possible to realize a CMOS differential amplifier circuit that is resistant to noise from a digital circuit that enters through the power supply line.

Further, since the current amplification ratio by each current mirror circuit is 1 or more (K> 1, L> 1, M> 1), the DC offset when operating as a voltage follower constitutes a current mirror circuit. MOS transistors (MP4 and MP7, MP5 and MP6, MN11
And MN13 and MN12 and MN14) are offset by 1 / K, 1 from the differential input stage, respectively.
/ L, 1 / M · L, 1 / M · L, the differential MOS transistor pair (M
(N9, MN10) is the only offset due to the variation, and the load MO is added to the offset of the differential MOS transistor pair.
There is an effect that the sum of the offsets of the pair of S transistors is smaller than the differential amplifier circuit of FIG.

Further, as in the second embodiment, each of the differential input stages is operated by an independent current source 1: a.
And a composed of MOS transistors of a: 1 size ratio 2
If the differential input stages are replaced, the output current of the differential input stage becomes 1 / (a + 1) of the current flowing in the constant current source, and the output current of the two differential input stages becomes When there is a difference between the positive and negative input signals, alternating currents having opposite phases are output, so that the operation of the output circuit is a class AB amplifying operation, which has the effect of reducing current consumption.

Further, as in the third embodiment, the differential input stage has two sets of differential inputs composed of a P-channel MOS transistor pair and an N-channel MOS transistor pair which are operated by independent current sources. By replacing with a stage, there is an effect that the allowable input voltage range for linear operation can be expanded.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. Figure 1
In the embodiment of FIG. 3, the phase compensation circuit Zf is connected to the capacitor C2.
Although it is configured by only the capacitor C2 as in the embodiment of FIG.
The resistor R2 may be connected in series with. Also,
On the contrary, the phase compensating circuit Zf including the capacitor C2 and the resistor R2 in the embodiment of FIG. 2 may be a phase compensating circuit including only the capacitor C2.

In the above description, the invention made by the present inventor has been mainly described by taking the video buffer circuit in the video signal processing LSI which is the field of application as the background, but the present invention is not limited thereto. Instead, it can be used for general differential amplifier circuits used as voltage followers.

[0044]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, changes in frequency characteristics of gain and phase with respect to changes in DC voltage of an input signal are small, DG (differential gain) characteristics and DP (differential phase) characteristics as a video buffer are excellent, and the power is supplied through a power supply line. It is possible to realize a CMOS differential amplifier circuit that is resistant to noise from an incoming digital circuit and has a small DC offset.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a CMOS differential amplifier circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of a CMOS differential amplifier circuit according to the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the CMOS differential amplifier circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of a CMOS differential amplifier circuit examined prior to the present invention.

[Description of Reference Signs] 21, 31, 32, 41, 42 Current Sources 22, 33, 34, 43, 44 Differential Input Stages 23, 35, 45, 46 Current Mirror Circuit 24 Third Current Mirror Circuit (cascode type current (Mirror circuit)

Front page continuation (72) Inventor Atsuhiko Nakauchi 5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (72) Inori Masanori Suganuma 5-22, Josuihonmachi, Kodaira-shi, Tokyo No. 1 inside Hitachi Microcomputer System Co., Ltd.

Claims (6)

[Claims] 1. A pair of differential MOS transistors whose sources are commonly connected.
A differential input stage composed of transistors, a current source connected to a common source of the differential MOS transistor, and a current flowing through one differential MOS transistor of the differential input stage of 1: K (K> 1) The current flowing through the first current mirror circuit composed of the MOS transistor for amplifying by the ratio and the other differential input MOS transistor is 1: L (L> L).
The second current mirror circuit composed of a MOS transistor for amplifying at a ratio of 1, L ≠ K, and the current amplified by the second current mirror circuit is further 1: M (M = K).
/ L), a cascode-type third current mirror circuit configured by a MOS transistor that amplifies at a ratio of / L) is provided, and the current amplified by the first current mirror circuit is used as an output current of the third current mirror circuit. The output voltage is obtained by adding and synthesizing so that the other current is regulated by the smaller one of the current amplified by the first current mirror circuit and the current amplified by the third current mirror circuit. A CMOS differential amplifier circuit characterized by: 2. The current source comprises a plurality of Ms connected in series.
The CMOS differential amplifier circuit according to claim 1, comprising an OS transistor. 3. A phase compensating circuit composed of a capacitor or a capacitor in series form and a resistor is connected between the output terminal and the input terminal of the third current mirror circuit. 1. The CMOS differential amplifier circuit according to 1 or 2. 4. A first differential input stage comprising a pair of differential MOS transistors which are commonly connected to sources and have a W / L value ratio of a: 1, and a differential of the first differential input stage. MOS
A first current source connected to the common source of the transistor and a source commonly connected so that the W / L value ratio is a: 1 and the same input signal as that of the first differential input stage is input. Second differential input stage composed of a pair of differential MOS transistors, and a differential MOS of the second differential input stage
A second current source connected to a common source of the transistor, the first differential input stage includes the first current mirror circuit, and the second differential input stage includes the second current source. 4. The CMOS differential amplifier circuit according to claim 1, wherein mirror circuits are connected to each other. 5. A first differential input stage composed of a pair of first-conductivity-type MOS transistors whose sources are commonly connected, and a common source of differential MOS transistors of the first differential input stage. A first current source and a pair of second conductivity type, which are connected in common to the sources and are operated by a carrier different from the first conductivity type, to which the same input signal as the first differential input stage is input. A second differential input stage consisting of a MOS transistor, a second current source connected to the common source of the differential MOS transistors of the second differential input stage, and the second differential input stage. Connected to one output node 1:
A fourth and a fifth current mirror circuit for flowing a current at a ratio of 1, and the output side currents of the fourth and fifth current mirror circuits are the two output currents of the first differential input stage. 5. The CM according to claim 1, 2, 3 or 4, wherein the first and second current mirror circuits that operate in the same polarity are connected so as to flow from the input side.
OS differential amplifier circuit. 6. The CMOS differential amplifier circuit according to claim 1, wherein the output terminal is directly connected to the inverting input terminal side, and the video signal is input to the non-inverting input terminal. A video signal processing device comprising: