JPH01128569A - Field effect transistor - Google Patents

Abstract

PURPOSE:To increase the amount of gain reduction efficiently with the decrease in power gain being suppressed, by forming at least a channel forming region on the surface of a one-conductivity type semiconductor layer, also forming gates on said channel forming region through a gate insulating film, and providing a one-conductivity type high concentration embedded layer at a specified position beneath said channel forming region. CONSTITUTION:A P<+>-type region is formed selectively on a semiconductor substrate 1 comprising P-type Si. Thereafter epitaxial growing is performed. A P<+>-type embedded layer 1a and a p-type epitaxial layer 2 are formed. Then, an N<+>-type source 3, a drain 5, impurities 4, a gate oxide film 6, a source electrode 9, a drain electrode 10, and first and second gates 7 and 8 are formed on the surface of the epitaxial layer 2. Therefore the leakage of electric lines of force, i.e., the leakage of a signal, from the channel forming region of a FET on the side of the first gate into the drain 5 due to the P<+> type embedded layer is not shielded when gain reduction is applied. The characteristic of gain reduction with the second gate is not impaired as in a conventional device. The excellent characteristics are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor (hereinafter referred to as FET), and particularly to a dual gate MOSFET with improved gain reduction characteristics.

[Conventional technology]

Conventionally, in this type of dual-gate MOSFET, a p-type lightly doped epitaxial layer 2'' is formed on a p-type heavily doped semiconductor substrate 1'' in order to improve the gain reduction characteristics, as shown in Fig. 3. an n-type high concentration source 3'', a drain 5'' and an impurity layer 4'' therebetween,
First and second gates 7'' and 8'' are provided on the channel forming region of the epitaxial layer N2'' through a gate insulating film 6'', and source and drain electrodes are connected to the source 3'' and drain 5'', respectively. 9 and 10'' are provided.

Here, the p-type high concentration semiconductor substrate 1'' is electrically connected to the source 3'' and serves as a shield to prevent signals from leaking from the lower part of the first gate 1'' to the drain 5''. Further, the concentration of the epitaxial layer 2'' can be arbitrarily selected and is selected so that the threshold voltage VT becomes a predetermined value.

[Problem that the invention seeks to solve]

In the above-mentioned conventional MOSFET, since the opposing area between the semiconductor substrate 1'' and the drain 5'' is large, the capacitance therebetween is so large that it cannot be ignored. When used for applications such as the following, there was a drawback that high frequency characteristics such as a decrease in power gain were impaired.

[Means for solving problems]

The field effect transistor of the present invention includes at least a channel formation region on the surface of a -conductivity type semiconductor layer and a gate formed on the channel formation region with a gate insulating film interposed therebetween, and a predetermined region below the channel formation region. A high concentration buried layer of one conductivity type is provided at the position.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

This embodiment is not designed for use with VHF band TV tuners.
This is an fI gate N-channel dual-gate MO8FET, and in order to form it, first, a P+ type region is selectively formed on a semiconductor substrate 1 made of p-type Si with a specific resistance of 10Ω, and then epitaxial growth is performed to form a P+ type region. Embedded layer 1
A and p type epitaxial layers 2 are formed. here,
To selectively form the P+ type buried M 1 a, boron ions are implanted at an energy of 30 KeV and a dose of 2.
X 1013C11-2 conditions, 100
Annealed for 10 minutes in a 0''C+N2M atmosphere, and then pressed for 48 hours at 1100°C in an inert atmosphere.

Also, the epitaxial layer 2 has a resistivity of 4Ω and a thickness of 2.5Ω.
This is a p-type paper density layer of μm.

On the surface of the epitaxial layer 2 on the semiconductor substrate 1 obtained in this way, an n+ type source 3. Drain 5. Impurity 4
．． Gate oxide film6. A source electrode 9, a drain electrode 10, and first and second gates 7 and 8 are formed.

Here, the electrodes and gates are all Aρ and are deposited using a sputtering method, and the buried layer 1a is electrically connected to the source 3.

Therefore, when applying a so-called gain reduction in which a negative potential is applied to the second gate to cut off the FET on the second gate side, if there is a P+ type buried layer 1a, the channel formation area of the FET on the first gate side is Leakage of electric lines of force from the drain 5 to the drain 5, that is, signal leakage, is blocked, and the gain reduction characteristics by the second gate are not impaired as in the conventional case, and exhibit good characteristics.

Furthermore, the opposing area of the P"-type buried layer 1 under the N"-type drain 5 is small, and most of it is an epitaxial layer 2 with a p-type paper concentration, so that the train-source interspace ficoss is smaller than that of the conventional example. is greatly reduced.

FIG. 2 is a sectional view of a second embodiment of the invention.

This example is a molybdenum gate N-channel dual gate MOSFET designed for a UHF band TV tuner.
ET, and in order to form this, first, a P+ type region is selectively formed in a p-type semiconductor substrate 1, and then epitaxial growth is performed to form a P"-type buried a1a' and a p-type buried region a1a'. An epitaxial layer 2' is formed.

Next, an n1 type source 3' and drain 5' are formed on the surface of the epitaxial layer 2', and first and second molybdenum gates 7' and 8' are formed via a gate oxide film 6'. Using this as a mask, N-type low concentration impurity layers 3a', 4' and 5a' are formed by ion implantation.

Therefore, a P+ type buried Jla' exists below the impurity layers 3a', 4' and 5a', but not below the N+ type doped source 3' and drain 5'.

That is, the N4 type high concentration source 3' and drain 5' and p
"Since the distance between the mold and the buried layer 1a' can be increased and the opposing area can be reduced, it is possible to not only reduce the capacitance but also improve the breakdown voltage between the train and the source.

〔Effect of the invention〕

As explained above, the present invention prevents signals from leaking from the lower part of the first gate to the drain side by providing a high concentration buried layer below the channel formation region, and also reduces the output capacitance C3ss. VHF'PUH
When used in a high frequency band circuit such as an F-band TV tuner, it is possible to provide a high frequency FET that can efficiently increase the amount of gain reduction while suppressing a decrease in power gain.

Embodiment 2 is a sectional view, and FIG. 3 is a sectional view of an example of a conventional FET.

1.1"...Semiconductor substrate, la, la'...Buried layer, 2.2', 2~...Epitaxial layer, 3°3'
, 3"...source, 3a', 4.4', 4".

5a'... Impurity layer, 5.5', 5"... Drain, 6.6', 6"... Gate oxide film, 7.7', 7"
...First gate, 8.8', 8"...Second gate, 9.9', 9"...Source electrode, 10.10'.

10″...Drain electrode.

Claims (1)

[Claims] It comprises at least a channel formation region on the surface of a semiconductor layer of one conductivity type and a gate formed on the channel formation region via a gate insulating film, and a high concentration semiconductor layer of one conductivity type is provided at a predetermined position below the channel formation region. A field effect transistor characterized by providing a buried layer.