JPH01125996A - Pattern formation - Google Patents
Pattern formationInfo
- Publication number
- JPH01125996A JPH01125996A JP28325387A JP28325387A JPH01125996A JP H01125996 A JPH01125996 A JP H01125996A JP 28325387 A JP28325387 A JP 28325387A JP 28325387 A JP28325387 A JP 28325387A JP H01125996 A JPH01125996 A JP H01125996A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- stencil
- layer
- layers
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007261 regionalization Effects 0.000 title description 5
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 6
- 239000002952 polymeric resin Substances 0.000 claims 2
- 229920003002 synthetic resin Polymers 0.000 claims 2
- 239000004642 Polyimide Substances 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 229920000642 polymer Polymers 0.000 claims 1
- 229920005989 resin Polymers 0.000 abstract description 12
- 239000011347 resin Substances 0.000 abstract description 12
- 238000009499 grossing Methods 0.000 abstract 1
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229920003986 novolac Polymers 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910003271 Ni-Fe Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
- H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜磁気ヘッド作製プロセス等において、高
Ｍ度な導体コイルパターン形成に好適なりフトオフ法を
用いたパターン形成技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern forming technique using a foot-off method, which is suitable for forming a conductor coil pattern with a high M degree in a thin film magnetic head manufacturing process and the like.
薄膜磁気ヘッド作製プロセス等において、導体コイルは
上下磁極の間に形成する。この導体コイルの形成方法と
して、周知のようにエツチング法。In the process of manufacturing a thin film magnetic head, a conductor coil is formed between the upper and lower magnetic poles. The well-known etching method is used to form this conductor coil.
メツキ法、リフトオフ法などがある。コイルパターン形
成後、上部磁極を積層する前に、樹脂の塗布、バイアス
スパッタ、エッチバックなどによって、コイル段差によ
って生じた凹凸の平坦化を行なう。There are methods such as the Metsuki method and the lift-off method. After the coil pattern is formed and before the upper magnetic pole is laminated, the unevenness caused by the coil steps is flattened by resin coating, bias sputtering, etching back, etc.
ここで、上記凹凸の段差は数μｍに達するため、上記の
樹脂の塗布法、バイアススパッタ法、エッチバック法な
どでは、段差と同等以上の膜厚を積層する必要があり、
平坦化を行なうプロセスが非常に煩雑であった。Here, since the level difference between the above-mentioned unevenness reaches several μm, the above-mentioned resin coating method, bias sputtering method, etch-back method, etc. requires laminating a film with a thickness equal to or greater than the level difference.
The process of flattening was extremely complicated.
本発明の目的は、簡便なパターン形成ならびにその平坦
化法を提供することにある。An object of the present invention is to provide a simple method for pattern formation and planarization thereof.
上記目的は、リフトオフ法を用いてパターン形成を行な
い、さらにリフトオフに用いるステンシル層を２層以上
の層に分割し、その一部を除去せずにパターン間に残す
ことによって、達成される。The above object is achieved by forming a pattern using a lift-off method, and further dividing the stencil layer used for lift-off into two or more layers, and leaving a part of the layer between the patterns without removing it.
以下、本発明の作用を第１図を用いて説明する。 Hereinafter, the operation of the present invention will be explained using FIG.
まじめに、基板１上に、下部ステンシル層２．上部ステ
ンシル層３．ステンシル層加工用のマスク層４を積層し
、続いて所望の形状のレジストパターン５を形成する（
同図（ａ）。Seriously, on the substrate 1, the lower stencil layer 2. Upper stencil layer 3. A mask layer 4 for processing the stencil layer is laminated, and then a resist pattern 5 of a desired shape is formed (
Same figure (a).
このレジストパターン５をマスクにマスク層４を加工し
く同図（ｂ）’）、続いて、上部・下部のステンシル層
３，２を加工する（同図（Ｃ））。Using this resist pattern 5 as a mask, the mask layer 4 is processed ((b)'), and then the upper and lower stencil layers 3, 2 are processed ((c) of the same figure).
その後、所望の材料をステンシルパターンを有する基板
上に被着する（同図（ｄ））。Thereafter, a desired material is deposited on the substrate having the stencil pattern (FIG. 4(d)).
続いて、ステンシル層を除去してリフトオフを行なう（
同図（ｅ））。このとき、上下のステンシル層として選
択的に除去できる材料を選ぶことによって下部ステンシ
ル層だけを選択的に残すことができる。続いてパターン
とステンシル層間のわずかな空隙を充填し平坦化させる
ため樹脂層７を塗布する。Next, remove the stencil layer and perform lift-off (
Figure (e)). At this time, by selecting materials that can be selectively removed for the upper and lower stencil layers, only the lower stencil layer can be left selectively. Subsequently, a resin layer 7 is applied to fill and flatten the slight gap between the pattern and the stencil layer.
以上のように、パターン間にステンシル層の一部を残す
ことができるので、パターン形成後の表面の平坦化を容
易に行なうことができる。As described above, since a portion of the stencil layer can be left between the patterns, the surface can be easily flattened after pattern formation.
以下、本発明を薄膜磁気ヘッドに適用した場合の実施例
を第１図を用いて説明する。はじめ下地上に膜厚１．５
μｍのＮｉ−Ｆｅ合金からなる下部磁極およびその上に
膜厚０．２μｍのＡ１２２０３からなる絶縁膜を被着し
たものを基板１とする。An embodiment in which the present invention is applied to a thin film magnetic head will be described below with reference to FIG. Initially, the film thickness is 1.5 on the substrate.
A substrate 1 includes a lower magnetic pole made of a Ni-Fe alloy with a thickness of 0.2 μm and an insulating film made of A12203 with a thickness of 0.2 μm deposited thereon.
その上に以下に示す工程によって銅からなる導体コイル
パターンを形成する。A conductor coil pattern made of copper is formed thereon by the steps described below.
同図（ａ）に示すように基板１上に、下部ステンシル層
２として膜厚３μｍのＰＩＱ樹脂（日立化成社！りを塗
布・ベークにより形成する。続いて、その上に上部ステ
ンシル層３として、ノボラック樹脂を３μｍ積層する。As shown in FIG. 1A, a lower stencil layer 2 is formed on a substrate 1 by coating and baking a 3 μm thick PIQ resin (Hitachi Chemical Co., Ltd.).Subsequently, an upper stencil layer 3 is formed on the substrate 1. , Novolac resin is laminated to a thickness of 3 μm.
ノボラック樹脂には、通常ポジ型のホトレジストとして
用いられるＡＺレジスト（ヘキスト社製）を使用した。As the novolak resin, AZ resist (manufactured by Hoechst), which is usually used as a positive photoresist, was used.
その上のマスク層４には、膜厚０．１μｍのＳＯＧ （
スピン オン グラス）膜を用いた。その・後、通常の
露光現像により所望のレジストパターン５を形成する。The mask layer 4 on top of it is made of SOG (
A spin-on glass) film was used. Thereafter, a desired resist pattern 5 is formed by normal exposure and development.
次にＣＦ４ガスを用いた反応性イオンエツチングを用い
て、レジストをマスクにマスク層４をエツチングする（
同図（ｂ））。続いてこのマスク層をマスクに、Ｏｚガ
スを用いた反応性イオンエツチングにより上部・下部の
ステンシル層３，２を同時にエツチングする。このとき
、０２ガス圧２Ｘ１０−’Ｐａ、Ｐａ−は２００Ｗとし
た。ここでＰＩＱ樹脂ならびにＡＺレジストのエツチン
グ速度は、ＳＯＧ膜のエツチング速度に較べて極めて大
きいため、側面がほぼ垂直なステンシルパターンが得ら
れる。ここで、さらにオーバエツチングを行なうか、ま
たは０２ガス圧を約１．５倍はど高くマてオーバエツチ
ングを行なうことにより、オーバハング状のリフトオフ
に適したステンシルパターンが形成できる（同図（Ｃ）
）。Next, the mask layer 4 is etched using the resist as a mask using reactive ion etching using CF4 gas (
Figure (b)). Subsequently, using this mask layer as a mask, the upper and lower stencil layers 3 and 2 are simultaneously etched by reactive ion etching using Oz gas. At this time, 02 gas pressure 2X10-'Pa, Pa- was set to 200W. Here, since the etching speed of the PIQ resin and the AZ resist is much higher than the etching speed of the SOG film, a stencil pattern with substantially vertical sides can be obtained. At this point, a stencil pattern suitable for overhang-like lift-off can be formed by further over-etching or by increasing the 02 gas pressure by about 1.5 times (see figure (C)).
).
次に、このステンシルパターン上に蒸着によって銅から
なる被着層６を３μｍ被着する（同図（ｄ））。次にこ
の基板を、アセトン溶液中に浸漬する。ここで、ノボラ
ック樹脂はアセトンに可、溶性であるのに対し、ＰＩＱ
は不溶性であるため、上部ステンシル層およびステンシ
ル層上の被着層のみ除去されＰＩＱからなる下部ステン
シル層は、銅パターン８の間に残されたままとなる（同
図（ｅ））。次にさらにＰＩＱ樹脂７を１μｍ塗布して
、銅パターンと下部ステンシル層間の空隙を充填し、平
坦化を行なう（同図（ｆ））。この後、平坦な表面上に
薄膜１．５μｍＮｉ−Ｆｅ合金からなる上部磁極（図示
省略）を形成し、薄膜磁気ヘッドとする。Next, on this stencil pattern, a layer 6 made of copper is deposited to a thickness of 3 μm by vapor deposition (FIG. 4(d)). This substrate is then immersed in an acetone solution. Here, while novolak resin is soluble in acetone, PIQ
Since PIQ is insoluble, only the upper stencil layer and the adhesion layer on the stencil layer are removed, and the lower stencil layer made of PIQ remains between the copper patterns 8 (FIG. 4(e)). Next, 1 μm of PIQ resin 7 is applied to fill the gap between the copper pattern and the lower stencil layer, and planarization is performed (FIG. 4(f)). Thereafter, an upper magnetic pole (not shown) made of a thin film of 1.5 μm Ni-Fe alloy is formed on the flat surface to form a thin film magnetic head.
以上述べてきｈ本実施例によれば、導体コイル形成後も
、コイル間にステンシル層が残るので、コイル表面の平
坦化層を薄くすることができ、平坦化が容易にできると
いう効果がある。As described above, according to this embodiment, even after the conductor coil is formed, the stencil layer remains between the coils, so that the planarization layer on the coil surface can be made thinner, and the planarization can be easily performed.
ここで、本実施例では表面の平坦化法として樹脂の塗布
の場合を示したが、エッチバック法やバイアススバッタ
法を用いた場合においても同様に平担化に必要な膜厚を
薄くすることができる。Here, although this example shows the case of coating a resin as a method for flattening the surface, the film thickness required for flattening can be similarly reduced when using an etch-back method or a bias spatter method. be able to.
なお、上記実施例では、上部および下部のステンシル層
として、ＡＺレジストとＰＩＱ樹脂を用いたが反応性イ
オンエツチングを加工でき１選択的に除去できる材料の
組み合わせであれば良い。In the above embodiment, AZ resist and PIQ resin were used as the upper and lower stencil layers, but any combination of materials that can be processed by reactive ion etching and selectively removed may be used.
したがって、例えば上部ステンシル層、下部ステンシル
層、および除去のための溶媒として、ＰＭＭＡレジスト
、ＰＩＱ樹脂、アセトンの組合せか、ＡＺレジスト、架
橋したノボラック樹脂、アセ１−ンの組合せ、また溶媒
として通常レジスト除去に用いられるフェノール系のレ
ジスト剥離液を用いることもできる。Thus, for example, a combination of PMMA resist, PIQ resin, acetone or a combination of AZ resist, cross-linked novolac resin, acetone as a solvent for the upper stencil layer, lower stencil layer and removal, and also a conventional resist as a solvent. A phenolic resist stripper used for removal can also be used.
また、ステンシル層の加工用マスクとして、ＳＯＧ膜を
用いたが１通常の３層レジストプロセスで用いるＭｏ、
Ｔｉなどの金ｉｓや塗布型の酸化チタンなども使用する
ことができる。In addition, although an SOG film was used as a mask for processing the stencil layer, 1 Mo, which is used in a normal three-layer resist process,
Gold is, such as Ti, and coated titanium oxide can also be used.
さらに、本実施例では、薄膜磁気ヘッドの導体コイル形
成に関して述べたが、本発明は、他の薄膜デバイスのパ
ターン形成工程にも広く応用できることはいうまでもな
い。Further, in this embodiment, the formation of a conductor coil for a thin film magnetic head has been described, but it goes without saying that the present invention can be widely applied to pattern forming processes for other thin film devices.
本発明によれば、パターン形成後パターン間にステンシ
ル層を残すことができるので、パターン形成後の表面の
平坦化を容易に行なえるという効果がある。According to the present invention, since a stencil layer can be left between patterns after pattern formation, the surface can be easily flattened after pattern formation.
第１図は本発明の実施例の加工工程を説明する断面図で
ある。
１・・・基板、２・・・下部ステンシル層、３・・・上
部ステンシル層、４・・・マスク層、５・・・レジスト
パターン、第１ （！］
（Ｃン
ｌ 算堵
ど ハークーンFIG. 1 is a sectional view illustrating the processing steps of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Lower stencil layer, 3...Upper stencil layer, 4...Mask layer, 5...Resist pattern, 1st (!)
Claims (3)
、所望の材料を被着後、ステンシルパターンの除去しパ
ターン形成を行なうリフトオフ法において、ステンシル
パターンが膜厚方向に選択的に除去できる２層以上の材
料の異なる層からなることを特徴とするパターン形成方
法。1. Two or more layers of material from which the stencil pattern can be selectively removed in the film thickness direction in a lift-off method in which a desired material is deposited on a substrate having a stencil pattern in a desired area, and then the stencil pattern is removed to form a pattern. A pattern forming method characterized by comprising different layers.
よび次最隣接の各層が高分子樹脂からなることを特徴と
する特許請求の範囲第１項記載のパターン形成方法。2. 2. The pattern forming method according to claim 1, wherein in the stencil pattern, each of the layers closest to the substrate and the next closest to the substrate are made of a polymer resin.
高分子層が、ポリイミド系高分子樹脂からなることを特
徴とする特許請求の範囲第２項記載のパターン形成方法
。3. 3. The pattern forming method according to claim 2, wherein in the stencil pattern, the polymer layer closest to the substrate is made of a polyimide polymer resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28325387A JPH01125996A (en) | 1987-11-11 | 1987-11-11 | Pattern formation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28325387A JPH01125996A (en) | 1987-11-11 | 1987-11-11 | Pattern formation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01125996A true JPH01125996A (en) | 1989-05-18 |
Family
ID=17663063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28325387A Pending JPH01125996A (en) | 1987-11-11 | 1987-11-11 | Pattern formation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01125996A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5407530A (en) * | 1992-11-18 | 1995-04-18 | Mitsumi Electric Co., Ltd. | Method of preparing fine conductive pattern |
| KR100777234B1 (en) * | 2001-10-31 | 2007-11-19 | 주식회사 포스코 | Eccentric bottom tapping opener of electrode arc furnace |
-
1987
- 1987-11-11 JP JP28325387A patent/JPH01125996A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5407530A (en) * | 1992-11-18 | 1995-04-18 | Mitsumi Electric Co., Ltd. | Method of preparing fine conductive pattern |
| KR100777234B1 (en) * | 2001-10-31 | 2007-11-19 | 주식회사 포스코 | Eccentric bottom tapping opener of electrode arc furnace |
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