JPH01123553A - Pattern detecting circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit by responding to a special pattern identifying bit in a latch timing of a special pattern detected by a pattern detecting signal generating circuit and generating a timing signal to latch a detected pattern detecting signal to a pattern detecting signal accumulating circuit. CONSTITUTION:The detection of the special pattern of input serial data converted to parallel data by a serial parallel converting circuit 10 is executed by a pattern detecting signal generating circuit 12 and a timing signal is generated at the detecting time of a special pattern from a timing signal generating circuit 22. A detecting pattern signal is held at a pattern detecting signal accumulating circuit 14 by the timing signal and supplied for the use. Thus, it is not necessary to execute the counting of a clock for the generation of the timing signal and the circuit can be simplified.

Description

[Detailed Description of the Invention] [Summary] Regarding a pattern detection circuit that derives a latch timing signal of a pattern detection signal of a specific pattern of serial data from a specific pattern identification bit in the latch timing, the present invention aims to simplify the circuit. a serial-parallel conversion circuit that converts serial data into parallel data; a pattern detection signal generation circuit that generates a pattern detection signal of the converted parallel data; a pattern detection signal accumulation circuit that accumulates the detected pattern detection signal; a timing signal generation circuit that generates a timing signal that causes the pattern detection signal storage circuit to latch the detected pattern detection signal in response to a specific pattern identification bit at a latch timing of a specific pattern detected by the pattern detection signal generation circuit; It was composed of.

[Industrial application field]

The present invention relates to a pattern detection circuit that derives a latch timing signal for a pattern detection signal of a specific pattern of serial data from a specific pattern identification bit at latch timing.

A digital trunk such as a digital private branch exchange is configured to detect a specific pattern of serial data received on the trunk for control purposes, etc., and provide this to the exchange control unit.

[Conventional technology]

A conventional pattern detection circuit for the above-mentioned purpose is shown in FIG. In this figure, input serial data is converted into parallel data in a serial/parallel conversion circuit IO. The parallel data is applied to a pattern detection generation circuit 12, from which a pattern detection signal is output. On the other hand, the input serial data is input to the counter reset timing generation circuit 16, where the first bit of a specific pattern included in the manual serial data is detected. The pattern counter 18 is reset to zero by this leading bit detection signal (counter preset timing signal). This pattern counter 18 is supplied with a clock of the bit period of the input serial data, and generates a latch timing signal at the time when the pattern detection signal is output from the pattern detection generation circuit 12.

This latch timing signal is applied to the pattern detection signal storage circuit 14 to accumulate the pattern detection signal therein. The contents of the pattern detection signal storage circuit 14 are taken into the processor (MPU) of the exchange and used for its control.

[Problem that the invention seeks to solve]

As is clear from the above, this pattern detection circuit uses the counter reset timing generation circuit 16 and the pattern counter 18 to generate the latch timing signal. That is, the pattern counter 18 is characterized by counting constituent bits of a specific pattern.As the specific pattern length becomes longer, the hardware of the pattern counter 18, that is, the circuit becomes larger.

The present invention was created in view of such problems.
The object of the present invention is to provide a pattern detection circuit that can detect a specific pattern by simplifying the circuit.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. The circuit of the present invention includes a serial-to-parallel conversion circuit 1o, a pattern detection signal generation circuit 12,
It consists of a pattern detection signal storage circuit 14 and a timing signal generation circuit 22, and the timing signal generation circuit 22 detects a pattern in response to a specific pattern identification bit at the latch timing of a specific pattern signal detected by the pattern detection signal generation circuit 12. It generates a timing signal that causes the pattern detection signal storage circuit 14 to hold the pattern detection signal from the signal generation circuit 12.

[For production]

The pattern detection signal generation circuit 12 detects a specific pattern of the input serial data converted into parallel data by the serial/parallel conversion circuit 10, while the timing signal generation circuit 22 generates a timing signal at the detection time of the specific pattern. generated.

By this timing signal, the detection pattern signal is held in the pattern detection signal storage circuit 14 and made available for use.

Since there is no need to count clocks to generate a timing signal, the circuit can be simplified.

〔Example〕

FIG. 2 shows an embodiment of the invention. This example is 100
A circuit for detecting a specific pattern 00 is shown. In this figure, 10+ represents the inverted input bit serial data T'STT and the inverted receive clock -WτK
This is a shift register that is shifted in by the serial/parallel converter circuit 10 shown in FIG. 1
2. ．． 12□ are a four-manpower NAND gate and a one-manpower NAND gate, respectively, and these correspond to the pattern detection signal generation circuit 12 of FIG. 4-person Nando Gate 12. is shift register 10. output QB.

Connected to QC, QD, and QE. 221 is a latch circuit, and the circuit 22. D input of shift register 10
．． , and is connected to the output QF of the shift register 101 from the input of the latch circuit 22 . An example of the configuration of the timing signal generation circuit 22 shown in FIG. 1 has been shown up to this point. 14+, 1
4z is a latch circuit, which corresponds to the pattern detection signal storage circuit 14 in FIG. Latch circuit 1
The D input of 41 is connected to the output of a 1-input NAND gate 12□, and its clock input is connected to the output direction of the latch circuit 221. Latch circuit 14□ is latch circuit 14+
This is for resetting the shift register 1, and its D input is for shift register 1.
The clock input is connected to the output QA of the latch circuit 22.0I. connected to the output direction. Further, the output ζ is output from the latch circuit 14. It is connected to the glue set manual R.

This pattern detection circuit operates as follows.

For convenience of explanation, latch circuit 14. It is assumed that the bit serial data R3ER input to the shift register 101 is the second specific pattern 10000 in the state where the shift register 101 is set.

Each bit of the data R3ER is sequentially input to the shift register 101 by the clock RCLK ((2) in FIG. 3). This shift register is 10 years old! Divide rX
Therefore, the first bit "1" of the specific pattern 1oooo is shifted in the shift register 101 every clock from the input time T1 as shown in (3) to (8) in FIG. Sequential bit positions (output Q
A to QF). At that time TI, the first bit is in shift register 10. and its output QA
As is clear from the above conditions of the input serial data at that time, when the first bit of the preceding specific pattern appears in register 10. appears at the output QF of The signal level of this output QF is set in the latch circuit 22 in response to the rise of the clock RCLK. Therefore, the signal level in the output direction is at time 1 as shown in (9) in Figure 3.
It is at a high level for around 2 clock periods. Further, the latch circuit 22. This rising edge sets the signal level appearing at the output QA of the shift register 101 in the latch circuit 14□, so its output ζ becomes high level.

Then, when the clock time advances and reaches time T6, shift register 10. The first bit is output from the output QF of the latch circuit 22. after half a clock. A signal pulse (timing signal) as shown in (9) in FIG. 3 appears at point (d) in FIG.

At this time, shift register 10. The output QE, QD of
, QC, and QB respectively appear, and the detection of the specific pattern is a four-man NAND gate 12. The rising transition output that passes through the NAND gate 122 causes the latch circuit 141 receiving the above-mentioned signal pulse to set a pattern detection signal as shown in (11) in FIG.

When such a pattern is detected, the latch circuit 14
．． The pattern detection signal set to is reset if that specific pattern is not continuously input. for example,
When a serial data bit stream DP as shown in the figure is input following the specific pattern SP shown in FIG.
As is clear from the timing chart in the figure, the first bit °“1°” of the data bit stream DP is in the shift register 10. appears in the output QF ((9) in Figure 3)
), and shift register 10. After half a clock has elapsed from time Tll when the sixth bit "°0" of the bit stream DP input to the shift register io+ is shifted into the shift register io+ (see (3) in FIG. 3), the latch circuit 14
Although the output direction of □ falls to a low level (see 00 in FIG. 3), the latch circuit 141 is reset by the rising transition. That is, the pattern detection signal that has been detected and set is switched to a low level ((11) in Figure 3).
reference).

In the above example, the specific pattern 10Ooo is 001:000011 when looking at its repetition in time.
It can also be seen as a repetition of a specific pattern of 00001 when separated like 000. Therefore, bit "1" can be seen as the first bit of the preceding specific pattern as in the embodiment, or it can be seen as the last bit.Also, the latch circuit can be reset after it is set there. , it may be reset after a predetermined time.

〔Effect of the invention〕

As described above, according to the present invention, a circuit for detecting a specific pattern of serial data can be simplified and the detection can be performed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is a timing chart of the embodiment of Fig. 2, and Fig. 4 is an example of a conventional pattern detection circuit. It is a diagram. 1 and 2, 10 is a serial-to-parallel conversion circuit (shift register 10.), 12
is a pattern detection signal generation circuit (4-man powered NAND gate 12
1.1 Manual NAND gate 12, 14 is a pattern detection signal storage circuit (latch circuit 14), and 22 is a timing signal generation circuit (latch circuit 22). Patent applicant: Fujitsu Limited
Fujitsu Kansai Communication System Co., Ltd. Main layer January Hara Kori 7 "Rock diagram Figure 1 Book ≦ Date and month arrow-specific buoy row Figure 2 /'% -/'% -, -, -^ ^ ^ -6C-
To 1 length LnI-Or+-Nono-1

Claims (1)

[Claims] A serial-to-parallel conversion circuit (10) that converts serial data to parallel data, a pattern detection signal generation circuit (12) that generates a pattern detection signal of the converted parallel data, and a detected pattern detection circuit. Pattern detection signal accumulation circuit that accumulates signals (
14), and in response to the specific pattern identification bit at the latch timing of the specific pattern detected by the pattern detection signal generation circuit (12), the detected pattern detection signal is sent to the pattern detection signal storage circuit (14). A pattern detection circuit comprising a timing signal generation circuit (22) that generates a timing signal to be latched.