JPH01123527A - Phase locked loop - Google Patents

Abstract

PURPOSE:To resolve to be placed in a dilemma between a jitter problem and a modulation problem by making the frequency of an error signal supplied to a loop filter into four times to the frequency of the input signal of a phase comparator. CONSTITUTION:Without changing the basic character of a phase locked loop (PLL), the frequency of an error signal supplied to a loop filter 16 is made into four times as much as a signal frequency supplied to phase comparators 13 and 14. Consequently, the freedom degree of a design is improved in accordance with a use purpose. Namely, for the jitter problem to occur basically at a conventional PLL, since a loop band can be expanded to double compared with the conventional PLL, the jitter can be reduced to at least 1/2 or below. When the level of the jitter is placed to a reference, the AC part in an error voltage to a voltage control oscillator(VCO) 17 can be suppressed to 1/2 or below and a modulation phenomenon can be suppressed in proportion to it.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase-locked loop, and more particularly to a phase-locked loop capable of reducing jitter in a voltage controlled oscillator (VCO).

(Background of the Invention) In power line transmission of data, it is necessary to synchronize the power frequency with the modem of the data and perform phase synchronization by frequency multiplication. When performing multiplication by PL
As the multiplier of L increases, the jitter of vCO also increases, which becomes a problem.

Therefore, the present invention has devised a method to tackle this problem and systematically improve it.

(Prior Art) PLLs have been widely used in modulators, demodulators, servo systems, and others. That PLL is basically the fifth
This can be represented by the configuration shown in the figure.

First, the input signal ei(t) is supplied from the input terminal 1 to the phase comparator 2. On the other hand, a voltage controlled oscillator (i.e., V
The output signal e o(t) of CO) 4 is output to the output terminal 5, and is also fed back to the phase comparator 2, and the input signal ei(
t) and the output signal e of the 6-phase comparator 2, whose phase is compared with
r(t) is output as an error signal, and is further converted to an error voltage Er(t) via a loop filter 3 and applied to VC.
An output signal e o(t) is supplied to O4, the phase of the oscillation output of VCO4 is controlled, and is synchronized with the input signal ei(t).
is output.

Now, let the phase of the input signal e1(t) be θi, and the phase comparator 2
KC is the gain of KC, and the transfer function of loop filter 3 is F(s).
, the gain of VCO4 is KO/s, the output signal e o(t)
If the phase of is θ0, the number of loop transmissions θ0(S)/
θ1(s) is expressed as follows. The transmission number of this loop θ0(S)/θ1
(s), the natural angular frequency ωn of the loop, the damping factor ζ, the lock range Δω, and the capture range Δω
C etc. are required. Further, the band in the loop needs to be determined depending on the purpose of use, and the loop band is determined by the loop gain and the cutoff frequency of the loop filter F (s).

(Problems to be Solved by the Invention) In PLL, temporary phase error (generally called jitter) of VCO, that is, jitter, tends to be a problem in frequency multiplication using PLL, and as the number of multipliers increases, the jitter increases. is strengthened. To suppress this jitter, it is necessary to widen the loop band, but on the other hand, the alternating current component of the error signal reaches a state where it cannot be ignored, so the oscillation frequency of the vCO is modulated by the alternating current component (angle modulation).
It becomes a problem. That is, there was a problem in which the jitter problem and the modulation problem were caught in the middle.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a PLL that improves the problem between the jitter problem and the modulation problem found in conventional PLLs.

(Means for Solving the Problems) In order to achieve the above object, the present invention supplies an input signal to a phase comparator, supplies an output signal of a voltage controlled oscillator to the phase comparator, and supplies the input signal to the phase comparator. In the phase locked loop, the error signal outputted from the phase comparator is converted into an error voltage via a loop filter, and the error signal is supplied to the voltage controlled oscillator. The present invention provides a phase-locked loop characterized in that the frequency of the phase comparator is four times the frequency of the input signal of the phase comparator.

(Embodiment) An embodiment of the PLL according to the present invention will be explained below with reference to the drawings. The configuration of the present invention is shown in FIG. 1, the waveforms of each part are shown in FIG. 2, and the configuration of FIG. The equivalent basic configuration is the third one.
It is shown in Fig. 4.

In FIG. 1, an input signal ei(t) is supplied from an input terminal 11 to a phase comparator 13 and a π/2 phase shifter 12, respectively. Output signal e h(t) from the π/2 phase shifter 12
is supplied to the phase comparator 14.

On the other hand, the output signal e o(t) obtained from the VCO 17 via the 1/2 frequency divider 18 is supplied to the phase comparator 13, where the phase is compared with the input signal ei(t).

Further, the output signal e of the exclusive OR of the output of the VCOl 7 and the output signal e o(t) by the Ex-OR gate 19 is
oh(t) is supplied to the phase comparator 14, and the phase is compared with the output signal e h(t) of the π/2 phase shifter 12.

Output signal ec1(t) of phase comparator 13 and phase comparator 1
The output signal eC2(t) of 4 is supplied to the arithmetic circuit 15 for addition, and the error signal eC2(t) resulting from the addition is passed through the loop filter (LF) 16 at the next stage to become an error voltage Er.
(t) and supplied to VCOl 7.

Due to such loop feedback loop, the output signal e o(t) becomes phase synchronized with the input signal e 1(t).

Now, input signal ei(t) is cosωt [(a) in Fig. 2]
waveform]. Therefore, the output signal e h (t) of the π/2 phase shifter 12 becomes si ωt [the waveform of (b) in FIG. 2].

On the other hand, the output signal eo(t) obtained by passing the output signal of the VCO 17 through the 1/2 frequency divider 18 is expanded as follows, and has the waveform shown in FIG. 2(d).

Also, the output signal e oh(t) of the Ex-OR gate 19
The expansion equation eoh(ωt) is as follows, resulting in the waveform shown in FIG. 2(e).

Phase comparators 13 and 14 are ±π/2 type phase comparators (balanced transformers or functionally equivalent to analog multipliers).
are using.

Therefore, the expansion equation eC1(ωt) of the output signal eC1(t) of the phase comparator 13 is as follows, resulting in a waveform shown in (f) in FIG.

The expansion equation eC2(ωt) of the output signal ec2(t) of the phase comparator 14 is as follows, and has the waveform shown in (g) in FIG.

Note that the conventional PLL uses (4) as the phase comparator output signal.
), and the fundamental frequency of this output signal is as shown by 5in2ωt in the first term on the right side,
The frequency is twice that of the vCO output.

Next, the expansion formula er(ωt) of the output signal added by the arithmetic circuit 15, that is, the error signal er(t), becomes the waveform shown in (h) in FIG.

As is clear from equation 0, the fundamental frequency is 5in4ωt
The frequency is twice that of the phase comparator output of a conventional PLL (that is, the frequency is four times that of the phase comparator input signal).

Next, the loop operation of the - cycle will be explained with reference to FIG. In other words, the configuration in Figure 1 is equivalent to the configuration in Figure 3;
The configuration of the figure is also equivalent to that of FIG.

Phase comparator 13 in FIG. 1 corresponds to phase comparator 22 in FIG. 3, and phase comparator 14 in FIG. 1 corresponds to phase comparator 23 in FIG. 3. Furthermore, the 1/2 frequency divider 18 in FIG. 1 corresponds to the 1/2 frequency divider 27 in FIG.
Gate 19 corresponds to 1/2 frequency divider 28 in FIG. Furthermore, the phase comparators 22 and 23 in FIG. 3 correspond to the phase comparator 32 in FIG. 4, and the 1/2 frequency dividers 27 and 28 in FIG. 3 correspond to the 172 frequency divider 35 in FIG. do.

In FIG. 4, the input terminal is 31, the phase comparator is 32,
A loop filter 33, a 34.1/2 frequency divider 35, and an output terminal 36 are used as a VCO.

Now, the conversion gain of the phase comparator 32 is KC, the transfer function of the loop filter 33 is F(s), the conversion gain of the VCO 34 is KO/s, the gain of the 1/2 frequency divider 35 is Kd, and the input signal θ1( The output signal θ0(S) for s) is: θo(s)=-3÷1 can・θ1(S) (7)
(However, K = Kc - Ko - Kd), and compared to the conventional PLL, KC = 2. There is no difference from the gain distribution of Kd = 1/2, and the basic properties of the PLL are the same as those of the conventional PLL, as is clear from equation (7).

An embodiment of the phase-locked loop of the present invention is shown in FIG. The matched 1/2 frequency-divided signals are not limited to those according to the above-mentioned embodiment, and the arithmetic circuit 17 is not limited to addition, but also subtraction (however, the phase ratio divider input signal is opposite in phase). case)
But it's okay.

However, in this case, the one-round feedback loop is basically a negative feedback operation.

(Effect of the invention) As described above, the phase-locked loop of the present invention has the following effects:
The frequency of the error signal supplied to the loop filter is four times the frequency of the signal supplied to the phase comparator without changing the basic properties of the PLL, thus increasing the degree of freedom in design depending on the purpose of use. In other words, regarding the jitter problem that fundamentally occurs in conventional PLLs (mainly vCO jitter), since the loop bandwidth can be doubled compared to conventional PLLs, jitter can be reduced to at least 1/2 or less. It is possible. (The main component of VCO jitter is the 1/f noise of the transistor in the VCO, so
If the cutoff frequency of the loop filter is shifted to a high frequency that is twice as high, jitter can be suppressed by more than twice as much. ) Also, if the jitter level is taken as the standard, VC
It has the advantage that the AC component in the error voltage to O can be suppressed to less than 1/2, and therefore the modulation phenomenon can be suppressed in proportion to this.

Further, the present invention can significantly improve frequency multiplication by PLL.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the phase-locked loop according to the present invention, FIG. 2 is a diagram showing waveforms of various parts in FIG. 1, and FIG.・
FIG. 4 is a diagram showing the basic configuration of the loop. FIG. 5 is a diagram showing the configuration of a conventional phase-locked loop. 1.11.21.31...Input terminal, 2.13.14
, 22, 23.32... phase comparator, 3.16.25
．． 33...Loop filter (LF), 4.17, 26
．． 34・”Voltage controlled oscillator (VCO), 5.20, 29
．． 36... Output terminal, 12... π/2 phase shifter, 15
．． 24...Arithmetic circuit, 18.28.35...1/2
Frequency divider, 19...EX-OR gate.

Claims (2)

[Claims] (1) An input signal is supplied to a phase comparator, an output signal of a voltage controlled oscillator is supplied to the phase comparator to perform phase comparison with the input signal, and an error signal output from the phase comparator is filtered through a loop filter. In the phase-locked loop, the frequency of the error signal supplied to the loop filter is set to 4 with respect to the frequency of the input signal of the phase comparator.
A phase-locked loop characterized by a doubling. (2) means for supplying the input signal to the first phase comparator;
means for shifting the input signal by π/2 and supplying the input signal as a π/2 phase-shifted signal to a second phase comparator; and comparing the frequency of the divided signal obtained by dividing the output signal of the voltage controlled oscillator with the first phase. means for performing phase comparison with the input signal described above; and means for supplying a π/2 phase-shifted frequency-divided signal, which is phase-shifted by π/2 with respect to the frequency-divided signal, to the second phase comparator. means for performing phase comparison with the π/2 phase-shifted signal, and calculating (adding or subtracting) the output of the first phase comparator and the output of the second phase comparator to generate an error signal. , further comprising means for converting into an error voltage via a loop filter and supplying the error voltage to the voltage controlled oscillator.