JPH01121768A - Frequency difference detecting device - Google Patents

Abstract

PURPOSE:To evade the malfunction of a detecting device by providing a means which detects the phase difference between a signal to be measured which has a frequency relatively close to a reference clock signal and the reference clock signal, and detecting the phase difference reaching a prescribed value and deciding whether the frequency is high or low. CONSTITUTION:A frequency difference detecting circuit 1 uses a normal circuit and a reference clock signal generating circuit 2 consists of an oscillation circuit 2a and a N-notation counter 2b. This counter 2b uses a presettable counter and a value theta which is set in a register 3 is preset with the output signal leading edge of an OR gate 4. Consequently, the counter 2b starts coupling up at the preset value. Thus, the circuit 1 is made to correspond to a phase difference detecting means and a decision means, and the counter 2b, register 3 and OR gate 4 are allowed to correspond to a phase shifting means. Malfunction due to a slight phase difference between the reference clock signal and signal to be measured is evaded and the response speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a device for detecting a frequency difference between two signals.

(bl) Conventional technology Various devices are known for detecting the height of a frequency. One of them is to detect the phase difference between the signal under test and a reference clock signal, and gradually There is a method of detecting that the changing phase difference has reached a predetermined value and detecting the frequency of the signal under test relative to the reference clock signal.

FIG. 5 shows a circuit example of a frequency difference detection device according to the above method. This is the same ms person who has already applied and announced the special public interest in Showa 5.
This is the same as the first embodiment of No. 5-7188.

In FIG. 5, b is a flip-flop, and its inputs have a first signal a and a second signal port connected to differentiating circuits a and a, respectively.
' has been entered through. SL is a flip-flop b
This is a switch operated by the output Q of . When the switch S1 is turned on, the capacitor C1 is charged via the resistor R1. Therefore, S3 is a switch that is turned on instantaneously at the rising edge of the input signal A, and the monostable circuit b1 starts up at the rising edge of the input signal A. Actuates based on output signal. By turning on the switch S3, the voltage of C1 becomes 02
is applied to C1, and the charging voltage of C1 is maintained. S2 is a switch that is activated a very short time later than switch S3, and when switch S2 is turned on, the charge in C1 is discharged. bl' is a monostable circuit that generates a pulse with a very short delay in response to the signal from bl in order to activate S2.

C is a signal duration indicating pulse which actuates switch S4 and holds a voltage in capacitor C3. c and c' are differentiating circuits, and d and d' are waveform shaping circuits. Field effect transistor Q1 is connected to capacitor C3.
Since the differentiating circuit C1C' and the waveform shaping circuits d and d' are connected, detection signals are output from O and 0' in response to voltage fluctuations of the capacitors C2 and C3.

The waveforms of each part of the above circuit are shown in correspondence with (a) to (h) in FIG. Figure 5 shows the entire operation
The outline is as follows.

2 as shown in (a), (b), and (c) in Figure 6.
The phase difference between the two rectangular wave signals is converted into the duty of the rectangular wave, and the change in the duty is converted into a step wave via a triangular wave. The height of the two signals is detected by detecting the rise or fall of a certain level difference or more included in the step wave.

(C) Problems to be Solved by the Invention For example, in a tidal current meter, the received signal having a Doppler shift frequency that corresponds to the speed of the ship is an intermittent wave obtained from an ice block of a certain width in the sea or from the seabed. By detecting the height of the frequency between this received signal and the reference clock signal, and changing the frequency of the reference clock signal in a direction that reduces the difference in height, the reference clock signal when the frequency difference becomes 0 is The frequency of the received signal to be measured can be determined from the frequency.

However, the characteristics of the received signal are quite complex. For example, due to the spread (directivity angle) of the transmitted beam, a slight frequency difference occurs in the Doppler effect between the inside and outside of the beam, and the S/N changes depending on the strength of the received signal level. Furthermore, if the ship oscillates, beam deflection occurs, and the frequencies of the transmitted and received signals are always affected by the acceleration. All these factors will be observed as a superimposed signal.

The signals commonly measured in this way always have a certain bandwidth as long as they are ideal frequency signals, i.e., have only one spectrum, and include a frequency fluctuation element called jitter during the signal conversion process. . When comparing the frequency difference between the signal under test and the reference clock signal based on a slight difference, the difference becomes more uncertain as the jitter becomes larger.

FIG. 7 shows an example of the operation of the circuit shown in FIG. 5 when (a) is a reference clock signal and (b) is a signal under test including jitter. As shown in this example, when converting the phase difference between two signals into a duty signal, the direction in which the frequency difference detection pulse is generated is determined by a slight time difference between cent and reset of the flip-flop. Even if the jitter is not as large as shown in FIG. 7, when the phase difference between the two signals is very close, the effect of the jitter becomes noticeable. For example, as shown in FIG. A large number of frequency difference detection pulses may be generated in the vicinity where the phase differences of the two overlap. In Fig. 8, (a), (b), and (C) correspond to (f), (nu), and (l) in Fig. 6. In any case, the phase variation due to jitter is due to the frequency difference. When the difference in frequency is sufficiently smaller than the change in phase, there is no problem, but when the difference in frequency is small, there is a risk of malfunction.

An object of the present invention is to provide a frequency difference detection device that prevents malfunction of frequency difference detection even when two signals to be compared contain a certain amount of jitter. Means for Solving the Problem The frequency difference detection pulse of the present invention includes a phase difference detection means for detecting a phase difference between a signal under test and a reference clock signal for a signal under test whose frequency is relatively close to that of the reference clock signal; In a frequency difference detection device comprising a determination means for detecting that the phase difference has reached a predetermined value and determining whether the frequency is high or low with respect to a reference clock signal, when the determination means outputs a determination result, the reference clock signal The present invention is characterized in that a phase shift means is provided for shifting the phase of the signal to a phase different from the phase of the signal under test.

(e) Operation In the frequency difference detection device of the present invention, the phase difference detection means detects the phase difference between the signal under test and the reference clock signal, and the determination means detects that the phase difference has reached a predetermined value. to determine whether the frequency is high or low relative to the reference clock signal. This allows the frequency difference to be detected, but when the determination means outputs the determination result, the phase shift means
The phase of the reference clock signal is shifted to another phase different from the phase of the signal under test.

If the frequency is the same as that of the signal under test, the phase difference is constant, but if the frequencies are different, the phase difference changes over time in accordance with the frequency difference.

The determining means determines whether the frequency of the signal under test is higher or lower than the reference clock signal by detecting that this phase difference has reached a predetermined value. When the determination means outputs the determination result, the phase shift means shifts the phase of the reference clock signal to another phase different from the phase of the signal under test, thereby reducing the phase difference between the signal under test and the reference clock signal. It is possible to determine whether the frequency is high or low within a range that does not become 0. Therefore, even if the signal under test includes jitter, the rising or falling timings of the reference clock signal and the signal under test will not be reversed, and no malfunction will occur.

(f) Embodiment FIG. 1 is a block diagram of a frequency difference detection device which is an embodiment of the present invention.

In FIG. 1, a frequency difference detection circuit 1 is constructed from the conventional circuit shown in FIG. In the figure, 2 is a reference clock signal generation circuit, which includes an oscillation circuit 2a and an N-ary counter 2.
It is composed of b. This counter 2b is a preset counter, and the value θ set in the register 3 is preset by the rise of the output signal P of the OR gate 4. As a result, the counter 2b starts counting from the preset value.

In the above configuration, the frequency difference detection circuit 1 corresponds to the phase difference detection means and determination means according to the present invention, and the frequency difference detection circuit 1 corresponds to the phase difference detection means and determination means according to the present invention.
, the register 3 and the OR gate 4 correspond to the phase shift means according to the present invention. FIG. 2 is a diagram showing the waveforms of the main parts in the frequency difference detection circuit 1 shown in FIG.
Figures (a) and (b) correspond to (f) and (g) shown in Figure 6, and (C) and (d) in Figure 2 correspond to (h) and (su) shown in Figure 6. It corresponds to As is clear from these figures, when the phase of the signal under test matches the phase of the reference clock signal, the phase of the reference clock signal is summed by θ, thereby reducing the phase difference between the signal under test and the reference clock signal. The time required to reach the predetermined value is shortened. For example, θ
By setting the value to N/2, the phase change is accelerated by N/2 values, and the frequency difference detection response becomes
twice as fast. Note that the value of the threshold level Ls shown in (C) and (d) in FIG. 2 needs to be set to a value that does not detect the peak value of the differential waveform due to the phase shift of the reference clock signal.

Although the above embodiment was a hybrid circuit of an analog circuit and a digital circuit, an example of a frequency difference detection device using only a digital circuit will be described next. Figure 3 is its block diagram.
FIG. 4 shows the states and waveforms of the main parts of the block diagram.

In FIG. 3, 5 is a circuit that latches a predetermined upper bit of the preset counter 2b at the rising edge of the signal under test. Further, 6 is a decoder that decodes the value of the latch circuit 5 and generates a frequency difference detection pulse when the value exceeds a predetermined range.

Considering the case where the frequency difference detection range is divided into M equal parts from the range N values that the counter 2b can take, a latch circuit with a number of bits that can decode N7M values is required. For example, M
If =4, then 2iit is required from 22. Decoder 6 receives the output of launch circuit 5! given that! ≦(N/M) ・i and l≧N−((N/M) ・i) are decoded and outputted to terminals O° and O as frequency difference detection signals, respectively. Here, i is an integer (M-4
1=1).

If the frequency of the signal under test is equal to the frequency of the reference clock signal, the latch circuit 5 always latches the same value from the counter 2b. If the frequency of the signal under test is different from the frequency of the clock signal, the value latched by the launch circuit 5 increases or decreases depending on the frequency difference. The decoder 6 decodes the value of the latch circuit 5 to determine whether the frequency difference is high or low.

In FIG. 4, the upper waveform is the preset counter 2.
It shows the change in value when the value of b is latched by the latch circuit 5. (Here, M=4°i=1.) In this way, the value of the preset counter 2b is (1/4)N~(
Within the range of 3/4)N, the signal from the oscillation circuit 2a is counted as is, but when the output P of the OR gate 4 rises, that is, the value of the counter 2b becomes (3/4)N.
When it exceeds the value of (1/4)N or falls below the value of (1/4)N, the value of N/2 is preset in the counter 2b. After the counter 2b is preset, the next rising edge of the signal under test causes the latch circuit 5 to receive a value of approximately N/2 (the upper 2b
It) is latched, so the output 0.0' of the decoder 6 is not outputted, and a frequency difference detection pulse having a width W shown in FIG. 4 is generated.

According to the above device, even if the difference in wave number between the signal under test and the reference clock signal is small, malfunctions can be avoided and the detection speed can be further increased.

The frequency difference detection range (R1 and R2 in FIG. 4) can be set by the values of M and i, but expanding this range narrows the limit of the frequency band of the signal under test. Therefore, if the Doppler shift of the signal under test is small, the detection range can be widened to speed up the response, and conversely, if the signal under test has a wide band, the frequency difference detection range can be narrowed. .

(g) Effects of the Invention As described above, according to the present invention, the phase difference between the signal under test and the reference clock signal is detected, and the frequency is determined by detecting that the phase difference reaches a predetermined value. When the determination is made, the phase of the reference clock signal is shifted to another phase different from the phase of the signal under test, which prevents malfunctions due to small phase differences between the reference clock signal and the signal under test. be done. Additionally, as a result, the phase difference between the reference clock signal and the signal under test changes faster, and the frequency difference detection response speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frequency difference detection device according to an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms of main parts in the frequency difference detection circuit in FIG. 1. FIG. 3 is a block diagram of a frequency difference detection device according to another embodiment, and FIG. 4 is a diagram showing the states and waveforms of its main parts. FIG. 5 is a circuit diagram of a conventional frequency difference detection device, and FIGS. 6 to 8 are diagrams showing waveforms of the main parts thereof. 2b - Preset counter, 3 - Register, 4 - OR gate, 2b, 3.4 - Phase shift means.

Claims (1)

[Claims] (1) A phase difference detection means for detecting the phase difference between the signal under test and the reference clock signal, which has a frequency relatively close to that of the reference clock signal, and detecting when the phase difference reaches a predetermined value. In a frequency difference detection device comprising a determining means for detecting and determining whether the frequency is high or low with respect to a reference clock signal, when the determining means outputs a determination result, the phase of the reference clock signal is determined by another signal that is different from the phase of the signal under test. A frequency difference detection device comprising a phase shift means for shifting the phase.