JPH01119038A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01119038A JPH01119038A JP27473087A JP27473087A JPH01119038A JP H01119038 A JPH01119038 A JP H01119038A JP 27473087 A JP27473087 A JP 27473087A JP 27473087 A JP27473087 A JP 27473087A JP H01119038 A JPH01119038 A JP H01119038A
- Authority
- JP
- Japan
- Prior art keywords
- buried layer
- layer
- oxide film
- epitaxial
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 230000007547 defect Effects 0.000 abstract description 11
- 229910052785 arsenic Inorganic materials 0.000 abstract description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野]
本発明は半導体装置に関し、特に選択エピタキシャル成
長技術を用いて形成したエピタキシャル領域内に能動素
子を形成する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which active elements are formed in an epitaxial region formed using selective epitaxial growth technology.
従来、この種の半導体装置においては、成長させるエピ
タキシャル領域に高濃度埋込領域を必要とする場合には
、二〇埋込領域を囲むようにして開孔部を形成した上で
、この開孔内に選択エピタキシャル層を成長させる方法
がとられている。Conventionally, in this type of semiconductor device, when a high-concentration buried region is required in the epitaxial region to be grown, an opening is formed to surround the buried region, and then a hole is formed inside the opening. A method has been adopted in which selective epitaxial layers are grown.
例えば、第4図(a)乃至(C)はその−例を工程順に
示す断面図である。For example, FIGS. 4(a) to 4(C) are cross-sectional views showing an example of the method in the order of steps.
即ち、第4図(a)はシリコン基板1上に砒素の埋込層
2を形成し、950″Cの高圧酸化により酸化膜3を形
成した状態を示している。ここで、砒素埋込層2は濃度
10cm−’深さ1.5μmであるが、埋込層の無い所
で酸化膜が1.5μmになるように酸化を行うと、埋込
層上での酸化膜厚は1.75μmとなる。このとき、埋
込層上の酸化膜は周囲から約1350人盛り上がり、が
っ埋込層中に周囲より約1150人食い込んで段差が発
生される。That is, FIG. 4(a) shows a state in which an arsenic buried layer 2 is formed on a silicon substrate 1, and an oxide film 3 is formed by high-pressure oxidation at 950''C. 2 has a concentration of 10 cm and a depth of 1.5 μm, but if oxidation is performed so that the oxide film becomes 1.5 μm in a place where there is no buried layer, the oxide film thickness on the buried layer will be 1.75 μm. At this time, the oxide film on the buried layer rises by about 1,350 layers from the surroundings, and the oxide film digs into the buried layer by about 1,150 layers from the surroundings, creating a step.
次に、第4図(b)のように反応性イオンエツチング(
RIE)技術を用いて酸化膜3を選択エツチングし、埋
込領域2を囲む形で選択エピタキシャル層を形成するた
めの領域を開孔する。Next, as shown in Figure 4(b), reactive ion etching (
The oxide film 3 is selectively etched using the RIE technique to form a region surrounding the buried region 2 for forming a selective epitaxial layer.
次いで、露出したシリコン基板の表面を適切な方法で清
浄にした後、第4図(c)のように選択エピタキシャル
層4を成長する。この選択エピタキシャル成長は、シリ
コンと酸化シリコンの領域を有する基板にエピタキシャ
ル層を形成するとき、5iHn系のガスとH(lの流量
比を適切に選ぶことにより、酸化シリコン表面にはシリ
コン層を成長させないでシリコン表面だけシリコンのエ
ピタキシャル層を成長させようとする技術で、その代表
的な成長条件は、温度950°C2圧力50Torr。Next, after cleaning the exposed surface of the silicon substrate by an appropriate method, a selective epitaxial layer 4 is grown as shown in FIG. 4(c). This selective epitaxial growth prevents the growth of a silicon layer on the silicon oxide surface by appropriately selecting the flow rate ratio of 5iHn gas and H(l) when forming an epitaxial layer on a substrate having regions of silicon and silicon oxide. This is a technology that attempts to grow an epitaxial layer of silicon only on the silicon surface, and its typical growth conditions are at a temperature of 950°C and a pressure of 50 Torr.
S i HCl zの流量300SCCM T(Cf
fiの流量1l100SCC,H,の流量170SCM
である。成長速度は約0.1μm/winなので、15
分成長することにより、選択エピタキシャル層の表面と
酸化膜の表面を一致させることができる。S i HCl z flow rate 300SCCM T(Cf
fi flow rate 1l100SCC, H, flow rate 170SCM
It is. The growth rate is approximately 0.1 μm/win, so 15
By growing the selective epitaxial layer, the surface of the selective epitaxial layer and the surface of the oxide film can be made to coincide with each other.
しかしながら、上述した従来の構造では、シリコンエピ
タキシャル成長領域内に存在する砒素埋込層2の境界箇
所には酸化膜3の形成時に生じた1150人の段差があ
るため、選択エピタキシャル成長を行うと、第4図(C
)のように埋込層上のエピタキシャル表面に欠陥Xが生
じる。この欠陥によりエピタキシャル層に形成される素
子の特性不良が発生し、半導体装置の製造歩留りが低下
されるという問題がある。第6図はこの欠陥の発生の様
子を示す表面顕微鏡観察図である。However, in the conventional structure described above, there is a 1,150-layer step created during the formation of the oxide film 3 at the boundary of the arsenic buried layer 2 existing in the silicon epitaxial growth region. Figure (C
) A defect X occurs on the epitaxial surface on the buried layer. These defects cause defects in the characteristics of elements formed in the epitaxial layer, resulting in a problem in that the manufacturing yield of semiconductor devices is reduced. FIG. 6 is a surface microscopic observation diagram showing how this defect occurs.
本発明は欠陥を生じることな(エピタキシャル層を成長
することが可能な半導体装置を提供することを目的とし
ている。An object of the present invention is to provide a semiconductor device in which an epitaxial layer can be grown without causing defects.
本発明の半導体装置は、埋込層を形成した半導体基板の
表面に酸化膜を形成し、この酸化膜を埋込層上で開孔し
てこの開孔部内にエピタキシャル層を形成した半導体装
置において、前記開孔部を埋込層の領域内で開孔して前
記エピタキシャル層を成長させ、埋込層の段差によるエ
ピタキシャル層の欠陥発生を防止した構成としている。The semiconductor device of the present invention is a semiconductor device in which an oxide film is formed on the surface of a semiconductor substrate on which a buried layer is formed, a hole is formed in the oxide film on the buried layer, and an epitaxial layer is formed in the hole. The epitaxial layer is grown by forming the opening in the region of the buried layer, thereby preventing defects in the epitaxial layer due to steps in the buried layer.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の断面図であり、その製造方
法を第2図(a)及び(b)に示している。FIG. 1 is a cross-sectional view of one embodiment of the present invention, and the manufacturing method thereof is shown in FIGS. 2(a) and 2(b).
第1図に示すように、この半導体装置はシリコン基板l
に砒素埋込層2を形成し、この上にN型エピタキシャル
層4を成長しかつその周囲を酸化膜3で包囲した構成と
している。このエピタキシャル層4内には図外の素子が
形成される。また、ここではエピタキシャル層4は埋込
層2よりも平面寸法を小さくし、埋込層2の領域内にの
み成長されるように構成している。As shown in FIG. 1, this semiconductor device consists of a silicon substrate l
An arsenic buried layer 2 is formed thereon, an N-type epitaxial layer 4 is grown thereon, and an oxide film 3 surrounds it. Elements (not shown) are formed within this epitaxial layer 4. Further, here, the epitaxial layer 4 has a smaller planar dimension than the buried layer 2, and is configured to grow only within the region of the buried layer 2.
先ず、第2図(a)はシリコン基板1の表面に砒素埋込
層2を形成し、この埋込層上に1.75μmの酸化膜3
を形成した状態を示している。埋込層2の周辺に酸化膜
の食い込みによる1150人の段差がシリコン表面に見
られる。First, in FIG. 2(a), an arsenic buried layer 2 is formed on the surface of a silicon substrate 1, and an oxide film 3 of 1.75 μm is formed on this buried layer.
The figure shows the state in which it has been formed. Around the buried layer 2, 1150 steps are seen on the silicon surface due to the encroachment of the oxide film.
そして、この酸化膜3に対してRIE法により選択エツ
チングを行ってエピタキシャル成長のための開孔部を開
設するが、このとき開孔部は第2図(b)に示すように
、前記埋込層2よりも小さくなるようにする。換言すれ
ば埋込層2の領域内に開孔部が開設されるように選択エ
ツチングを行う。Then, this oxide film 3 is selectively etched by the RIE method to open an opening for epitaxial growth. Make it smaller than 2. In other words, selective etching is performed so that openings are created in the region of the buried layer 2.
しかる上で、この開孔部内に選択エピタキシャル成長を
行い、エピタキシャル層4を形成することにより、第1
図の構成が完成される。Then, selective epitaxial growth is performed in this opening to form an epitaxial layer 4, thereby forming the first layer.
The composition of the diagram is completed.
この構成によれば、埋込N2を形成したことにより酸化
膜3形成時に埋込層2に生じる段差がエピタキシャル層
4の領域内に入ることがない。このため、エピタキシャ
ル成長時に欠陥が生じることがな(、エピタキシャルN
4内に形成する素子の特性不良の発生を防止し、半導体
装置の歩留りを向上できる。According to this configuration, by forming the buried layer N2, a step formed in the buried layer 2 when the oxide film 3 is formed does not enter into the region of the epitaxial layer 4. Therefore, defects do not occur during epitaxial growth (epitaxial N
It is possible to prevent the occurrence of characteristic defects in elements formed in the semiconductor device 4 and improve the yield of semiconductor devices.
第3図は本発明を応用した例の縦断面図である。FIG. 3 is a longitudinal sectional view of an example to which the present invention is applied.
ここでは同一砒素埋込N2上に複数個のN型シリコン選
択エピタキシャルeIM4 a、4 b、〜4nを有す
る例を示しており、全ての選択エピタキシャル領域4a
、4b、〜4nが砒素埋込層2の領域内に位置するため
、各選択エピタキシャル層4a、4b、〜4nに欠陥が
発生することはない。Here, an example is shown in which a plurality of N-type silicon selective epitaxial regions eIM4a, 4b, ~4n are provided on the same arsenic-embedded N2, and all the selective epitaxial regions 4a
, 4b, .about.4n are located within the region of the arsenic buried layer 2, so that no defects occur in each selective epitaxial layer 4a, 4b, .about.4n.
第5図はこの例の表面顕微鏡観察図であり、欠陥が生じ
ていないことが判る。FIG. 5 is a surface microscopic observation of this example, and it can be seen that no defects have occurred.
なお、本発明は高濃度ボロン埋込層の上にP型選択エピ
タキシャル層を形成する構成においても同様に適用する
ことができる。Note that the present invention can be similarly applied to a structure in which a P-type selective epitaxial layer is formed on a high concentration boron buried layer.
〔発明の効果]
以上説明したように本発明は、半導体基板に形成した酸
化膜を埋込層の領域内で開孔してエピタキシャル層を形
成した構成としているので、選択エピタキシャル領域内
に埋込層の段差が存在することはなく、欠陥ないエピタ
キシャル層を形成して素子の特性不良を防止でき、かつ
半導体装置の製造歩留りを向上できるという効果がある
。[Effects of the Invention] As explained above, the present invention has a structure in which the epitaxial layer is formed by opening holes in the oxide film formed on the semiconductor substrate in the region of the buried layer. There is no layer step difference, and a defect-free epitaxial layer can be formed to prevent defective device characteristics, and the manufacturing yield of semiconductor devices can be improved.
第1図は本発明の半導体装置の一実施例の断面図、第2
図(a)及び(b)はその製造方法を工程順に示す断面
図、第3図は本発明の他の実施例の断面図、第4図(a
)乃至(C)は従来構造を製造工程順に示す断面図、第
5図は本発明の半導体装置の顕微鏡観察図、第6図は従
来の半導体装置の顕微鏡観察図であ之。
1・・・シリコン基板、2・・・埋込層、3・・・酸化
膜、4゜4a、4b、〜4n・・・エピタキシャル層。FIG. 1 is a sectional view of one embodiment of the semiconductor device of the present invention, and FIG.
Figures (a) and (b) are cross-sectional views showing the manufacturing method in order of steps, Figure 3 is a cross-sectional view of another embodiment of the present invention, and Figure 4 (a).
) to (C) are cross-sectional views showing the conventional structure in the order of manufacturing steps, FIG. 5 is a microscopic view of the semiconductor device of the present invention, and FIG. 6 is a microscopic view of the conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Buried layer, 3... Oxide film, 4°4a, 4b, -4n... Epitaxial layer.
Claims (1)
成し、この酸化膜を埋込層上で開孔してこの開孔部内に
エピタキシャル層を形成した半導体装置において、前記
開孔部を前記埋込層の領域内で開孔して前記エピタキシ
ャル層を成長させてなることを特徴とする半導体装置。(1) In a semiconductor device in which an oxide film is formed on the surface of a semiconductor substrate on which a buried layer is formed, a hole is formed in the oxide film on the buried layer, and an epitaxial layer is formed in the hole, the hole is 1. A semiconductor device, wherein the epitaxial layer is grown by forming a hole in a region of the buried layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62274730A JPH0712055B2 (en) | 1987-10-31 | 1987-10-31 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62274730A JPH0712055B2 (en) | 1987-10-31 | 1987-10-31 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01119038A true JPH01119038A (en) | 1989-05-11 |
JPH0712055B2 JPH0712055B2 (en) | 1995-02-08 |
Family
ID=17545776
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62274730A Expired - Lifetime JPH0712055B2 (en) | 1987-10-31 | 1987-10-31 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0712055B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5453396A (en) * | 1994-05-31 | 1995-09-26 | Micron Technology, Inc. | Sub-micron diffusion area isolation with SI-SEG for a DRAM array |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5115489A (en) * | 1974-07-29 | 1976-02-06 | Hitachi Ltd | |
JPS51112277A (en) * | 1975-03-28 | 1976-10-04 | Hitachi Ltd | Semiconductor device and its production method |
-
1987
- 1987-10-31 JP JP62274730A patent/JPH0712055B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5115489A (en) * | 1974-07-29 | 1976-02-06 | Hitachi Ltd | |
JPS51112277A (en) * | 1975-03-28 | 1976-10-04 | Hitachi Ltd | Semiconductor device and its production method |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5453396A (en) * | 1994-05-31 | 1995-09-26 | Micron Technology, Inc. | Sub-micron diffusion area isolation with SI-SEG for a DRAM array |
Also Published As
Publication number | Publication date |
---|---|
JPH0712055B2 (en) | 1995-02-08 |
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