JPH01118953A - Multi-processor system - Google Patents

Abstract

PURPOSE:To reduce the load of a host computer and to improve the overall processing performance of a multi-processor system by securing such a constitution where no need is required at the host side for retrieval of the processor numbers and user processes corresponding to the interruptions when the interruption signals are sent to the host computer from each processor. CONSTITUTION:Plural processors 1a-1n are connected to a host computer 3 via a network 2. When the users have the requests of interruptions to the computer 3 via their occupying processors 1a-1n while these processors are working, each requester processor can perform such processes needed for interruptions. That is, the message signals are transmitted to other processors used by the same user for wait, forcible stop, etc., or the user process number of the host side where the interruption is carried out is added to an interruption message to be sent to the computer 3. As a result, the load of the computer 3 is reduced and the overall system processing efficiency is improved.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a multiprocessor system consisting of a plurality of processors connected via a network and a host computer that controls these processors. Regarding.

(Prior Art) Due to the development of computer technology and the increasing demand for high-speed calculation, multiprocessor systems that perform processing using a large number of processors are being actively constructed.

These systems can perform processing at high speed by performing parallel processing using multiple processors. Furthermore, as such a system, there is a system in which a host computer controls a group of processors mainly responsible for calculations.

In such a system, the host computer is responsible for loading programs and initial data to each processor. At the same time, the host computer also needs to process interrupts such as input/output requests sent asynchronously from each processor.

When such a multiprocessor system is used by a plurality of users, a method is adopted in which a number of processors are assigned to each user. In this case, the host computer must perform a large number of processes such as processor management in response to requests from each user, loading of each user program and initial data, and processing of interrupt signals from the executing processor. In particular, for interrupts from each processor, first interpret the interrupt signal to determine the processor that requested the interrupt, then refer to a processor management table etc. to determine the user process currently using that processor. and interrupt that user process.
Furthermore, if necessary, it is necessary to perform very complicated and time-consuming processing such as sending a wait or forced stop signal to other processor groups used by the user.

For this reason, when multiple users execute user programs with many input/output requests, even though the speed of each individual processor is sufficient, the host computer cannot handle the interrupt requests from each processor, resulting in the entire system The disadvantage was that the processing performance was significantly reduced.

(Problems to be Solved by the Invention) As described above, in conventional multiprocessor systems, the processing performance of the entire system deteriorates due to the host computer being unable to handle the interrupt requests frequently issued by each processor. There was a problem.

The present invention was developed in consideration of these circumstances, and its purpose is to eliminate the need for the host to search for the processor number and user process corresponding to the interrupt when each processor sends an interrupt signal to the host computer. The object of the present invention is to provide a multiprocessor system that can reduce the burden on a host computer and improve the processing performance of the entire system.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides environment information storage means and message storage means described below for each of a plurality of processors that are interconnected via a network and controlled by a host computer. It is characterized by being provided with a sending means.

The environment information storage means stores information about the computer environment that controls itself on the host computer, that is, the number of the user process that controls it, and other processors that are used under the same process as the user process. (hereinafter referred to as "group processor") information such as the number is stored.

Further, the message sending means sends out a message related to the interrupt based on information stored in the environment information storage means in response to an interrupt request to the computer environment controlling the computer. Examples of the message include the user process number sent to the host computer, a standby or stop request signal sent to the group processor, and the like.

(Function) According to the present invention, since information regarding the computer environment that controls each processor on the host computer is provided on each processor side, when an interrupt request is generated from each processor, the conventional system The contents of the processing that the host computer had to perform in each case, that is, the contents related to interrupt processing, such as which user process should be interrupted, or whether it is necessary to issue a standby request or a stop request to a group processor, etc. The processors themselves can understand this information, and each processor sends necessary messages to the host computer and other processors accordingly.

For example, when an interrupt occurs on a certain processor to indicate that a breakpoint has been reached, the message sending means sends a stop request signal to all group processors, and at the same time informs the host computer of the user process number that should cause the interrupt. Send the attached message. Further, in the case of a normal input/output request, the message sending means does not send a message to the group processor, but similarly sends a message to the host computer with a user process number to be interrupted.

The above operations are performed by each processor itself and do not place any burden on the host computer. In this case, the interrupt processing on the host computer side requires exactly the same amount of effort as when supporting a normal multi-user environment.

As described above, according to the present invention, the processing burden that the host computer must perform in response to interrupt requests sent from each processor is significantly reduced, and as a result, the effective performance of the entire system is improved.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 is a diagram showing a schematic configuration of a multiprocessor system according to this embodiment. Multiple processors la, lb,
lc~in and the host computer 3 are each connected via a network 2. Here, the physical connection form of the network 2 may be of any type.

When this system is used by a plurality of users, each user exclusively uses several processors and performs parallel processing using these processors. For example, user A uses processor la.

User B has four processors: lb, lc, and ld (however, 1d is not shown), and user B uses processor le.

Third processors if and Ig (not shown) are used to perform their own processing. Next, four processors la, lb, l
The internal configuration of each processor and their operation will be explained by taking the case of user A who uses c and ld as an example.

FIG. 1 is a diagram showing the internal configuration of each processor 1a to 1d used by user A. Note that here processor 1a
Although only one processor is shown in the figure, the other processors 1b to 1d have a similar configuration.

The processor 1a has two registers as environment information storage means, namely a user register 20 and a group register 2.
1, and an interrupt diagnosis section 22 as a message sending means.
, a message transfer section 23, and a message generation section 24.

The user register 20 and group register 21 are set with data (information regarding the computer environment) necessary for loading programs and initial data from the host computer to each processor. That is, the user register 20 contains the process number of user A to be interrupted on the host computer.
The group register 21 also contains processor numbers (lb, lc in this case) of group processors used simultaneously by the same user (user A) as this processor 1a.

ld) is set. Note that the number of words in the group register 21 may be set as appropriate depending on the number of processors configuring the system and the usage pattern of the system.

The interrupt request asynchronously output from the processor 1a is
First, it is input to the interrupt diagnosis section 22, and its contents are analyzed. In general, interrupt factors output from the processor include input/output requests, breakpoint processing requests, and dev
There are various types of interrupts, such as hardware interrupts such as lde by zero, and communication requests with other processors, but a unique interrupt number is set for each factor, and this is added as header information before the interrupt message to interrupt the interrupt. Input to the diagnostic section 22. The interrupt diagnostic section 22 decodes this interrupt number, determines whether or not the interrupt requires message transfer to another processor, and sends a transfer request signal C to the message transfer section 23. For example, when interrupt numbers are set as shown in the following table, the interrupt diagnosis section 22 sends the transfer request signal C to the message transfer section 23 if the upper byte of the interrupt number is 1, and does not send it if it is 0. Since this interrupt diagnosis section 22 can be easily configured using several decoding circuits and gate circuits, the details thereof will be omitted here.

When the message transfer unit 23 receives the transfer request signal C from the interrupt diagnosis unit 22, it transfers necessary messages such as interruption and forced stop to each processor entered in the group register 21. Also, the interrupt diagnosis section 22
The interrupt message analyzed is then sent to the message generation section 24, which generates an interrupt message for the host computer. The message generating section 24 adds the process number to be interrupted held in the user register 20 to the received interrupt message, generates a message to the host, and transfers the message to the host computer.

A flowchart of the operations on each of the above processors is shown in FIG. In addition, in the figure, a module related to the operation is shown in parentheses.

That is, when loading a program and initial data from the host computer 3 (see (a) in the same figure), following the loading of the program and data (31), information regarding the computer environment is stored in the user register 20 and the group loop register 21. are set (32).

Next, when an interrupt occurs during execution, the process shown in FIG. 2(b) is performed.

For example, when an interrupt for a interrupt processing request occurs in the processor la (33), the interrupt diagnosis unit 22 analyzes the message (34), determines that it is necessary to transfer the message to the group register, and transfers the message (35). A request signal C is output (36). Message transfer section 2
When this transfer request signal C is input, 3 refers to the contents of the group register 21 and sends a forced stop signal to the group processors lb, lc, and ld that have entered (
37). At the same time, the message is sent to the message generator 2.
4, a message is generated to which the process number of user A to be interrupted, which is entered in the user register 20, is added. This message is transferred to the host computer and normal interrupt processing is performed (38).

Also, if this processor generates an input request interrupt (
In step 33), the interrupt diagnostic unit 22 determines that there is no need to transfer the message to the group register as a result of the message analysis (34), and does not output the transfer request signal C (35). Therefore, no messages are sent to other processors. Therefore, the message transmission from the processor is only to the host computer via the message generation unit 24 (38).

In either case, the message generator 2 sends the message to the host computer.
4 is sent, and information regarding the user process to be interrupted is added to the message, so there is no need for the host computer to search for or analyze the processor number, user number, process number, etc. At the same time,
Since message transfer to other processors is also performed by the processor that generated the interrupt, the burden on the host computer can be reduced.

Note that the present invention is not limited to the embodiments described above.

For example, in the above embodiment, a means for storing both a user process number and a group register number is shown as an environment information storage means, and a means for sending both a message to a host computer and a message to a group register is shown as a message sending means. Ta. However, if the environment information storage means is provided with a device that stores only the user process number, and the message sending device is provided with a device that sends the user process number from the host computer along with an interrupt request, or if the environment information storage device is provided with a group processor. To fully exhibit the effect of the present invention of reducing the burden on a host computer during interrupt processing even when only a number is stored and a message sending means is provided for sending messages such as a standby request or a stop request to a group processor. is possible.

Furthermore, if a signal line for an interrupt request signal that affects other processors and a signal line for an interrupt request signal that only needs to be sent to the host computer are provided independently within each processor, the interrupt diagnosis The section 22 can also be omitted.

[Effects of the Invention] As described above, according to the present invention, when a processor occupied by each user of a multiprocessor system requests an interrupt from the host computer during its operation, each requesting processor side On the host side, processing required for interrupts, such as autonomously sending message signals such as wait and forced stop to other processors used by the same user, and interrupting the host computer with interrupt messages. It is possible to do things such as adding a user process number.

These functions allow user management on the host computer side,
Operations such as processor management and sending messages to each processor are no longer necessary, and the burden on the host computer in system control can be significantly reduced, which can greatly contribute to improving the processing efficiency of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the internal configuration of each processor constituting a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a block diagram showing a schematic configuration of the multiprocessor system, and FIG. 3 is a block diagram showing each processor. 2 is a flowchart showing the above operation. la, lc, lc~1n...processor, 2...network, 3...host computer, 20...user register, 21...group register, 22...interrupt diagnosis unit, 23...・Message transfer section, 24...
Message generator. Applicant's agent Patent attorney Takehiko Suzue

Claims (4)

[Claims] (1) In a multiprocessor system consisting of a plurality of processors interconnected via a network and a host computer that controls these processors, each processor has a computer environment in which it controls itself on the host computer. environment information storage means for storing information related to the computer environment; and message sending means for sending out a message related to the interrupt based on the information stored in the environment information storage means in response to an interrupt request to the computer environment controlling the self. A multiprocessor system characterized by being equipped with. (2) The message sending means analyzes the interrupt request, and as a result, if it is necessary to send a message to another processor that is used in the same environment as the environment controlling the self, the message sending means analyzes the interrupt request. 2. The multiprocessor system according to claim 1, wherein a predetermined message is sent not only to the host computer but also to the other processors. (3) The environment information storage means stores a user process number controlling itself on the host computer as information regarding the computer environment, and the message sending means sends a message to the host computer about the user process. 3. The multiprocessor system according to claim 1, wherein the multiprocessor system transmits the number as a message. (4) The environment information storage means stores, as information regarding the computer environment, another processor number used in the same environment as the computer environment controlling itself on the host computer, and sends the message. Claim 1 or 2, characterized in that the means sends a standby or stop request signal as a message to other processors used in the same environment.
Multiprocessor system as described in Section.