JPH01115249A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To prevent a malfunction at the time of starting transmission without fail by providing a means to send a modulating signal after the lock of a PLL circuit is detected in the title transmitting device to switch the reference frequencies of the PLL according to 1 and 2 of data bits. CONSTITUTION:When digital transmission data SD are of an NRZ encoding system as shown in a figure, first, since a SD signal is set at the bit 0, the oscillating condition of FSK frequencies based on reference frequencies fr2 set at the time of starting the transmission is maintained. When the SD signal changes to 1 at the next bit, it is switched to the action of an oscillating circuit 1a, and reference frequencies fr1 are outputted to a phase comparator. In such a case, when a phase comparator 2 is locked, a lock detecting output 1 is inputted to an AND gate 16, further, when a delay time set beforehand from the supply of a request sending signal RS is expired, 1 is outputted from a delay circuit 17, and an FSK signal is made into a condition to be outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device that uses a PLL circuit to modulate digital data into an FSK signal that is a combination of two different frequency signals.

[Prior art] Conventionally, FSK using a prescaler type PLL circuit
As a modulation device, for example, the one shown in FIG. 3 is known.

In FIG. 3, the PLL circuit is composed of a reference oscillation frequency (frequency unit 1, a phase comparator 2, a low-pass filter 3, a voltage controlled oscillation unit 4, a prescaler 5, and a programmable counter 6). The division ratio of
/P and further, when the frequency division ratio of the program counter 6 is set to 1/N, the oscillation frequency fo of the voltage controlled oscillator 4 is controlled to fo=N-P-fr.

In order to modulate digital data into an FSK signal using such a prescaler type PLL circuit, the digital data is amplified by an amplifier 7, then converted to a DC voltage signal by a low-pass filter 8, and applied to the voltage controlled oscillator 4 as a control voltage. do.

That is, by applying the control voltage vh corresponding to bit "1" of the digital data to the voltage controlled oscillator 4, the oscillation frequency is shifted by a predetermined frequency +Δ[ with respect to the center frequency fo of the PLL locked state, while bit rOJ By applying the control voltage 1 corresponding to , the oscillation frequency is shifted by a predetermined frequency -Δf with respect to the center frequency. Therefore, F with different frequencies becomes (fo+Δf) for data bit “1” and (fo−Δf) for data bit rOJ.
The signal is modulated into an SK signal and sent to a transmission line such as a coaxial cable via an amplifier 9 and a bandpass filter 10.

However, in such conventional data transmission equipment,
There is no problem with modulating digital data in which the bit state constantly changes, such as in the Manchester code, but the NRZ coding system (non-return to z
, ero change at one), where one bit state continues for a long time, the frequency shifted by bit inversion returns to the original center frequency due to the feedback action of the PLL. FSK using PLL circuit
There was a problem in that it was not possible to modulate the signal.

In order to solve this problem, the inventors of the present invention have proposed a method of switching the division ratio of a programmable counter provided in the PLL circuit according to the data bit, or a method of providing two reference frequency oscillators in the PLL circuit to A method is proposed in which the W j% frequency for the phase comparator is switched accordingly.

According to these methods, even if one pin 1 state continues for a long time like a digital signal of NRZ encoding method, P
An oscillation control state with a frequency corresponding to the data bit is obtained by the LL lock operation, and digital data can be reliably modulated into an FSK signal.

[Problems to be Solved by the Invention] However, in the frequency division ratio switching method or the reference frequency switching method, when the data transmission device is started up and transmission is started, the FSK signal with a stable frequency is There is a time delay before this P is sent.
There are problems in that erroneous data may be transmitted due to the frequency signal sent before LL lock is reached, or that it may interfere with FSK transmission of other adjacent channels.

[Means for Solving the Problems] The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a data transmission device that reliably prevents malfunctions at the start of transmission. purpose.

In order to achieve this object, the present invention modulates digital data into an FSK signal consisting of a combination of different frequency signals by switching the reference frequency or frequency division ratio of the PLL circuit according to data bit 1.0. The data transmission device for output is provided with an output control circuit that sends out a modulated signal after detecting the frequency lock operation of the PLL circuit.

[Operation] According to the data transmission device of the present invention having such a configuration, when the data transmission start signal (request sent) is supplied to the data transmission device, the initialized data bits, e.g. The control operation of the PLL circuit is started by switching the reference frequency or frequency division ratio according to the data bit rOJ, and when the PLL circuit reaches a frequency lock operation in which the PLL circuit is in a stable frequency oscillation state, this lock operation is detected and output The control circuit creates an output state of the modulated signal to the transmission circuit, and the digital data given thereafter is FSK modulated and sent to the transmission line.

[Embodiment] FIG. 1 is a circuit block diagram showing an embodiment of the present invention. In this embodiment, FSK modulation is performed by switching the reference frequency of the PLL circuit according to the data bits. Take for example the case where

In FIG. 1, first, the PLL1 path includes two oscillation circuits 1a, 1b, which oscillate different reference frequencies Tri, fr2,
Phase comparator 2, low pass filter 3, voltage controlled oscillator 4
, a prescaler 5 and a programmable counter 6.

Here, if the reference frequency for the phase comparator 2 is fr, the frequency division ratio of the prescaler 5 is (1/P), and the frequency division ratio of the programmable counter 6 is (1/N>), then the output frequency from the voltage controlled oscillator 4 is fo is given by fo=NP-fr.

In the PLL circuit of this embodiment, there are two oscillation circuits 1a.
, 1b are provided, and the oscillation circuit 1a outputs the data bit "1".
” and outputs the reference frequency frl corresponding to the oscillation circuit 1.
b outputs the reference frequency fr2 corresponding to the data bit rOJ (however, frl>fr2).

Therefore, when the oscillation circuit 1a is activated by the data bit "1" and the reference frequency fr1 is applied to the phase comparator 2, the voltage is controlled by the PLL feedback operation! The output frequency f, fO of one oscillation 4 is fo=f1 =NP-
It becomes frl. On the other hand, after the data bit rOJ, the oscillation circuit 1b is activated and the reference frequency fr is output to the phase comparator 2.
2, and due to the PLL feedback operation at this time, the output frequency fO of the voltage controlled oscillator 4 becomes fO=f2=NP-fr2.

That is, by switching the reference frequencies frl and fr2 according to data bits r1J rOJ, the PLL circuit outputs an FSK signal consisting of a combination of output frequencies f1 and f2.

Switching control between the oscillation circuits 1a and 1b is performed by a circuit section consisting of an inverter 11, a changeover switch 12, and an inverter 13. That is, the digital transmission data S is sent to the inverter 11.
When D is applied and the data bit is 11, bit “1” is applied to the oscillation circuit 1a via the inverter 11, changeover switch 12 and inverter 13, the oscillation circuit 1a operates, and the reference frequency frl is set. Output. On the other hand, when the data pit is "0", a bit "1" is applied to the oscillation circuit 1b via the inverter 11 and the changeover switch 12, and the oscillation circuit 1b operates to output the reference frequency "r2".

The changeover switch 12 is used to switch between the output of the inverter 11 and the output of the inverter 14, which is an inverted version of the output of the inverter 11. As shown by the dotted line, when switching to the output of the inverter 14, data bit "1" causes the oscillation circuit to switch. 1b
operates, and the oscillation circuit 1a comes to operate with the data bit rOJ, making it possible to change the frequency of the FSK signal corresponding to the data bit.

The FSK signal oscillated by such a PLL circuit, ie, the output of the voltage controlled oscillator 4, is sent via amplifiers 9a, 9b and a bandpass filter 10 to a transmission line using a coaxial cable of a CATV system, for example.

On the other hand, in order to prevent sending out an unstable frequency signal at the start of FSK signal transmission, inverter 15 and AND gate 1
6 and a delay circuit 17 is provided.

That is, a request sent signal R3 for starting data transmission is inputted to the inverter 15 from an appropriate data processing device, and a request sent signal R8 is input to the bit r.
OJ becomes a transmission start command. AND gate 16 is 3
It is a human-powered AND gate, and the request send signal @R8 inverted by the inverter 15 is input, and the PL
A detection signal of frequency lock operation in the phase comparator 2 of the L circuit is input. Furthermore, an inverted signal of the R3 signal delayed by a delay circuit 17 for a predetermined time is applied to the AND gate 16. Here, the delay time of the delay circuit 17 is set to be longer than the time required for frequency locking operation in the PLL circuit, for example, 20 m5.

The output of the AND gate 16 is given to the amplifier 9b provided at the output stage of the PLL circuit, and the output of the AND gate 16 becomes "1".
”, the amplifier 9b becomes operational and the FSK
A condition is created where the signal exits the transmission line. Furthermore, the R3 signal inverted by the inverter 15 is directly input to the amplifier 9a provided before the amplifier 9b.
The amplifier 9a becomes operational when transmission is started by the R3 signal.

Furthermore, the output of the AND gate 16 is inverted by an inverter 18 and output as a clear send signal C8 for starting one transmission of digital transmission data to an external data processing device.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, prior to the start of data transmission, a request sent signal @R8 is given as "O" from an external data processing device to the data transmission device shown in FIG. 1 to instruct the data transmission device to start transmission. At this time, the digital transmission data SD to the inverter 11 is in the state of bit rOJ.

The request send signal R3, which has been inverted to "1" by the inverter 15, is supplied to the voltage control excavator 4 of the PLL circuit, so that the voltage control excavator 4 enters the operating state, while the digital transmission data to the inverter 11 Since SD is at bit rOJ, the oscillation circuit 1b is activated and outputs the reference frequency f'r2 to the phase comparator 2.

The control operation of the PLL circuit is started by the operation of the voltage controlled oscillator 4 and the output of the reference frequency fr2 to the phase comparator 2, and the output frequency fO of the voltage controlled excavator 4 is set so that fo = f2 = NxPxf r2. After a predetermined feedback control delay time, a frequency lock state is reached in which the output frequency is fixed at fo = fl.

When the PLL circuit shifts to the frequency f2 lock state in this manner, the frequency lock operation detection output "1" from the phase comparator 2 is input to the AND gate 16. Furthermore, when a preset delay time has elapsed since the request sent signal R3 was supplied, the output of the delay circuit 17 becomes "1". As a result, all the inputs of the AND gate 16 become "1", so that the output rises to "1", putting the amplifier 9b into the operating state and establishing a state in which the PLL circuit can output the FSK signal. At the same time, the output of the AND gate 16 is inverted by the inverter 18 and notified to the data processing device as a clear send signal O8, and the data processing device receiving this clear send signal C8 sends the digital transmission data S
Start sending D.

If the digital transmission data SD supplied at this time is, for example, data based on the NRZ encoding method as shown in Figure 4, the SD low signal bit is initially in "O", so the standard set at the start of transmission is Based on the frequency fr2, the excavation state of <FSK frequency f2 is maintained, and when the next bit changes to the SD double signal bit "1", the oscillation circuit 1
Switch to operation a, output the reference frequency frl to the phase comparator, and set the output frequency fO of the voltage control excavator 4 as fO=
A PLL feedback operation is performed so that f1=N-P-frl, and the state is switched to the transmission state of frequency f1. Thereafter, by switching the reference frequencies frl and fr2 according to the SD double signal data bits, an FSK signal consisting of a combination of different frequencies 1fl and f2 is sent to the transmission line.

FIG. 2 is a circuit block diagram showing another embodiment of the present invention. In this embodiment, the frequency division ratio ( 1/N).

That is, the frequency division value switching circuit 20 is provided for the programmable counter 6 of the PLL circuit, and the frequency division value switching circuit 20
has two frequencies f1 and f of the FSK signal that is modulated and output.
The frequency division value Nl corresponding to 2.

N2 is set in advance, for example, the data bit "1" of the digital transmission data SD obtained via the amplifier 7 sets the frequency division value N1 in the programmable counter 6, and the frequency division value N2 is set in the programmable counter 6 with the data bit rOJ. Set to 6. For such settings of frequency division values Nl and N2, the excavation frequency fo for the PLL circuit is controlled so that fO=fl=N1-P-fr fO=f2=N2-P-fr, and 2 depending on
It is possible to modulate and output an FSK signal consisting of a combination of two frequencies. Note that the reference frequency fr for the phase comparator 2
Since is fixed, only one oscillation circuit 1 is provided.

P that switches the frequency division value N according to such data bits.
For the LL circuit, an output control circuit consisting of an inverter 15, an AND gate 16, and a delay circuit 17 is provided, similar to the embodiment shown in FIG. 1, in order to prevent the output of an erroneous frequency signal at the start of transmission. .

As a result, even in the data transmission device using the PLL circuit that switches the frequency division value according to the data bit in the embodiment shown in FIG. Since the operation of the amplifier 9b is stopped when the cent signal R3 is applied, the transmission of the frequency output is prohibited until the frequency lock operation of the PLL circuit is detected, and the phase comparator 2 outputs the detection output of the frequency lock operation. is obtained and the delayed output of the delay circuit 17 is obtained, the amplifier 9b becomes operational. That is, after the PLL circuit shifts to a locked state in which it outputs a stable frequency signal, the clear send signal C8 is sent to the data processing device;
Transmission of the FSK signal is started upon receiving the input of the digital transmission data SD.

In the embodiments shown in Figs. 1 and 2, a modulation method is used as an example in which the reference frequency or frequency division value is switched depending on the data bit, but the modulation method for switching the frequency when the data bit changes is used as an example. In order to prevent a rise delay due to the PLL feedback operation time, the digital transmission signal is converted to a DC voltage signal by a bypass filter and directly connected to the voltage controlled oscillator 4.
The rising response may be accelerated by applying a control voltage to. This makes it possible to achieve faster FSK modulation.

[Effects of the Invention] As described above, according to the present invention, digital data is converted into a reference frequency of a PLL circuit according to data bit 1.0, or an FSK signal consisting of a combination of different frequency signals by switching the frequency division ratio. In a data transmission device that modulates and outputs a signal, an output control circuit that sends out a modulated signal after detecting the frequency lock operation of the PLL circuit is installed, so the PLL circuit can output a stable frequency from the start of transmission. It is possible to prohibit the transmission of frequency signals to the transmission line until a frequency lock state is reached, which reliably prevents erroneous data transmission due to the transmission of unstable frequency signals or interference with FSK transmission of adjacent channels. Highly reliable F
SK modulation data can be transmitted.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram showing one embodiment of the present invention, Fig. 2 is a circuit block diagram showing another embodiment of the invention, Fig. 3 is a circuit block diagram showing a conventional example, and Fig. 4 is a circuit block diagram showing an embodiment of the present invention. The figure is NRZ
It is an explanatory diagram of a signal. 1, la, 1b: Oscillator circuit (for reference frequency) 2: Phase comparator 3: Low-pass filter 4: Voltage-controlled oscillator 5; Prescaler 6: Programmable counter 7.9: Amplifier 10: Band-pass filter 11.13, 15 , 18: Inverter 12: Changeover switch 16: AND gate 17: Delay circuit 20: Frequency division value switching circuit

Claims (1)

[Claims] In a data transmission device that modulates and outputs digital data into an FSK signal consisting of a combination of different frequency signals by switching the reference frequency or division ratio of the PLL circuit according to data bits 1 and 0, the PLL circuit A data transmission device comprising an output control circuit that sends out a modulated signal after detecting a frequency lock operation.