JPH01114173A - Output circuit for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To synthesize an output signal of a horizontal register while eliminating noise by providing a clamp circuit and a delay circuit to each of N-set of horizontal register sections, mixing output signals of the delay circuit nonadditively and outputting the result. CONSTITUTION:Each pickup output signal obtained from horizontal registers 4a-4d is a signal varying for each transfer period T comprising a precharge period Tp, a reference potential period To and a transfer period Tt. Each pickup output signal is given to clamp circuits 11a-11d and a level of a reference level part of each period To is clamped to a prescribed level. The output of the circuit 11a is fed to a nonadditive mixer 19 without any modification and outputs from the circuits 11b-11d are given to delay circuits 16-18 respectively and retarded by T/4, T/2, 3T/4 and the result is fed to the mixer 19. The mixer 19 outputs selectively the lowest level in the input signal. Thus, the output signal of the mixer 19 is a synthesis video signal including the signal of four horizontal registers for each period T.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit of a solid-state imaging device having a plurality of horizontal reading registers.

[Summary of the invention]

The present invention includes a plurality of light receiving elements arranged in a matrix, a plurality of vertical register sections that transfer signal charges accumulated in the light receiving elements, and a plurality of vertical register sections that are controlled by a common transfer clock. selectively receive the output,
In an output circuit of a solid-state imaging device having N horizontal register sections (N is an integer of 2 or more) adapted for reading, a clamp circuit for clamping a reference level section of an output signal in each of the N horizontal register sections; , N extending delay circuits are provided, and the output signals of the delay circuits are non-additively mixed and output, so that noise is removed with a simple circuit configuration, and aliasing due to high-frequency thermal noise does not occur. , further N
The outputs of horizontal registers can be combined.

[Prior art] Charge-coupled device (C
Solid-state imaging devices composed of charge transfer devices such as CDs are
For example, an interline transfer method includes a light receiving section that performs a photoelectric conversion function, a charge transfer section that transfers signal charges obtained by the light receiving section, and an output section that extracts an output signal based on the transferred signal charges. In the case of , the signal charge of each light-receiving cell is transferred to the light-shielded vertical register through the transfer gate, and then the signal charge is sequentially sent from the vertical register to the light-shielded horizontal register, which is connected to the horizontal register. An imaging signal is extracted by a signal extraction circuit.

A conventional signal extraction circuit has a configuration shown in FIG. In FIG. 6, 41 indicates a horizontal register;
For example, a two-phase clock pulse φ is applied to the horizontal register 41, where 3 indicates a horizontal output gate, from terminals 42A and 42B.
, and φ2 are supplied. A bias voltage at a predetermined level is supplied to the horizontal output gate 43 from a terminal 44 . A field effect transistor 46 constituting a floating diffuse amplifier is inserted between the drain and source between the horizontal output gate 43 and the power supply terminal 45, and a capacitor 48 is equivalently connected between the horizontal output gate 43 and the ground. It is formed. A terminal 47 connected to the gate of the field effect transistor 46 supplies a precharge pulse PP synchronized with the transfer clock φ and φ2. The imaging output signal taken out to the connection point between the source of the field effect transistor 46 and the capacitor 48 is transmitted to a two-stage source follower circuit composed of field effect transistors 49 and 50, respectively, and an emitter 5. The signal is taken out to the output terminal 52 via the Ta follower circuit.

7th rj! J shows the relationship between the two-phase transfer clocks φ1 and φ2, the precharge pulse Pp, and the output voltage Vo generated at one end of the capacitor 48. (φ1:
High level, φ! During the precharge period Tp in which the precharge pulse PP is supplied to the gate of the field effect transistor 46 in the state (low level), the field effect transistor 46 is turned on. When field effect transistor 46 is turned on, capacitor 48 is connected to terminal 4.
It is instantly charged by the power supply voltage vb applied to 5.

At the same time, the precharge pulse Pp supplied to the gate of the field effect transistor 46 appears on the source side through the parasitic capacitance substantially formed between the gate and source of the field effect transistor 46. Therefore, at one end of the capacitor 48, an output voltage ■0 is generated, which is the power supply voltage vb and the voltage Vp of the precharge pulse Pp superimposed.

After the precharge period Tp has passed, the reference potential period To begins immediately before the charge is transferred from the horizontal register 41 to the signal extraction circuit. During this reference potential period To, the precharge pulse Pp is at a low level, so the field effect transistor 46 is in an off state. Therefore, the output voltage Vo at one end of the capacitor 48 is during the precharge period Tp
Compared to , the voltage Vp of the precharge pulse Pp is lowered to the power supply voltage (reference level) b.

After the reference potential period TO has passed, (φ1: low level, φ
t: high level) is the transfer period Tt.

During this transfer period Tt, the output voltage Vo of the information signal voltage Vsn corresponds to the signal charge transferred from the horizontal register 41.
is obtained.

As described above, when the output voltage Vo is taken out, in the precharge period Tp, the floating diffusion region and the precharge drain region are formed in the region between the source and drain of the field effect transistor 46 (precharge gate region l region). As a result, the potential of the floating diffusion region is stabilized. Therefore, the charge state immediately before the precharge gate region is turned off is not constant, and therefore, when the precharge gate region is turned off, the reset noise component Δn is generated in the floating diffusion region. is included. Due to this reset noise component Δn, the reference potential (feedthrough level) in the reference potential period To differs between each transfer period. As a result, when signal charges are transferred during the transfer period Tt, reset noise Δn is also included in the signal charges.

In addition to this reset noise, there are so-called 1/f noise and thermal noise generated in the source follower stage (field effect transistor 49,50). With 1/f noise, the noise level increases inversely with frequency. Thermal noise is high-frequency white noise.

In order to remove these noises, for example,
As described in Japanese Patent No. 116374, correlated double sampling processing is applied to the imaging output signal taken out from the solid-state imaging device to produce an output image in which the influence of level fluctuations in the reference level portion of the imaging output signal is compensated for. It is proposed to obtain a signal.

FIG. 8 shows the output circuit shown in the above publication.
In the figure, the imaging output signal SV shown in FIG. 9A is supplied to an input terminal indicated by 61, and this imaging output signal Sv is supplied to sample and hold circuits 62 and 63, respectively.

The sample and hold circuit 62 samples and holds the imaging output signal Sv based on the sampling pulse SP shown in FIG. 9B supplied from the terminal 64. The sampling pulse SP has a phase corresponding to the reference level portion obtained in the reference potential period TO in the imaging output signal S■, and therefore, from the sample hold circuit 62, the level of the reference level portion within each transfer cycle is A matching output signal is obtained. The output signal of this sample and hold circuit 62 is supplied to a sample and hold circuit 65.

In the sample hold circuit 63, the sampling pulse S P z shown in FIG.
A sample and hold operation is performed based on. The sampling pulse SP2 has a phase corresponding to the information signal portion obtained during the transfer period Tt in the imaging output signal SV, and therefore, the sample and hold circuit 63 outputs an output that matches the level of the information signal portion within each transfer period. I get a signal.

The output signal of this sample hold circuit 63 is the subtraction circuit 6
7. Further, in the sample hold circuit 65, the output signal of the sample hold circuit 62 is sampled and held based on the sampling pulse SPg, and the output signal of the sample hold/do circuit 65 is held in the subtraction circuit 6.
7.

In the subtraction circuit 67, a process of subtracting the output signal of the sample and hold circuit 65 from the output signal of the sample and hold circuit 63 is performed. Therefore, at the output terminal 68 provided at the output end of the subtraction circuit 67, an output video signal is obtained from which level fluctuations caused by level fluctuations in the reference level portion of the imaging output signal Sv have been removed.

Further, as described in U.S. Pat. No. 3,781,574, the reference level section is clamped to a predetermined potential, and then the clamped imaging output signal is supplied to a sample and hold circuit to sample the level of the information signal section. A hold configuration has also been proposed.

[Problem that the invention seeks to solve]

These conventional output circuits of solid-state image sensors are effective in removing the above-mentioned reset noise and (1/f) noise. However, since both sample and hold high-frequency components above the Nyquist frequency, the S/N deteriorates due to aliasing of high-frequency noise (thermal noise components).
occurs.

Furthermore, in a high-definition television type color camera, since the number of pixels is large, a plurality of horizontal registers for reading are provided, and a floating diffusigon amplifier is provided on the output side of each horizontal register. For these multiple floating diffusion amplifiers,
Providing a correlated double sampling circuit for each circuit would complicate the circuit configuration, which is not preferable.

Therefore, another object of the present invention is to provide an output of a solid-state imaging device that can remove noise components from the outputs of a plurality of horizontal registers and combine the output signals of the plurality of horizontal registers with a simple circuit configuration. The purpose is to provide circuits.

[Means for solving problems]

In this invention, a plurality of light receiving elements arranged in a matrix, a plurality of vertical register sections for transferring signal charges accumulated in the light receiving elements, and a plurality of vertical register sections are controlled by a common transfer clock. In an output circuit of a solid-state imaging device that has N horizontal register sections (N is an integer of 2 or more) configured to selectively receive and read out outputs, each of the N horizontal register sections has a standard for output signals. A clamp circuit for clamping the level portion and N delay circuits extending thereto are provided, and the output signals of the delay circuits are non-additively mixed and output.

[Effect]

Each imaging output signal obtained from the N horizontal registers has a precharge period Tp and a reference potential period T.

This is a signal that changes every one transfer period T consisting of a transfer period Tt and a transfer period Tt. Each imaging output signal is processed by a clamp circuit.
The level of the reference level portion of each reference potential period T6 is clamped to a predetermined level. These clamp circuits remove random noise such as reset noise.

When each output signal of the clamp circuit is (N-4), it is delayed by 0° (T/4), (T/2), and (3T/4) before being supplied to the non-adding mixer. The non-additive mixer selectively outputs the lowest level portion of the input signal. Therefore, the output signal of the non-additive mixer becomes a composite image signal that includes the output signals of four horizontal registers for each transfer period T. In this way, with a simple circuit configuration, random noise such as reset noise can be removed, and signals of N channels can be combined.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, an interline transfer type solid-state imaging device having a plurality of, for example, four horizontal registers 4a, 4b, 4c, and 4d as shown in FIG. 2 is used. In FIG. 2, reference numeral 1 indicates, for example, a P-type silicon substrate, and on the surface of the P-type silicon substrate 1, light receiving elements 2a, 2b, 2c, . . . consisting of photodiodes are arranged in a matrix. Although simplified in FIG. 2, the light receiving elements 2a, 2b, 2c, etc. are (2000
1000) are arranged in a matrix. Also, the vertical register 3a is shielded from light in close proximity to the light receiving elements 2a, 2b, 2c, .

3b, 3c... are provided. Vertical register 3a
, 3b, 3c, . . . and four horizontal registers 4a, 4b, 4c, 4d are provided.

Every fourth vertical register 3a, 3b, 3c, . . . is selectively connected to horizontal registers 4a, 4b, 4c, 4d. Vertical registers 3a, 3b.

3C... are provided for the sake of simplicity, the first vertical register 3a and the fifth vertical register 3e are connected to the horizontal register 4a, and the second vertical register 3b and The sixth vertical register 3f is connected to the horizontal register 4b, the vertical registers 3C and 3g are connected to the horizontal register 4C, and the vertical registers 3d and 3h are connected to the horizontal register 4d. During the vertical blanking period, by gate pulse φSV,
From the light receiving elements 2a, 2b, 2c... to the vertical register 3a
, 3b, 3c, . . . signal charges are read out. This signal charge is generated by four-phase clocks φV1, φV2 . φV3
．． Vertical registers 3a, 3b, 3c・
. . are transferred and read out to the horizontal registers 4a, 4b, 4c, 4d during the horizontal blanking period. Two-phase transfer clocks φH1 and φH2 are supplied to the horizontal registers 4a, 4b, 4c, and 4d, and signal charges in the horizontal registers 4a, 4b, 4c, and 4d are read out during the horizontal video period.

The signal charges taken out from the horizontal registers 4a, 4b, 4c, 4d are supplied to output amplifiers 5a, 5b, 5c, 5d, and output terminals 6a, 6b, 6c, 6c, as video signal voltages.
It is taken out on 6d. Output amplifiers 5a, 5b, 5c, 5
d is composed of, for example, a floating differential amplifier and a source follower transistor.

FIG. 3A schematically shows the signal voltage taken out to the output terminal 6a, and FIG. 3B, FIG. is schematically shown.

Corresponding to the signal charges of the light receiving elements 2a to 2h in FIG. 2, signal voltages S2a and S2e corresponding to the light receiving elements 2a and 2e, respectively, are taken out to the output terminal 6a. Similarly, signal voltages S2b and 32f corresponding to the light receiving elements 2b and 2f are output to the output terminal 6b, and signal voltages S2c and 32f corresponding to the light receiving elements 2C and 2g are output to the output terminal 6C.
32g is taken out, and the light receiving element 2d is connected to the output terminal 6d.
and 2h and corresponding signal voltages S2d and S2h are extracted. The output signals of these horizontal registers 4a, 4b, 4c, and 4d are combined by a non-adding mixer, as will be described later, to obtain a video output signal as shown in FIG. 3.

As understood from the above description, by providing N horizontal output registers, the transfer frequency of signal charges in the horizontal registers becomes 1/N.

Therefore, even if the number of picture elements is large, such as in a color camera for high-definition television, the readout of the signal charge is only 1.
This is easier than using a book horizontal register.

An embodiment of the present invention will be described in further detail with reference to FIG. As described above, the output terminals 6a, 6b of the solid-state imaging device have four horizontal registers.

5c, 5d, amplifier 10a, variable gain amplifier 1
0b, a variable gain amplifier 10c, and a variable gain amplifier 10d are connected, respectively. Variable gain amplifier 10b, 10c, 10
d, as described later, are output amplifiers 5a, 5b, 5c,
This is provided in order to compensate for variations in gain caused by differences in capacitance between the respective floating diffusion regions of 5d.

The output signal SvO of the amplifier 10a is supplied to a clamp circuit ILa surrounded by a broken line. The clamp circuit 11a is
It consists of a capacitor 12 inserted in series with the signal path, a switching element 13 inserted between one end of the capacitor 12 and ground, and a fixed voltage source 14a for generating a clamp voltage. Variable gain amplifier 10b
, 10e, and 10d are supplied to clamp circuits 11b, llc, and lfd, respectively, which are shown surrounded by broken lines.

These clamp circuits 11b, llc, and lid, like the clamp circuit 11a, are configured by a capacitor 12, a switching element 13, and variable voltage sources 14b, 14c, and 14d. Variable voltage sources 14b, 14c, 14d
is provided to correct variations in black level, as will be described later. The switching elements 13 of the clamp circuits 11a-lid are controlled by a clamp pulse Pc from a terminal 15.

The output signal SVI of the clamp circuit 11a is output from the non-addition mixer 1.
9. The output signal of the clamp circuit llb is supplied to the delay circuit 16, and the output signal SV2 of the delay circuit 16 is supplied to the non-addition mixer 19. The output signal of the clamp circuit 11c is supplied to the delay circuit 17, and the output signal SV3 of the delay circuit 17 is supplied to the non-addition mixer 19. The output signal of the clamp circuit lid is supplied to the delay circuit 18, and the output signal SV4 of the delay circuit 18 is supplied to the non-adding mixer 19.

The delay circuit 16 has a delay amount of (T/4), where T is the transfer period of the information signal voltage in the output signal obtained from one horizontal register of the solid-state imaging device. Delay circuit 1
The delay time of the non-adding mixer 1 is (T/2), and the delay time of the delay circuit 18 is (3T/4).
9 are four input signals SV1. SV2. SV3 and 5V
4(7), outputs the minimum level. As the non-summing mixer 19, for example, the emitters of four PNP transistors are commonly connected to a constant current source, and
It is possible to use a structure in which the collectors are commonly connected and the output is taken out from a common emitter contact point. A composite information signal SV5 from the non-adding mixer 19 is taken out to an output terminal 21 via an amplifier 20.

Floating diffusion amplifier 5a.

When the precharge pulse PP shown in FIG. 4A is supplied to 5b, 5c, and 5d, the output signal S20 of the floating diffusion amplifier 5a becomes as shown in FIG. 4, for example. That is, this output signal is one of the transfer clocks φH1 and φH2 supplied to the horizontal register 4a.
Within the period (T), the precharge period Tp and the reference potential period T
o and the transfer period Tt, respectively.

Precharge pulse Pp and transfer clock φH1゜φH2
The respective periods Tp, To, and Tt are defined by the level relationship with .

During the precharge period Tp, the field effect transistor constituting the floating diffusion amplifier is turned on, and the level of the output signal becomes the sum of the reference potential and the voltage of the precharge pulse pp. In the next reference potential period To, the bridge pulse Pp becomes low level, and the field effect transistor is turned off. The level of the output signal at this time becomes the reference level. Furthermore, the transfer period T
At time t, the signal charge is transferred from the horizontal register 4a to the floating diffuse region, and the level of the output signal becomes the information signal voltage Sal.

Since the charge state of the field effect transistor of the floating diffusion amplifier immediately before it changes from the on state to the off state is not constant, the reference level during the reference potential period To does not match the reference voltage, and the This results in a difference in reset noise Δ7. Δ7゜1
... occurs.

The clamp pulse Pc supplied to the clamp circuits 11a to lid is at a high level within each reference potential period TO, as shown in the fourth [ilC], and when the clamp pulse Pc is at a high level, the switching element 13 is turned on. Ru. The level (feedthrough level) in the reference potential period To is clamped to the clamp voltage by this clamp circuit 11a. Therefore, as shown in the fourth diagram, the output signal SVI of the clamp circuit 11a is affected by the reset noise Δ7
, Δ73. ．． ... has been removed.

The above-described reset noise removal operation is also performed by the other clamp circuits 11b, IIC, and lid. The output signal of the clamp circuit 11b is passed through the delay circuit 16, so as shown in FIG. 4, it becomes a signal SV2 with a time delay of (T/4) with respect to the signal S1. .

The output signal of the clamp circuit 11c is passed through the delay circuit F, and becomes the signal SVI as shown in FIG. 4F.
In contrast, the signal Sv3 has a time delay of (T/2). The output signal of the clamp circuit 11d is sent to the delay circuit 18.
As shown in FIG. 4G, the signal S with a time delay of (3T/4) with respect to the signal SVI is
It is considered to be V4.

These imaging output signals SVI, SV2. SV3 and SV
4 is supplied to the non-adding mixer 19, the output signal SV5 of the non-adding mixer 19 has the large amplitude portion of the precharge period Tp removed, as shown in FIG.
The information signal voltages Sal, Sb1 . Scl
, Sdl, . . . become a continuous signal. Therefore, by the non-adding mixer 19, the four horizontal registers 4a, 4b
, 4c, and 4d are combined into one channel of imaging signals.

Sample and hold circuits 23a, 23b, and 23c are connected via a switch 22 to an output terminal of an amplifier 20 to which the output signal of the above-mentioned non-adding mixer 19 is supplied.

23d is connected. These sample and hold circuits 23a to 23d receive sampling pulses φa and φb.
, φC9φd are supplied, respectively. Comparing amplifiers 24, 25 and 26 are provided to detect a difference in gain or a difference in black level between one signal channel and the other three signal channels. The signal channel that includes the amplifier 6a is selected as the reference signal channel. Therefore, the output signal of the sample and hold circuit 23a is supplied to one input terminal of each of the comparison amplifiers 24, 25, and 26, and the sample and hold circuit 23a
The output signals of b, 23c, and 23d are sent to comparison amplifiers 24 and 25.
．． 26 are respectively supplied to the other input terminal.

The error signals obtained from the comparison amplifiers 24, 25, 26 are supplied to averaging circuits 27, 28, 29.

The averaging circuits 27, 28, and 29 smooth the error signal over one field period.
．． 29, a vertical synchronization signal is supplied from a terminal 30. The error signals averaged by these averaging circuits 27, 28, and 29 are stored in the memory 31. In the example shown in FIG. 1, an analog memory is used as the memory 31, but a digital memory may also be used. However, in the case of a digital memory, an A/D for converting the error signal written into the memory 31 into a digital signal.
A converter is required, as well as a D/A converter to convert the digital signal read from memory 31 into an analog error signal.

The memory 31 includes memory portions 32b and 33b in which the error signal from the averaging circuit 27 is stored, and memory portions 32c and 33c in which the error signal from the averaging circuit 28 is stored.
and memory portions 32d and 33d in which the error signal from the averaging circuit 29 is stored. Also, memory 3
A switch 34 is provided in association with 1. Memory portion 32b.

Error signals regarding gain are stored in memory portions 32c and 32d, and error signals regarding black level are stored in memory portions 33b, 33c and 33d.

The error signals read out from the memory portions 32b, 32c and 32d are sent to the variable gain amplifier 10b.

10c and 10d as a gain control signal, and the gain of the signal channel including the amplifier 10a is made equal to the gain of the other three signal channels.

Error signals read from memory portions 33b, 33c and 33d, respectively, are applied to variable voltage sources 14b and 14c.

14d as a control signal. The value of the clamp voltage is controlled by each of the variable voltage sources 14b, 14c, and 14d, and the black level is controlled to be equal among the four channels. The switch 34 is provided to switch between adjusting the gain and adjusting the black level. For example, the switch 34 is turned on when adjusting the black level.

When adjusting the gain, a color camera photographs an object whose entire surface is white, and an imaging output signal is guided to the sample and hold circuits 23a to 23d via the turned-on switch 22. As shown in FIG. 5, the level of the imaging output signal obtained when a completely white object is photographed does not match among the four signal channels due to variations in gain. The sample hold circuits 23a to 23d include
Sampling pulses φa, φb, φC2φ shown in FIG. 5B
d is supplied to each of the four signal channels, and the white level of each of the four signal channels is detected by sample and hold circuits 23a to 23d.

The output signals of the sample and hold circuits 23a to 23d are supplied to comparison amplifiers 24, 25, and 26, and the difference in the level of the output signal of each of the sample and hold circuits 23b, 23c, and 23d with respect to the level of the output signal of the sample and hold circuit 23a is detected. be done.

The average value of one field of the output signals of the comparison amplifiers 24, 25, and 26 is stored in the memory portion 32b of the memory 31.

32c and 32d. When the setting operation is completed, the switch 22 is turned off, and the memory portions 32b,
The error signals read from the amplifiers 32c and 32d are supplied as control signals to the variable gain amplifiers 10b, 10c and 10d. Variable gain amplifiers 10b, 10c, and 10d control the gains between channels to be equal.

Therefore, after the setting operation is performed, if an object whose entire surface is white is photographed, the levels of the output signals of each channel will be equal.

When adjusting the black level, the iris of the color camera is completely closed and the switches 22 and 34 are turned on. Similar to the gain adjustment described above, the black level is detected and compared, and the error signal is stored in the memory portion 33b of the memo I731.
, 33c, 33d. And memory 31
The variable voltage sources 14b and 14c are controlled by the error signal read from the
and 14d are controlled so that the black levels of the four channels match.

Note that once the gain or black level is set to eliminate the difference between channels, there will be almost no fluctuations other than changes in the circuit over time. Therefore, for example, by manually adjusting a variable resistor, the gain or clamp voltage can be controlled, and the level of each channel may be adjusted while observing the imaging output signal obtained at the output terminal 21. Typically, such preset adjustments are made at the time of factory shipment.

〔Effect of the invention〕

According to this invention, since the output signals of the plurality of horizontal registers are respectively supplied to the clamp circuit, random noise such as reset noise is removed by the clamp circuit.

Furthermore, in this invention, the output signals of the plurality of clamp circuits are delayed by different amounts before being supplied to the non-adding mixer, so the information signal voltage can be extracted without using sample and hold. High frequency noise (thermal noise)
It is possible to prevent aliasing and improve the S/N ratio. Furthermore, since the output signals of a plurality of horizontal registers can be combined by the non-additive mixer, the circuit configuration can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2 and 3 are a route map showing the configuration of a solid-state imaging device in an embodiment of the invention, and timing charts used to explain the processing of output signals. No. 4 is a waveform diagram of each part used to explain the operation of an embodiment of the present invention, FIG. 5 is a waveform diagram used to explain the gain adjustment operation of an embodiment of the invention, and FIGS. 6 and 7 are signal extraction diagrams. FIGS. 8 and 9 are a connection diagram of an example of the circuit and a waveform diagram of each part used for explaining the operation. FIGS. 8 and 9 are a connection diagram of a correlated double sampling circuit and a waveform diagram for explaining the same. Explanation of main symbols in the drawings 4a, 4b, 4c, 4d: horizontal register, 5a5b,
5C15d: Output amplifier, 10b, 10C, 10d
: variable gain amplifier, lla, llb. 11c, lid: clamp circuit, 16, 17° 18
: delay circuit, 19: non-adding mixer, 24.25.
26: Comparison amplifier, 31: Memory. Agent Patent Attorney Tadashi Sugiura Tomo SbI Sdl Sb2 Sd2 Each V Ryoshozu 4th 7th f! f

Claims (1)

[Claims] A plurality of light-receiving elements arranged in a matrix, a plurality of vertical register sections for transferring signal charges accumulated in the light-receiving elements, controlled by a common transfer clock, In an output circuit of a solid-state imaging device having N horizontal register sections (N is an integer of 2 or more) each selectively receiving and reading out the output of the vertical register sections, each of the N horizontal register sections A clamp circuit clamps the reference level portion of the output signal, and the output signals of the N clamp circuits are respectively 0, 1/NT, 2/NT, . . .
- An output circuit for a solid-state imaging device, which includes a delay circuit that delays (N-1)/NT (T: period of a transfer clock) and outputs the output signals of the delay circuit in a non-additive manner.