JP2006025451A - Correlated double sampling circuit and amplification type solid-state imaging device employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a correlated double sampling circuit that remarkably suppresses a fixed pattern noise, and an amplification type solid-state imaging device employing the circuit. <P>SOLUTION: An input changeover switch 200 is switched to the vertical signal line 145 side in a first period, and the signal of the vertical signal line 145 is clamped by first clamping circuit (201, 202) in the first half of the first period. Thereafter, a signal on the output side of the clamping capacitor 201 is sampled and held by first sample hold circuit (203, 204) in the last half of the first period. Next, the input changeover switch 200 is switched to the fixed potential side in a second period, and the clamping potential is sampled and held by the first clamping circuit with respect to a fixed potential in the first half of the second period. Thereafter, a signal on the output side of the clamping capacitor 201 is sampled and held by the first sample hold circuit. Then, a difference between the signals sampled and held before and after the second sample hold operation executed by the first sample hold circuit is taken. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a correlated double sampling circuit having a clamp unit and a sample hold unit, and an amplification type solid-state imaging device using the same.

  Conventionally, as an amplification type solid-state imaging device, the signal charge generated in each pixel itself is not read, converted into a voltage signal (or current signal) within the pixel, amplified, and then scanned for the voltage signal (or current signal). What is read by a circuit has been proposed. The pixel portion of the amplification type solid-state imaging device is classified into a horizontal type in which the photoelectric conversion unit and the amplification unit are arranged in a plane and a vertical type in which the photoelectric conversion unit and the amplification unit are arranged in a three-dimensional manner.

As the horizontal amplification type solid-state imaging device, an APS (Active Pixel Sensor) type shown in FIG. 14 is known. In FIG. 14, the signal charge generated in the photoelectric conversion unit 101 is transferred to the gate of the transistor 103 via the transistor 102 having the voltage φ _T applied to the gate to become a voltage signal. In the transistor 103, impedance conversion (current amplification) is performed, and the signal V _sig is read out through the pixel selection switch 104 in which the voltage φ _X is applied to the gate. Immediately before or after the reading of the signal V _sig , the signal charge accumulated in the gate of the transistor 103 is discharged to the power supply voltage V _D side by the reset transistor 105 whose voltage φ _R is applied to the gate.

As a vertical amplification type solid-state imaging device, a CMD (Charge Modulation Device) type shown in FIG. 15 is known. In FIG. 15, a transistor 111 accumulates signal charges generated by photoelectric conversion under the gate. Next, by applying a read voltage φ _X to the gate of the transistor 111, a change in characteristics of the transistor 111 due to the signal charge is read as an output signal V _sig . Thus, in the transistor 111, photoelectric conversion, amplification, and pixel selection are performed. Further, the reset operation is achieved by applying a voltage φ _R sufficiently higher than that at the time of reading to the gate so that signal charges are discharged to the substrate side. For this reason, a ternary high voltage pulse of φ _X / φ _R is required for driving.

As shown in FIG. 16, the pixel portion of each amplification type solid-state imaging device shown in FIGS. 14 and 15 is represented by a common schematic diagram. In FIG. 16, reference numeral 131 denotes a pixel portion that performs photoelectric conversion, readout, and reset operation. Reading of the pixel portion 131 is controlled by the voltage φ _X of the signal line 106, and resetting is controlled by the voltage φ _R of the signal line 107. Then, the pixel portion 131 outputs the amplified signal V _sig via the vertical signal line 107.

  FIG. 17 is a configuration diagram of an amplification type solid-state imaging device (two-dimensional image sensor) configured using the pixel unit. In FIG. 17, the pixel portion 131, the first vertical scanning circuit 141, and the second vertical scanning circuit 142 form a two-dimensional pixel region 140. The readout operation of the pixel unit 131 is controlled by a signal 143 from the first vertical scanning circuit 141, and the reset operation is controlled by a signal 144 from the second vertical scanning circuit 142. The output signal from the pixel unit 131 is read out to the vertical signal line 145, and then guided to a correlated double sampling circuit provided for each vertical signal line 145. The difference from the reference signal is output from the correlated double sampling circuit. Here, there are two cases in which the light reception signal and the reference signal come before. In the difference output, the variation in threshold value for each pixel unit 131 is canceled, and fixed pattern noise (hereinafter referred to as FPN) for each pixel unit 131 is suppressed. The correlated double sampling circuit includes a clamp circuit (clamp capacitor 146, clamp switch 147) and a sample hold circuit (sample hold switch 148, sample hold capacitor 149).

In the correlated double sampling circuit, the vertical signal line 145 is connected to the sample hold switch 148 via the clamp capacitor 146 and to the clamp potential V _CP via the clamp switch 147. The clamp operation to the clamp potential V _CP is performed by setting the pulse φ _C1 to the high level when the light reception signal is read from the pixel unit 131, and the sample hold operation is performed when the reference signal is read from the pixel unit 131. This is done by setting φ _S1 to high level. The signal from the sample hold switch 148 is held in the sample hold capacitor 149 and amplified by the amplifier circuit 155. The signal amplified by the amplifier circuit 155 is guided to the horizontal signal line 164 via the horizontal selection switch 156 controlled by the output line 161 from the horizontal scanning circuit 160, and the signal on the horizontal signal line 164 is amplified by the amplifier circuit 169. The signal OS is output via.
Japanese Patent Laid-Open No. 10-173997

  As described above, in the amplification type solid-state imaging device (two-dimensional image sensor) illustrated in FIG. 17, the correlated double sampling circuit provided for each vertical signal line 145 suppresses FPN due to threshold variation for each pixel unit 131. However, the amplifier circuit 155 for each vertical signal line 145 is accompanied by variations in offset level and gain. Since this variation is random in the horizontal direction of the image and common in the vertical direction, the image becomes a remarkable FPN with a vertical stripe pattern, and the image quality is significantly impaired. Furthermore, since the horizontal selection switch 156 is accompanied by variation in conductance, this also causes a vertical stripe pattern FPN.

As a method for solving the above vertical stripe pattern FPN, the present applicant has proposed an amplification type solid-state imaging device (two-dimensional image sensor) shown in FIG. 18 (Japanese Patent Laid-Open No. 10-173997: Patent Document 1). In this amplification type solid-state imaging device, the two-dimensional pixel region has the same configuration as 140 shown in FIG. 17, and the illustration and description of the two-dimensional pixel region are omitted. Further, the correlated double sampling circuit provided for each vertical signal line 145 has the same configuration as that in FIG. The difference from the amplification type solid-state imaging device shown in FIG. 17 is that the input of the amplifier circuit 155 for each vertical signal line 145 is two, one is the signal 153 from the correlated double sampling circuit, and the other is the reference voltage signal V _ref. It is in the point. Further, a second CDS (correlated double sampling) circuit 168 is provided at the end of the horizontal signal line 164.

In the amplification type solid-state imaging device (two-dimensional image sensor) having the above configuration, the signal from the amplifier circuit 155 is sent to the horizontal signal line by the horizontal selection switch 156 driven by the pulse φ _H (j) from the horizontal scanning circuit 160. The data is sequentially read to 164. In the middle of each readout period, the input of the amplifier circuit 155 is switched from the signal 153 to the reference signal 154. Accordingly, the horizontal signal line 164 sequentially obtains the signal of each vertical signal line 145 and the reference signal in pairs. Further, since the characteristic variation of each amplifier circuit 155 and the selection horizontal selection switch 156 exists in common to each of these pair signals, the second CDS circuit 168 causes the difference between the signal on each vertical signal line 145 and the reference signal. As a result, only a net signal component from which the characteristic difference between each amplifier circuit 155 and the selected horizontal selection switch 156 is removed is obtained. This prevents the vertical stripe pattern FPN.

  However, the amplification type solid-state imaging device (two-dimensional image sensor) shown in FIG. 18 has the following problems. That is, the clamp switch 147 for each vertical signal line 145 has a slight variation in characteristics, so that the feedthrough level during the clamping operation varies slightly for each vertical signal line 145. Further, since the sample hold switch 148 for each vertical signal line 145 also has a slight variation in characteristics, the feedthrough level during the sample hold operation also varies somewhat for each vertical signal line 145. These variations in the feedthrough level cause vertical stripe-shaped FPN.

Therefore, as another method for solving the vertical stripe pattern FPN, an amplification type solid-state imaging device (two-dimensional image sensor) shown in FIG. 19 has been proposed (Japanese Patent Laid-Open No. 10-145681). As shown in FIG. 19, a pair of capacitors 191 and 192 are connected to each vertical signal line 145 via a switch 190, and the other ends (output ends) of the capacitors 191 and 192 are connected via a switch 193 and 194 as a reference. Connected to voltage _Vref . The output terminal of the capacitor 191 branches and is input to the amplifier circuit 155. Signals from the amplifier circuit 155 are controlled by pulses φ _H (j) and φ _A2 (j) from the horizontal scanning circuit 160, and are sequentially read out to the horizontal signal line 164. Thereafter, only the net signal component is obtained by the second CDS circuit 168.

20A to 20E are timing charts for explaining the operation of the amplification type solid-state imaging device shown in FIG. In the following, the case where the light reception signal is the front and the reset signal is the back will be described. At time t ₁ within the horizontal blanking period, the switch 193 is turned on and the switch 190 is turned on (shown in FIGS. 20A and 20B), so that the potential of the (V ₂ ) portion is received by the pixel element. The signal becomes _Vf (shown in FIG. 20D), and the potential of the (V ₃ ) portion becomes V _ref (shown in FIG. _20E ). Thereafter, the switches 190 and 193 are sequentially turned off, whereby the (V ₂ ) potential becomes V _f −ΔV ₁ −ΔV ₂ and the (V ₃ ) potential becomes V _ref −ΔV ₂ (FIG. 20 (d), ( as shown in e)). However, ΔV ₁ is a field through level by the switch 190 at (V ₂ ), and ΔV ₂ is a field through level by the switch 193 at (V ₃ ). Through the above operation, the capacitor 191 holds the next voltage.

(V _f −ΔV ₁ −ΔV ₂ ) − (V _ref −ΔV ₂ ) = V _f −V _ref −ΔV ₁ Then, at time t ₂ within the horizontal blanking period, the switch 194 is turned on, and the switch 190 is turned on. By turning on (shown in FIGS. 20A and 20C), the potential of the (V ₂ ) portion becomes V _d −ΔV ₁ when the switch 190 is turned off after the pixel reset signal V _d is turned on. . At this time, since the potential of the (V ₃ ) portion is DC (direct current) floating, it is shifted from the (V ₂ ) voltage by the voltage difference held in the capacitor 191, and thus becomes the next voltage.

(V _d −ΔV ₁ ) − (V _f −V _ref −ΔV ₁ ) = V _ref + (V _d −V _f ) That is, the field through level ΔV ₁ of the switch 190 cancels out, and the light receiving signal V of the pixel element _A net effective signal V _d −V _f which is the difference between _f and the reset signal V _d is obtained as a value obtained by adding the reference voltage V _ref .

However, the amplification type solid-state imaging device of FIG. 19 has the following problems. In other words, during the period for reading out the pixel signals of one horizontal column, the pixel signals are held in the input of the amplifier circuit 155 and the region connected thereto, and this held period is distributed over the period during which the horizontal scanning circuit 160 scans. The pixel is short and the last pixel is long. For this reason, if a leak current exists in the input region of the amplifier circuit 155, the holding voltage decreases by ΔV _drp , and this value is small at the first pixel and large at the final pixel. That is, the output signal has a shading-like non-uniformity distributed from the left side to the right side on the screen. This also becomes a kind of FPN, and the image quality is greatly impaired. Further, the capacitors 191 and 192 and the switches 193 and 194 are not completely equivalent, and there are some differences, so that in actual operation, slight variations occur for each vertical signal line 145. FPN does not disappear completely.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an amplification type solid-state imaging device that can greatly reduce FPN associated with horizontal pixel selection, reduce shading-like non-uniformity, and obtain a high-quality image without FPN with a simple configuration. An object of the present invention is to provide a correlated double sampling circuit capable of realizing the device and an amplification type solid-state imaging device using the same.

  In order to achieve the above object, in the correlated double sampling circuit according to claim 1, a signal line is connected to one input terminal, a fixed potential is applied to the other input terminal, and the signal of the signal line or the fixed potential is An input changeover switch that selects and outputs one of them, a clamp capacitor that has one end on the input side connected to the output terminal of the input changeover switch, and one end that is connected to the other end on the output side of the clamp capacitor. First clamp means having a clamp switch whose end is connected to the clamp potential, a sample hold switch having one end connected to the other end of the clamp capacitor, and a sample having one end connected to the other end of the sample hold switch A first sample-and-hold means having a hold capacitor; and the input changeover switch is connected to the signal in the first period. And the signal on the signal line is clamped by the first clamping means in the first half of the first period, and then the signal on the output side of the clamp capacitor is the first sample in the second half of the first period. In addition to sample-holding by the holding means, in the second period following the first period, the input changeover switch is switched to the fixed potential side, and the clamp potential with respect to the fixed potential in the first half of the second period. Is sampled and held on the output side of the clamp capacitor by the first clamp means, and then the input changeover switch, clamp switch and so on are used to sample and hold the signal on the output side of the clamp capacitor by the first sample hold means. A control means for controlling the sample hold switch is provided.

  According to the correlated double sampling circuit of the first aspect, the first correlated double sampling operation by the first clamp means and the first sample hold means in the first period when the input changeover switch is switched to the signal line side ( (Hereinafter referred to as CDS operation), a net signal is obtained in the sample and hold capacitor as a difference between the first half period signal and the second half period signal. Next, a reference including the same feedthrough level as the first CDS operation is performed by the second CDS operation by the first clamp means and the first sample hold means in the second period when the input changeover switch is switched to the fixed potential side. A signal is applied to the sample and hold capacitor. Therefore, if the difference between the signals held in the sample-and-hold capacitors before and after the second sample-and-hold operation is taken, only a net signal component in which all the feedthrough levels generated in the CDS operation are canceled can be obtained. Therefore, by applying this correlated double sampling circuit to the amplification type solid-state imaging device, it is possible to greatly reduce the FPN associated with the horizontal pixel selection with a simple configuration, and to reduce the shading-like nonuniformity. High quality images can be obtained.

  The correlated double sampling circuit according to claim 2 is characterized in that, in the correlated double sampling circuit according to claim 1, the capacitance of the clamp capacitor is not less than 10 times the capacitance of the sample and hold capacitor.

  According to the correlated double sampling circuit of claim 2, when the capacitance of the clamp capacitor is set to 10 times or more of the sample hold capacitor, the signal passing through the clamp capacitor is accumulated in the sample hold capacitor. Gain can be increased.

  The correlated double sampling circuit according to claim 3 is the correlated double sampling circuit according to claim 1 or 2, wherein each of the clamp switch and the sample hold switch comprises a MOS transistor, and the clamp switch with respect to the capacitance of the clamp capacitor. And the ratio of the junction area of the sample and hold switch to the capacitance of the sample and hold capacitor is substantially the same.

  According to the correlated double sampling circuit of claim 3, the ratio of the junction area of the clamp switch to the capacitance of the clamp capacitor and the ratio of the junction area of the sample and hold switch to the capacitance of the sample and hold capacitor are substantially the same. Since the potential drop due to the leakage current of the MOS transistor becomes equal on the signal line between the clamp capacitor and the sample and hold capacitor and the signal line on the output side of the sample and hold capacitor, the potential drop due to the leakage current of the MOS transistor is reduced. It can be reliably removed by the CDS operation.

  According to a fourth aspect of the present invention, there is provided an amplifying solid-state image pickup device, an amplifying pixel element for amplifying and outputting a photoelectric conversion means and a light reception signal formed by the photoelectric conversion means and a reference signal serving as a reference for the light reception signal; A vertical signal line to which an output of the pixel element is connected; an amplifying unit for amplifying a signal of the vertical signal line; and a horizontal signal line to which an output of the amplifying unit is connected via a horizontal selection switch; An amplification type solid-state imaging device that transmits a signal of the pixel element to a horizontal signal line via the vertical signal line, an amplifying unit, and a horizontal selection switch, and between the vertical signal line and the amplifying unit. 3 is provided with one of the correlated double sampling circuits.

  According to the amplification type solid-state imaging device of the fourth aspect, the light reception signal of the pixel element is obtained by the first CDS operation by the first clamp means and the first sample hold means of the correlated double sampling circuit in the first period. And the difference between the reference signal and the reference signal is obtained on the input side of the amplification means for each vertical signal line, and then the first CDS is performed by the second CDS operation by the first clamp means and the first sample hold means in the second period. A reference signal including the same feedthrough level as the operation is obtained on the input side of the amplification means. Therefore, after that, by taking the difference between the difference signal and the reference signal by the CDS operation at the end of the horizontal signal line, only the net signal component in which all the feedthrough levels are canceled is obtained. Therefore, it is possible to realize an amplification type solid-state imaging device with a simple configuration that can greatly reduce FPN due to horizontal pixel selection, reduce shading-like non-uniformity, and obtain a high-quality image without FPN.

  The amplification type solid-state imaging device according to claim 5 is the amplification type solid-state imaging device according to claim 4, wherein the input changeover switch is switched to the vertical signal line side in the first period, and the first period After clamping one of the light reception signal or reference signal of the pixel element by the first clamping means in the first half period of the first, the other of the light reception signal or reference signal of the pixel element in the second half period of the first period, By sampling and holding the first sample and hold means through the clamp capacitor, a signal representing the difference between the received light signal from the pixel element and the reference signal by the amount of displacement from the clamp potential is held in the sample and hold capacitor. After that, in the second period, the input selector switch is turned to the fixed potential side. Thus, after the clamp potential is sampled and held on the output side of the clamp capacitor by the first clamp means at the beginning of the second period, the horizontal selection switch is turned on and the amplification means In the first half of the period in which the output signal is read out to the horizontal signal line, a first output signal that represents the difference between the light reception signal from the pixel element and the reference signal by the amount of displacement from the clamp potential is supplied to the horizontal signal via the amplification means. After output to the signal line, the signal on the output side of the clamp capacitor is sampled and held by the first sample-and-hold means, and becomes the clamp potential in the second half of the conduction period of the horizontal selection switch after the sample-and-hold. An output signal is output to the horizontal signal line through the amplification means.

  According to the amplification type solid-state imaging device of the fifth aspect, in the first period, the input changeover switch is switched to the signal line side, and the light receiving signal of the pixel element in the first half period of the first period. Alternatively, one of the reference signals is clamped by the first clamping means. Next, the other one of the light reception signal or the reference signal of the pixel element is sampled and held by the first sample hold means via the clamp capacitor in the latter half of the first period, and the light reception signal from the pixel element A signal representing the difference between the reference signal and the reference signal by the amount of displacement from the clamp potential is held in the sample hold capacitor. Thereafter, in the second period, the input changeover switch is switched to the fixed potential side, and the clamp potential is set to the fixed potential at the beginning of the second period by the first clamp means. Sample hold on output side. Next, in the first half of the period in which the horizontal selection switch is turned on and the output signal of the amplification means is read out to the horizontal signal line, the difference between the light reception signal from the pixel element and the reference signal is determined by the amount of displacement from the clamp potential. After the first output signal is output to the horizontal signal line via the amplification means, the signal on the output side of the clamp capacitor is sampled and held by the first sample hold means, and the horizontal selection switch A second output signal representing the clamp potential is output to the horizontal signal line in the second half of the conduction period. The difference between the received light signal and the reference signal is obtained by taking the difference between the first and second output signals thus obtained.

  An amplification type solid-state imaging device according to a sixth aspect is the amplification type solid-state imaging device according to the fifth aspect, wherein the first of the pair of the first output signal and the second output signal from the horizontal signal line. A second clamping means for clamping an output signal and outputting a difference signal between the first output signal and the second output signal during a period of the second output signal; and sampling the difference signal from the second clamping means And a second sample hold means for holding and outputting the sampled and held difference signal.

  According to the amplification type solid-state imaging device of the sixth aspect, the set of the first output signal and the second output read out to the horizontal signal line by the configuration of the second clamp circuit and the second sample hold circuit. A difference signal from the signal, that is, a difference between the light reception signal from the pixel element and the reference signal is obtained, and a signal representing an FPN-free image from which all variation components are removed can be obtained.

  An amplification type solid-state imaging device according to a seventh aspect is the amplification type solid-state imaging device according to the fifth aspect, wherein the first of the pair of the first output signal and the second output signal from the horizontal signal line. Third sample hold means for sample-holding the output signal, and fourth sample hold means for sample-holding the second output signal of the set of the first output signal and the second output signal from the horizontal signal line. And calculating means for obtaining a difference signal between the first output signal held by the third sample hold means and the second output signal held by the fourth sample hold means and outputting the difference signal It is characterized by having.

  According to the amplification type solid-state imaging device of the seventh aspect, the first set of the first set read out to the horizontal signal line is configured by taking the difference between the outputs of the third and fourth sample and hold circuits by the calculating means. A difference signal between the output signal and the second output signal, that is, a difference between the light reception signal from the pixel element and the reference signal is obtained, and a signal representing an FPN-free image from which all variation components are removed can be obtained.

  An amplification type solid-state imaging device according to claim 8 is the amplification type solid-state imaging device according to any one of claims 4 to 7, wherein the control means is a first control signal that is turned on in the latter half of the first period. And a second control signal that is turned on during a period in which the horizontal selection switch in the second period is turned on, and the first control signal is input to one input terminal, A control signal is input to the other input terminal, and a sample hold changeover switch having an output terminal connected to the control input terminal of the sample hold switch of the first sample hold means is provided.

  According to the amplification type solid-state imaging device of the eighth aspect, the sample hold changeover switch is switched to the first control signal side in the latter half of the first period, and the horizontal selection switch in the second period is turned on. By switching the sample hold changeover switch to the second control signal side during the period, the sample hold switch of the first sample hold means can be controlled for each vertical signal line in which the horizontal selection switch is sequentially turned on with a simple configuration. .

  The correlated double sampling circuit according to claim 9 is the correlated double sampling circuit according to claim 1 or 2, wherein each of the clamp switch and the sample hold switch is composed of a MOS transistor, and the gate portion of the MOS transistor of the clamp switch. The ratio of the junction area to the area is substantially the same as the ratio of the junction area to the gate area of the MOS transistor of the sample hold switch.

  According to the correlated double sampling circuit of claim 9, the ratio of the junction area to the gate area of the MOS transistor of the clamp switch and the ratio of the junction area to the gate area of the MOS transistor of the sample and hold switch Since the potential drop due to the leakage current of the MOS transistor becomes equal on the signal line between the clamp capacitor and the sample-and-hold capacitor and the signal line on the output side of the sample-and-hold capacitor. The potential drop can be reliably removed by the CDS operation.

  The correlated double sampling circuit according to claim 10 is the amplification type solid-state imaging device according to claim 5, wherein all the horizontal selections are performed in a period during which the first sample hold means samples and holds in at least the first period. The horizontal selection connected to the first sample hold means during a period in which the switch is conductive and the signal on the output side of the clamp capacitor in the second period is sampled and held by the first sample hold means. The switch is in a conductive state.

  According to the correlated double sampling circuit of the tenth aspect, the horizontal selection switch becomes conductive when the first sample hold means samples and holds both in the first and second periods, and the output of the amplifier means Are connected to the horizontal signal line via a horizontal selection switch. Therefore, the state of the load side of the first sample hold means is the same during the operation of the first sample hold means during the first and second periods, and the operation conditions are the same for the two operations. The unevenness of the shape can be reduced more completely.

  The correlated double sampling circuit according to claim 11 is the amplification type solid-state imaging device according to claim 10, comprising a constant current load connected to the horizontal signal line via a load connection switch, and at least all of the horizontal selection circuits. The load connection switch is in an OFF state during a period in which the switch is in a conductive state.

  According to the correlated double sampling circuit of claim 11, the load connection switch is turned off to disconnect the constant current source from the horizontal signal line during a period in which at least all of the horizontal selection switches are conductive. As a result, no load current flows, so that even if there is a large level difference between the outputs of the amplifying means, no interference occurs. Therefore, the sample-and-hold capacitor on the input side of the amplifying means is not affected, and the correct sample-and-hold operation can be performed in both operations, and the nonuniformity of FPN and sharding can be more completely reduced.

  Further, the correlated double sampling circuit according to claim 12 is the amplification type solid-state imaging device according to claim 5, wherein all the horizontal selections are performed in a period in which the first sample hold means samples and holds in at least the first period. The horizontal switch connected to the first sample hold means during a period in which the switch is non-conductive and the signal on the output side of the clamp capacitor within the second period is sampled and held by the first sample hold means. The selection switch is in a non-conductive state.

  According to the correlated double sampling circuit of the twelfth aspect, the horizontal selection switch becomes non-conductive when sample-holding is performed by the first sample-holding means in both the first and second periods, and the amplification means The output is not connected to the horizontal signal line via the horizontal selection switch. Therefore, the state of the load side of the first sample hold means is the same during the operation of the first sample hold means during the first and second periods, and the operation conditions are the same for the two operations. The unevenness of the shape can be reduced more completely.

  In the correlated double sampling circuit according to the first aspect of the present invention, the first half of the signal is obtained by the first CDS operation by the first clamp means and the first sample hold means during the first period when the input changeover switch is switched to the signal line side. The net signal is held in the sample and hold capacitor as the difference between the period signal and the second half period signal, and then in the second period when the input changeover switch is switched to the fixed potential side, the first clamp means and the first sample and hold means By the second CDS operation, a reference signal including the same feedthrough level as that in the first CDS operation is obtained in the sample and hold capacitor.

  Therefore, according to the correlated double sampling circuit of the first aspect of the invention, if the difference between the signals held in the sample and hold capacitors before and after the second sample and hold operation is taken, the noise component of the signal line is removed by the CDS operation. In addition, the clamp feedthrough level, sample hold feedthrough level generated by the CDS operation, and an extremely low noise signal from which the potential lowering component due to leakage is removed can be obtained. is there. Therefore, by applying this correlated double sampling circuit to the amplification type solid-state imaging device, it is possible to greatly reduce the FPN associated with the horizontal pixel selection with a simple configuration, and to reduce the shading-like nonuniformity. High quality images can be obtained.

  According to a second aspect of the present invention, there is provided a correlated double sampling circuit according to the first aspect of the present invention, wherein the clamp capacitor has a capacitance more than 10 times the capacity of the sample hold capacitor. The gain when the signal is accumulated in the sample hold capacitor can be increased.

  According to a third aspect of the present invention, there is provided a correlated double sampling circuit according to the first or second aspect, wherein each of the clamp switch and the sample hold switch is composed of a MOS transistor, and clamps the capacitance of the clamp capacitor. Since the ratio of the junction area of the switch and the ratio of the junction area of the sample and hold switch to the capacity of the sample and hold capacitor are substantially the same, the signal line between the clamp capacitor and the sample and hold capacitor and the sample and hold capacitor The potential drop due to the leak current of the MOS transistor becomes equal on the signal line on the output side, and the potential drop due to the leak current of the MOS transistor can be reliably removed by the CDS operation.

  According to a fourth aspect of the present invention, there is provided an amplification type solid-state imaging device that amplifies and outputs a photoelectric conversion means and a light reception signal formed by the photoelectric conversion means and a reference signal serving as a reference of the light reception signal. An element, a vertical signal line to which the output of the pixel element is connected, an amplifying means for amplifying the signal of the vertical signal line, and a horizontal signal line to which the output of the amplifying means is connected via a horizontal selection switch. An amplification type solid-state imaging device that transmits a signal of the pixel element to a horizontal signal line via a vertical signal line, an amplifying unit, and a horizontal selection switch, between the vertical signal line and the amplifying unit. 3 is provided with one of the correlated double sampling circuits.

  Therefore, according to the amplification type solid-state imaging device of the fourth aspect of the present invention, it is possible to remove the clamp feedthrough level, the sample hold feedthrough level, and the potential lowering component due to the leak generated by the CDS operation on each vertical signal line. It becomes possible to obtain a high-quality image signal from which all variation components have been removed. Further, compared with the conventional case where a correlated double sampling circuit is provided for each vertical signal line, it is extremely simple only by adding an input changeover switch in front of the clamp capacitor, and the area can be kept small.

  An amplification type solid-state imaging device according to a fifth aspect of the invention is the amplification type solid-state imaging device according to the fourth aspect, wherein the input changeover switch is switched to the signal line side in the first period, and the first One of the light reception signal or the reference signal of the pixel element is clamped by the first clamping means in the first half period of the period, and then the other of the light reception signal or the reference signal of the pixel element in the second half period of the first period. Is sampled and held by the first sample and hold means via the clamp capacitor, and a signal representing the difference between the light reception signal from the pixel element and the reference signal by the amount of displacement from the clamp potential is supplied to the sample and hold capacitor. After holding, in the second period, the input selector switch is switched to the fixed potential side. At the beginning of the second period, the clamp potential with respect to the fixed potential is sampled and held on the output side of the clamp capacitor by the first clamp means, and then the horizontal selection switch is turned on so that the amplification means In the first half of the period in which the output signal is read out to the horizontal signal line, a first output signal that represents the difference between the light reception signal from the pixel element and the reference signal by the amount of displacement from the clamp potential is supplied to the horizontal signal line via the amplification means. The output signal of the clamp capacitor is sampled and held by the first sample and hold means, and the second output signal representing the clamp potential is horizontal in the second half of the conduction period of the horizontal selection switch after the sample and hold. By outputting to the signal line and taking the difference between the first and second output signals, the received light signal and the reference signal The difference is obtained.

  An amplification type solid-state imaging device according to a sixth aspect of the invention is the amplification type solid-state imaging device according to the fifth aspect, wherein the first output signal and the second output signal of the set from the horizontal signal line are a first one. A second clamp means for clamping the output signal and outputting a difference signal between the first output signal and the second output signal during a period of the second output signal; and sampling and holding the difference signal from the second clamp means. The difference between the first output signal and the second output signal read out to the horizontal signal line, that is, the light reception from the pixel element, is constituted by the second sample hold means for outputting the difference signal sampled and held. A difference between the signal and the reference signal is obtained, and a signal representing an image without FPN from which all variation components are removed can be obtained.

  An amplification type solid-state imaging device according to a seventh aspect of the present invention is the amplification type solid-state imaging device according to the fifth aspect, wherein outputs of the third and fourth sample and hold circuits that sample and hold the first output signal are calculated by the arithmetic means. A difference signal between a set of the first output signal and the second output signal read out to the horizontal signal line, that is, a pixel element, by taking the difference between the outputs of the fourth sample hold circuit that samples and holds the second output signal. A difference between the received light signal from the reference signal and the reference signal is obtained, and a signal representing an FPN-free image from which all variation components have been removed can be obtained.

  An amplification type solid-state imaging device according to an eighth aspect of the present invention is the amplification type solid-state imaging device according to any one of the fourth to seventh aspects, wherein a sample-hold changeover switch is connected to the control means from the control means in the latter half of the first period. By switching to the first control signal side and switching the sample-hold changeover switch to the second control signal side from the control means during a period in which the horizontal selection switch in the second period is conductive, a simple configuration is achieved. Thus, the sample hold switch of the first sample hold means can be controlled for each vertical signal line through which the horizontal selection switch is sequentially turned on.

  According to a ninth aspect of the present invention, there is provided a correlated double sampling circuit according to the first or second aspect, wherein each of the clamp switch and the sample hold switch comprises a MOS transistor, and the clamp switch has a MOS transistor. Since the ratio of the junction area to the gate area and the ratio of the junction area to the gate area of the MOS transistor of the sample hold switch are substantially the same, the signal line and sample between the clamp capacitor and the sample hold capacitor The potential drop due to the leak current of the MOS transistor becomes equal on the signal line on the output side of the hold capacitor, and the potential drop due to the leak current of the MOS transistor can be reliably removed by the CDS operation.

  According to a tenth aspect of the present invention, there is provided the correlated double sampling circuit according to the fifth aspect, wherein at least the first sample-and-hold means within the first period samples and holds in the amplification type solid-state imaging device. The horizontal selection switch is turned on, and the signal connected to the first sample-holding means is connected to the first sample-holding means during a period in which the signal on the output side of the clamp capacitor in the second period is sample-held by the first sample-holding means. Since the horizontal selection switch is in the conductive state, the horizontal selection switch is in the conductive state when sample-holding by the first sample-holding means in both the first and second periods, and the load-side side of the first sample-holding means is Since the state is the same in the first and second periods and the operation conditions are the same for the two operations, It can be more fully reduce the non-uniformity of PN and shading shape.

  The correlated double sampling circuit of the invention of claim 11 is the amplification type solid-state imaging device of claim 10, comprising a constant current load connected to the horizontal signal line via a load connection switch, and at least all of the above Since the load connection switch is turned off and the constant current source is disconnected from the horizontal signal line during the period in which the horizontal selection switch is in a conductive state, no load current flows, so there is a large level difference in the output of each amplification means. Even if there is no interference, it does not affect the sample hold capacitor on the input side of the amplifying means, and the correct sample hold operation can be performed in both operations, thereby further reducing the nonuniformity of FPN and sharding. It can be completely reduced.

  According to a twelfth aspect of the present invention, there is provided the correlated double sampling circuit according to the fifth aspect of the present invention, wherein all the above-mentioned samples are sampled and held by at least the first sample and hold means within the first period. The horizontal selection switch is turned off and connected to the first sample hold means during a period in which the signal on the output side of the clamp capacitor within the second period is sampled and held by the first sample hold means. Since the horizontal selection switch is in a non-conducting state, the horizontal selection switch is in a non-conducting state when sample-holding by the first sample-holding means in both the first and second periods, and the first sample-holding means Does the load-side state be the same in the first and second periods, and the operating conditions are the same for the two operations? , It is possible to more completely reduce the FPN and shading-like nonuniformity.

  Hereinafter, a correlated double sampling circuit of the present invention and an amplification type solid-state imaging device using the same will be described in detail with reference to embodiments shown in the drawings.

(First embodiment)
FIG. 1 shows a circuit diagram of a correlated double sampling circuit according to the first embodiment of the present invention. As shown in FIG. 1, the correlated double sampling circuit includes an input selector switch 200 having a vertical signal line 145 connected to one input terminal and a ground GND as a fixed potential connected to the other input terminal, A clamp capacitor 201 having one end connected to the output terminal of the input changeover switch 200, a clamp switch 202 having one end connected to the other end of the clamp capacitor 201 and the other end connected to a clamp potential _VCP , and the clamp capacitor A sample hold switch 203 having one end connected to the other end of 201, and a sample hold capacitor 204 connected between the other end of the sample hold switch 203 and the ground GND. The clamp capacitor 201 and the clamp switch 202 constitute a first clamp means, and the sample hold switch 203 and the sample hold capacitor 204 constitute a first sample hold means. The correlated double sampling circuit has a timing generation circuit 213 as control means for outputting a pulse φ _P0 , a pulse φ _C0 and a pulse φ _S0, and controls the switching of the input selector switch 200 by the pulse φ _P0 , On / off of the clamp switch 202 is controlled by the pulse φ _C0 , and on / off of the sample hold switch 203 is controlled by the pulse φ _S0 . The input signal Vin _{in the} vertical signal line 145 is held in the sample hold capacitor 204 via the clamp capacitor 201 and the sample hold switch 203, and outputs an output signal _Vout .

  2A to 2F are timing charts showing the operation of the correlated double sampling circuit. Hereinafter, the operation of the correlated double sampling circuit will be described with reference to the timing chart of FIG.

First, as shown in FIG. 2, the pulse φ _{P0 is set} to a high level within the period 1 as the first period (shown in FIG. 2B), so that the input side of the clamp capacitor 201 shown in FIG. The signal is connected to the vertical signal line 145 via the input changeover switch 200. Next, the first half period of the input signal V _in at time t ₁ in (FIG. 2 (indicated by S ₁ in a)), (shown in FIG. 2 (c)) by the pulse phi _C0 to the high level, the clamp A clamping operation to the potential V _CP is performed. Then, at time t ₂ in the second half period of the input signal (indicated by S ₂ in FIG. 2 (a)), the pulse φ _{S0 is set} to the high level (shown in FIG. 2 (d)), thereby performing the sample hold operation. Done. At this time, since the level of the signal V _m of the output side of the signal line 211 of the clamp capacitor 201, after the clamping operation at time t _1, the there is a field-through level △ V _CP of the clamp pulse φ _C0, V _CP - △ V _CP (shown in FIG. 2 (e)). Thereafter, the level of the signal V _m of the signal lines 211, the signal through the clamp capacitor 201 changes by V _S (V _S is the difference between the period S ₁ and the period S ₂ of the input signal V _in, the net ),
V _m (t ₂ ) = V _CP −ΔV _CP + V _S ………………………… (Formula 1)
It becomes. Since the output signal _Vout obtained by sampling and holding this has the feedthrough level ΔV _SH of the sample and hold pulse φ _S0 ,
V _out (t ₂ + α) = V _CP −ΔV _CP + kV _S −ΔV _SH (Equation 2)
It becomes. Note that k is a gain when a signal passing through the clamp capacitor 201 (capacitance C _c ) is accumulated in the sample hold capacitor (capacitance C _S ), and is expressed by the following equation.

k = 1−C _S / C _C ……………………………………… (Formula 3)
That is, in order to increase the gain, it is necessary to sufficiently greater than the capacitance C _S of the capacitor C _C, the normal capacity C _C more than 10 times the capacity C _S.

The signal of the above (Equation 2) decreases by ΔV _drp due to the leakage current I _d2 on the signal line 212 (signal V _out ) near the time t ₄ at the time of the second sample hold (FIG. 2 (f) As shown). Accordingly, the first output signal S _a which is obtained at time t ₄ immediately before the signal line 212 (signal V _out) is
S _a (t ₄ −Δt) = V _CP −ΔV _CP + kV _S −ΔV _SH −ΔV _drp (Equation 4)
(Shown in FIG. 2 (f)).

On the other hand, on the signal line 211, after time t ₂ , the input side of the input selector switch 200 is grounded and clamped again at time t ₃ , so that V _CP −ΔV _CP is held on the output side of the clamp capacitor 201. Is done. Here, ΔV _CP is caused by the same clamp switch 202 as in the cases of (Expression 1), (Expression 2), and (Expression 4), and thus has the same value as at time t ₁ . Thereafter, due to the leakage current I _d1 on the signal line 211 until time t ₄ , a potential drop occurs by ΔV _drp . Therefore, the potential of the signal V _m of the signal lines 211 in the vicinity of the time t ₄ is V _CP - the △ V _CP -ΔV _drp (shown in FIG. 2 (e)). At time t _4, by the sample-and-hold pulse phi _S0 to a high level, the second output signal S _b at time t ₄ after the signal line 212 (signal V _out), a feed through level △ V _SH is added And
_{S b (t 4 + △ t} ) = V CP - △ V CP -ΔV drp - △ V SH ............... ( Equation 5)
(Shown in FIG. 2 (f)). Here, ΔV _SH is the same value as at time t ₂ because it originates from the sample hold switch 203 that is exactly the same as in the cases of (Expression 2) and (Expression 4). Therefore, if a difference OS between the first output signal _Sa and the second output signal _Sb is obtained by a correlated double sampling circuit (not shown) provided on the signal line 212 (signal _Vout ),
OS = S _a −S _b = kV _S ………………………… (Formula 6)
In addition to the noise reduction effect inherent in the correlated double sampling circuit, the clamp pulse feed-through level ΔV _CP and the sample hold pulse feed-through level ΔV _SH are removed, and the potential drop ΔV _drp due to leakage current _is also eliminated. A net signal V _S is obtained.

In the period between time t ₃ and time t ₄ , the input changeover switches 200, 202, and 203 are all off, and the signal line 211 (signal V _m ) and the signal line 212 (signal V _out ) are isolated from each other. And is in a floating state. In the isolated signal lines 211 and 212, the sources of the MOS transistors constituting the switches 202 and 203 exist as diodes, and junction leakage of the diodes becomes a leakage current.

In order to completely remove the potential drop ΔV _drp due to the leak current, it is necessary to match the potential drop on the signal line 211 (signal V _m ) with the potential drop on the signal line 212 (signal V _out ). When the leakage current of the signal line V (x) is I _d (x) and the capacitance is C (x), the potential drop ΔV (x) at time t is
ΔV (x) = I _d (x) · t / C (x) (Equation 7)

FIG. 3 shows the area relationship of signal line portions used in the correlated double sampling circuit, 300 is a p-type semiconductor substrate, 301 is a gate of a MOS transistor constituting each switch, 302 is a junction of the MOS transistor, Reference numeral 303 denotes a signal line. As shown in FIG. 3, when the junction area is S _J (x) and the gate area is S _C (x), I _d (x) and C (x) represent the junction leakage current per unit area as a _1. When the junction capacitance per unit area is b ₁ and the gate capacitance is b ₂ ,
I _d (x) = a ₁ S _J (x) ………………………………… (Formula 8)
C (x) = b ₁ S _J (x) + b ₂ S _C (x) (Equation 9)
= (B ₁ + b ₂ c ₀ ) S _J (x) ……………………… (Equation 10)
However, c ₀ = S _C (x) / S _J (x) (Equation 11)
It becomes.

a ₁ , b ₁ , b ₂ are generally constant values, and c ₀ is constant in area ratio.
ΔV (x) = constant …………………………………… (Formula 12)
It becomes.

That is, if the ratio of the junction area and the gate area is made substantially the same in the signal line 211 (signal V _m ) and the signal line 212 (signal V _out ), ΔV _drp is completely removed. In FIG. 1, when the ratio of the junction area of the signal line 211 (signal V _m ) is smaller than that of the signal line 212 (signal V _out ), the dummy junction 210 (indicated by the dotted line) is used to make the ratio of the junction area and the gate area substantially the same. Is required).

Thus, the period 1 by the first CDS operation of switching the input selector switch 200 to the vertical signal line 145 side, the net as a difference between the first half period signal and the second half period signal of the signal V _in the vertical signal line 145 side Is obtained by the sample hold capacitor 204, and the second CDS operation in the second period 2 in which the input changeover switch 200 is switched to the fixed potential side includes the same feedthrough level as the first CDS operation. A reference signal is obtained at the sample and hold capacitor 204. Thereafter, by taking the difference between the signals held in the sample hold capacitor 204 before and after the second sample hold operation, only a net signal component in which all the feedthrough levels generated in the CDS operation are canceled is obtained. Therefore, by applying this correlated double sampling circuit to the amplification type solid-state imaging device, it is possible to greatly reduce the FPN associated with the horizontal pixel selection with a simple configuration, and to reduce the shading-like nonuniformity. High quality images can be obtained.

  Further, by setting the capacitance of the clamp capacitor 201 to 10 times or more of the capacitance of the sample hold capacitor 204, the gain when the signal passing through the clamp capacitor 201 is accumulated in the sample hold capacitor 204 can be increased.

Further, the ratio of the junction area to the gate area of the MOS transistor of the clamp switch 202 and the ratio of the junction area to the gate area of the MOS transistor of the sample hold switch 203 are made substantially the same, whereby the signal line 211 is obtained. (Signal V _m ) and signal line 212 (signal V _out ) make the potential drop due to the leak current of the MOS transistor equal in each signal line 211, 212, and the potential drop due to the leak current of the MOS transistor is reliably removed by the CDS operation. be able to.

(Second Embodiment)
FIG. 4 shows a circuit diagram of an amplification type solid-state imaging device according to the second embodiment of the present invention. 4, the two-dimensional pixel region has the same configuration as the two-dimensional pixel region 140 shown in FIG. 17, and the two-dimensional pixel region is not shown and described. In the following, a signal path circuit after the vertical signal line 145 is used. Will be described. This amplification type solid-state imaging device has the same components as the correlated double sampling circuit shown in FIG. 1 except for the timing generation circuit, and the same components are denoted by the same reference numerals and description thereof is omitted. .

As shown in FIG. 4, in the amplification type solid-state imaging device, the other end of the signal line 212 having one end connected to the sample hold switch 203 is connected to an input terminal of an amplifier circuit 155 as an amplifying unit. The output terminal of the amplifier circuit 155 is connected to the horizontal signal line 164 via the horizontal selection switch 156. The output line 161 from the horizontal scanning circuit 160 is connected to the control input terminal of the horizontal selection switch 156. Further, the output terminal of the sample hold switch 207 is connected to the control input terminal of the sample hold switch 203, and the pulse φ _SA as the first control signal is input to one input terminal of the sample hold switch 207, An output terminal of an AND (logical product) circuit 205 is connected to the other input terminal of the sample hold changeover switch 207 via a signal line 208. A pulse φ _SH is input to one input terminal of the AND circuit 205, and a pulse φ _H (j) as a second control signal is output from the horizontal scanning circuit 160 to the other input terminal of the AND circuit 205 via the output line 161. And the pulse φ _Sj is output from the AND circuit 205. Further, the input terminal of the CDS circuit 168 is connected to the end of the horizontal signal line 164, the output terminal of the CDS circuit 168 is connected to the input terminal of the amplifier circuit 169, and the signal OS is output from the amplifier circuit 169. This amplification type solid-state imaging device has a timing generation circuit 214 as a control means for outputting pulses φ _SH , φ _SA , φ _SW2 , φ _CA , φ _SW , a clamp pulse φ _C2 and a sample hold pulse φ _S2. ing.

In FIG. 4, the switching of the input changeover switch 200 of the correlated double sampling circuit for each vertical signal line 145 is controlled by a pulse φ _SW , and the signal or fixed potential of the vertical signal line 145 is controlled by the input changeover switch 200 and the clamp capacitor 201. To the sample hold switch 203. Then, the clamp switch 202 is controlled by the pulse φ _{CA and} the output side of the clamp capacitor 201 is connected to the clamp potential V _CP via the clamp switch 202 to perform a clamp operation. Next, the sample hold switch 203 is controlled by the pulse φ _Sj, and the signal from the sample hold switch 203 is held in the sample hold capacitor 204 to perform the sample hold operation. The signal held in the sample hold capacitor 204 is amplified by the amplifier circuit 155, and the amplified signal is guided to the horizontal signal line 164 via the horizontal selection switch 156. Then, after the signal guided to the horizontal signal line 164 is processed by the CDS circuit 168, the signal OS is output from the amplifier circuit 169.

The operation of the amplification type solid-state imaging device having the above configuration is shown in the timing charts of FIGS. As shown in FIG. 5, by setting the pulse φ _sw to the high level within the horizontal blanking period as the first period (shown in FIG. 5B), the clamp capacitor 201 is connected via the input changeover switch 200. Connect to the vertical signal line 145. Then, the pulse φ _{CA is set} to the high level at time t ₁ within _one readout period of the light reception signal or reference signal from the pixel (indicated by S ₁ in the signal V ₁ in FIG. 5A) (FIG. 5). 5 (c)), the clamp operation to the clamp potential is performed. Further, the pulse φ _{SA is set} to the high level at time t ₂ within the other readout period of the light reception signal or the reference signal from the pixel element (not shown) (indicated by S ₂ in the signal V ₁ in FIG. 5A). (Shown in FIG. 5D), the sample and hold operation is performed. As described above, the difference between the light reception signal from the pixel element and the reference signal is held in the sample hold capacitor 204.

Next, at the end of the horizontal blanking period, the pulse φ _{sw is set} to the low level (shown in FIG. 5B), and the input changeover switch 200 is connected to the fixed potential (ground GND), and then the pulse φ _{CA at} time t ₃ . By turning on the clamp input changeover switch 200 again, the clamp potential V _CP is held on the output side of the clamp capacitor 201. In the horizontal effective period as the second period, the pulses φ _H (j), φ _H (j + 1), φ _H (j + 2),... (Shown in FIGS. 5E to 5G). ), The horizontal selection switch 156 is sequentially turned on for each vertical signal line 145, and the output of the amplifier circuit 155 is read to the horizontal signal line 164. At time t _J (j = 4, 5,...) In the middle of each readout period, pulses φ _H (j), φ _H (j + 1), φ _H (j + 2) _,. Sample hold switch (shown in FIGS. 5 (i) to (k)) by pulses φ _S (j), φ _S (j + 1), φ _S (j + 2),. 203 performs the second sample operation. As a result, the signal V _sr output from each amplifier circuit 155 to the horizontal signal line 164 becomes a signal that represents the difference between the light reception signal from the pixel element and the reference signal in the first half by the amount of displacement from the clamp potential V _CP . The clamp potential V _{CP held} by the clamp capacitor 200 in the latter half is obtained (shown in FIG. 5 (l)). These are represented by the first output signal _Sa and the second output signal _Sb in FIG. Thereafter, the clamp pulse phi _C2 and a sample hold pulse phi _S2 of CDS circuit 168 (FIG. 5 (m), shown in (n)), the difference between the first output signal S _a and the second output signal S _b is obtained The signal OS is output via the buffer amplifier 169.

The amplification type solid-state imaging device of the second embodiment of the present invention has the same operations and effects as the correlated double sampling circuit of the first embodiment. That is, by replacing the input signal Vin _in FIG. 1 of the first embodiment with V ₁ , the signal V _m of the signal line 211 with V ₂ , and the signal V _out of the signal line 212 with V _sr , The first and second output signals S _a and S _b are expressed by (Equation 4) and (Equation 5) as in FIG. Therefore, if the difference between the first output signal S _a and the second output signal S _b is obtained by the CDS circuit 168 provided in the horizontal signal line 164, the signal OS becomes OS = S _a − as in the above (formula 6). S _b = kV _s , so that not only the variation of each amplifier circuit 155 is removed, but also the field through level ΔV _CP of the clamp pulse and the field through level ΔV _SH of the sample hold pulse are removed, and the potential drop due to the leakage current is further removed. Only the net signal V _s from which ΔV _drp has also been removed is obtained. That is, an extremely high image quality image signal from which the FPN is almost completely removed can be obtained.

Further, in order to completely remove the potential drop ΔV _drp due to the leakage current, the method of _{combining the} potential drop of the signal V _{2 on} the signal line 211 and the potential drop of the signal V _{3 on} the signal line 212 is the same as in the case of FIG. It is. That is, if the ratio between the junction area and the gate area is made substantially the same between the signal line 211 (signal V ₂ ) and the signal line 212 (signal V ₃ ), ΔV _drp is completely removed. In FIG. 4, when the ratio of the junction area of the signal line 211 (signal V ₂ ) is smaller than that of the signal line 212 (signal V ₃ ), the dummy junction 210 (indicated by the dotted line) is used to make the ratio of the junction area and the gate area substantially the same. Is required).

  As described above, after obtaining the difference between the light reception signal of the pixel element and the reset signal on the input side of the amplifier circuit 155 for each vertical signal line 145 by the first CDS operation in the horizontal blanking period as the first period. After the second CDS operation in the horizontal effective period as the second period, a reference signal (clamp potential) including the same feed-through level as the first CDS operation is input to the amplifier circuit 155, and then the horizontal signal line 164 By taking the difference between the difference signal and the reference signal by the CDS operation of the CDS circuit 168 connected to the terminal of the signal, only the net signal component in which all the feedthrough levels are canceled can be obtained. Therefore, it is possible to realize an amplification type solid-state imaging device that can greatly reduce FPN associated with horizontal pixel selection, reduce shading-like non-uniformity, and obtain a high-quality image without FPN with a simple configuration. it can.

(Third embodiment)
FIG. 6 shows a circuit diagram of an amplification type solid-state imaging device according to the third embodiment of the present invention. This amplifying solid-state imaging device has the same configuration as that of the amplifying solid-state imaging device of the second embodiment except for the OR circuit 301, and the same components are denoted by the same reference numerals and description thereof is omitted. Although omitted in FIG. 4 of the second embodiment, as shown in FIG. 6, a constant current load 304 is connected between the horizontal signal line 164 and the ground GND.

As shown in FIG. 6, an OR circuit 301 is added to the output line 161 from the horizontal scanning circuit 160, the signal line 161 is connected to one input terminal of the OR circuit 301, and the other of the OR circuit 301 is connected. The pulse φ _SW is input to the input terminal, and the output terminal of the OR circuit 301 is connected to the signal line 302. The logical sum circuit 301 calculates the logical sum of the pulse (φ _H (j), φ _H (j + 1),...) Of the signal line 161 and the pulse φSW, and outputs a pulse (φ _HA (j), φ _HA (j + 1),...) are input to the control input terminal of the horizontal selection switch 156 via the signal line 302.

The operation of the amplification type solid-state imaging device is shown in the timing chart of FIG. FIG. 7 differs from FIG. 5 in the second embodiment only in the pulses φ _HA (j), φ _HA (j + 1) _,. That is, these pulses φ _HA (j), φ _HA (j + 1),... _Are ORed with the pulses φ _H (j), φ _H (j + 1) _,. Therefore, the waveforms are as shown in FIGS. Therefore, the horizontal selection switch 156 that reads the signal of the amplifier circuit 155 to the horizontal signal line 164 is simultaneously turned on in the first period (horizontal blanking period) and sequentially turned on in the second period (horizontal effective period). Become. This has the following characteristics when viewed from the CDS circuit side.

  The amplification type solid-state imaging device of the third embodiment is characterized in that the sample and hold operation is performed twice for each vertical signal line 145, once in the first period and once in the second period. That is, as shown in FIGS. 7 (i) to (k), each of the sample and hold switches 203 is turned on twice. At this time, the difference between the pixel signal and the reference signal is held at the first time, and the clamp potential signal as the reference signal is held at the second time. Therefore, it is desirable that the conditions be the same as much as possible in the two operations. In the case of the second embodiment shown in FIGS. 4 and 5, the horizontal selection switch 156 is turned off for the first sample hold operation, and the horizontal selection switch 156 is turned on for the second sample hold operation. The state of was different. On the other hand, in the third embodiment, the horizontal selection switch 156 is turned on for the first and second sampling and holding operations, and in either case, the output of the amplifier circuit 155 passes through the horizontal selection switch 156 to the horizontal signal line. 164, the state on the load side of the sample and hold switch 203 is the same. For example, when the amplifier circuit 155 is a source follower circuit, the input gate capacitance changes greatly when the horizontal selection switch 156 is turned on / on, and when it is turned on, a channel is formed under the input gate, and the input gate capacitance increases. When off, no channel is formed and the input gate capacitance is reduced. That is, if the horizontal selection switch 156 is turned on in both operations, the operating conditions are completely the same. Thereby, FPN and shading-like nonuniformity can be reduced more completely.

  In the third embodiment, the horizontal selection switch 156 is turned on at the same time in the first period (horizontal blanking period). However, the horizontal selection switch 156 is in a period during which at least the sample hold switch 203 is turned on in the first period. 156 may be turned on at the same time.

(Fourth embodiment)
FIG. 8 shows a circuit diagram of an amplification type solid-state imaging device according to the fourth embodiment of the present invention. This amplification type solid-state imaging device has the same configuration as the amplification type solid-state imaging device of the third embodiment except for the load connection switch 303 and the constant current load 304, and the same components are denoted by the same reference numerals. Description is omitted.

As shown in FIG. 8, a constant current load 304 is connected between the horizontal signal line 164 and the ground GND via a load connection switch 303. A pulse φ _LG is input to the control input terminal of the load connection switch 303.

The operation of the amplification type solid-state imaging device is shown in the timing chart of FIG. 9 differs from FIG. 5 in the second embodiment only in that a pulse φ _LG for driving the load connection switch 303 is added. That is, within the horizontal blanking period, the pulse φ _LG is turned off during the period in which the horizontal selection switches 156 are simultaneously turned on by the pulses φ _HA (j), φ _HA (j + 1),. 303 is turned off, and the current from the constant current load 304 does not flow through the horizontal signal line 164. On the other hand, in the horizontal effective period, the pulse _{φ HA (j), φ HA} (j + 1), within the time each horizontal selection switch 156 is respectively turned on by ..., pulse phi _LG is turned on, the load connection switch 303 Is turned on, and the current from the constant current load 304 flows through the horizontal signal line 164.

  As described above, in the fourth embodiment, it is desirable that the two conditions be as much as possible in the two sample-and-hold operations. In the case of FIG. 6 of the third embodiment, during the first sample and hold operation, the outputs of all the amplifier circuits 155 are simultaneously connected to the horizontal signal line 164 via the horizontal selection switch 156, while the load by the constant current load 304 Since the current is constant, if there is a large level difference in output on the amplifier circuit side, interference may occur between them. For this reason, in the third embodiment, the hold capacitor 204 on the input side of the amplifier circuit 155 is also affected, and it may be difficult to perform the sample and hold operation independently in each column.

  On the other hand, in the amplification type solid-state imaging device of the fourth embodiment, as shown in FIGS. 9 and 10, the outputs of all the amplifier circuits 155 are set to the horizontal selection switch 156 at the same time during the first sample hold operation. Since the load current due to the constant current load 304 does not flow by turning off the load connection switch 303 when connected to the horizontal signal line 164 through the amplifier circuit 155, they interfere with each other even if there is a large level difference in output between the amplifier circuits 155. It does not occur. Therefore, the hold capacitor 204 on the input side of the amplifier circuit 155 is not affected, and the sample and hold operation can be independently performed in each column. That is, the correct sample and hold operation can be performed in both operations, and the nonuniformity of FPN and sharding can be more completely reduced.

(Fifth embodiment)
FIG. 10 shows a circuit diagram of an amplification type solid-state imaging device according to the fifth embodiment of the present invention. This amplifying solid-state imaging device has the same configuration as that of the amplifying solid-state imaging device of the second embodiment except for the logical product circuit 401, and the same components are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 10, an AND circuit 401 is added to the output line 161 from the horizontal scanning circuit 160, the signal line 161 is connected to one input terminal of the AND circuit 401, and the other of the AND circuit 401 is connected. An inversion signal of the pulse φ _SH is input to the input terminal of, and the output terminal of the AND circuit 401 is connected to the signal line 302. Then, the logical product 401 calculates the logical product of the pulse (φ _H (j), φ _H (j + 1),...) Of the signal line 161 and the inverted signal of the pulse φ _SH , and represents the calculation result. Pulses φ _HB (j), φ _HB (j + 1),... Are input to the control input terminal of the horizontal selection switch 156 via the signal line 402.

The operation of the amplification type solid-state imaging device is shown in the timing chart of FIG. FIG. 11 differs from FIG. 5 in the second embodiment only in the pulses φ _HB (j), φ _HB (j + 1) _,. That is, in these signals, the logical product of the pulses φ _H (j), φ _H (j + 1),... And the inverted signal of the pulse φ _SH is obtained. The waveform is as shown. Therefore, the horizontal selection switch 156 that reads the signal of the amplifier circuit 155 to the horizontal signal line 164 is turned off in the first period (horizontal blanking period) and sequentially turned on in the second period (horizontal effective period). Is turned off only when the sample hold switch 203 is turned on. When viewed from the previous CDS circuit side, this has the following characteristics as in the case of FIGS.

  As already described, in the fifth embodiment, it is desirable that the same conditions are as much as possible in the two sample-and-hold operations. 10 and 11, the horizontal selection switch 156 is turned off both in the first time and the second time in which the sample hold switch 203 is turned on, and in either case, the output of the amplifier circuit 155 is supplied to the horizontal signal line via the horizontal selection switch 156. 164, the load-side state of the sample hold switch 203 is the same. That is, if the horizontal selection switch 156 is off in both operations, the operating conditions are completely the same. Thereby, FPN and shading-like nonuniformity can be reduced more completely.

FIGS. 12 and 13 show configuration examples of the CDS circuit 168 in FIGS. 4, 6, 8, and 10. FIG. 12 shows a CDS circuit in which a clamp circuit 21 as a second clamp means to which a signal V _SR is inputted and a sample hold circuit 22 as a second sample hold means are combined, and the clamp circuit 21 is controlled by a clamp pulse φ _C2. The sample and hold circuit 22 is controlled by the sample and hold pulse φ _S2 . The timings of the clamp pulse φ _C2 and the sample hold pulse φ _S2 are as shown in FIGS. By the CDS circuit, the difference between the light reception signal and the reference signal from the difference signal or pixel elements of a pair of first output signal S _a and the second output signal S _b read out to the horizontal signal line 164 is obtained. FIG. 13 shows a CDS circuit in which two sample hold circuits 31 and 32 as third and fourth sample hold means to which a signal V _SR is inputted and a differential amplifier 33 as a calculation means are combined. The hold circuits 31 and 32 are controlled by sample and hold pulses φ _S3 and φ _S4, respectively. The timings of the sample hold pulses φ _S3 and φ _S4 correspond to φ _C2 and φ _S2 in FIGS. The configuration taking the difference between the outputs of the sample-and-hold circuits 31 and 32 by the differential amplifier 33, i.e., the difference signal between the pair of first output signal S _a and the second output signal S _b read out to the horizontal signal line 164 A difference between the light reception signal from the pixel element and the reference signal is obtained. These 15, the CDS circuit shown in FIG. 16, the difference signal between the first output signal S _a and the second output signal S _b is formed, a signal OS representing an image without any variation components are removed FPN Obtainable.

Furthermore, the horizontal blanking ranking sample hold changeover switch 207 in the second half of the period is switched to the pulse phi _SH side as a first control signal, the period to the sample hold changeover switch 207 by the horizontal selection switch 156 to conduct in the horizontal effective period By switching to the pulse side as the second control signal, the sample hold switch 203 can be controlled for each vertical signal line 145 in which the horizontal selection switch 200 is sequentially turned on with a simple configuration.

FIG. 1 is a circuit diagram of a correlated double sampling circuit according to the first embodiment of the present invention. FIG. 2 is a timing chart of the correlated double sampling circuit. FIG. 3 is a diagram showing the area relationship of the signal line portion of the correlated double sampling circuit. FIG. 4 is a circuit diagram of an amplification type solid-state imaging device according to the second embodiment of the present invention. FIG. 5 is a timing chart showing the timing of each signal of the amplification type solid-state imaging device. FIG. 6 is a circuit diagram of an amplification type solid-state imaging device according to the third embodiment of the present invention. FIG. 7 is a timing chart showing the timing of each signal of the amplification type solid-state imaging device. FIG. 8 is a circuit diagram of an amplification type solid-state imaging device according to the third embodiment of the present invention. FIG. 9 is a timing chart showing the timing of each signal of the amplification type solid-state imaging device. FIG. 10 is a circuit diagram of an amplification type solid-state imaging device according to the third embodiment of the present invention. FIG. 11 is a timing chart showing the timing of each signal of the amplification type solid-state imaging device. FIG. 12 is a block diagram of a correlated double sampling circuit combining a clamp circuit and a sample hold circuit. FIG. 13 is a block diagram of a correlated double sampling circuit in which two sample and hold circuits are combined. FIG. 14 is a circuit diagram illustrating a conventional horizontal pixel. FIG. 15 is a circuit diagram illustrating a conventional vertical pixel. FIG. 16 is a block diagram schematically showing the circuits of FIGS. FIG. 17 is a circuit diagram showing a conventional amplification type solid-state imaging device. FIG. 18 is a circuit diagram showing another conventional amplification type solid-state imaging device. FIG. 19 is a circuit diagram showing another conventional amplification type solid-state imaging device. FIG. 20 is a diagram for explaining the problems of the conventional amplification type solid-state imaging device.

Explanation of symbols

145: Vertical signal line, 155, 169: Amplifier circuit, 160: Horizontal scanning circuit, 168: CDS circuit, 200: Input switch, 201: Clamp capacitor, 202: Clamp switch, 203: Sample hold switch, 204: Sample hold Capacitor 205 ... AND circuit 206 ... Clock line 207 ... Sample hold changeover switch 210 ... Dummy junction

Claims (12)

A signal line is connected to one input terminal, a fixed potential is applied to the other input terminal, and an input selector switch that selects and outputs either the signal of the signal line or the fixed potential;
A clamp capacitor having one end on the input side connected to the output terminal of the input selector switch, and a clamp switch having one end connected to the other end on the output side of the clamp capacitor and the other end connected to a clamp potential. One clamping means;
A first sample and hold means having a sample and hold switch having one end connected to the other end of the clamp capacitor; and a sample and hold capacitor having one end connected to the other end of the sample and hold switch;
In the first period, the input selector switch is switched to the signal line side, and the signal on the signal line is clamped by the first clamping means in the first half of the first period, and then the second half of the first period. The signal on the output side of the clamp capacitor is sampled and held by the first sample hold means, and the input changeover switch is switched to the fixed potential side in the second period following the first period. The clamp potential with respect to the fixed potential is sampled and held on the output side of the clamp capacitor by the first clamp means in the first half of the period 2, and the signal on the output side of the clamp capacitor is then sampled by the first sample hold means. The input selector switch, clamp switch and sample hold switch A correlated double sampling circuit comprising control means for controlling the control. The correlated double sampling circuit according to claim 1,
The correlated double sampling circuit, wherein the capacitance of the clamp capacitor is 10 times or more the capacitance of the sample and hold capacitor. The correlated double sampling circuit according to claim 1 or 2,
The clamp switch and the sample hold switch are each composed of a MOS transistor,
A correlated double sampling circuit characterized in that the ratio of the junction area of the clamp switch to the capacitance of the clamp capacitor is substantially the same as the ratio of the junction area of the sample and hold switch to the capacitance of the sample and hold capacitor. . An amplifying pixel element that amplifies and outputs a photoelectric conversion means, a light reception signal formed by the photoelectric conversion means and a reference signal serving as a reference of the light reception signal, and a vertical signal line to which the output of the pixel element is connected And amplifying means for amplifying the signal of the vertical signal line, and a horizontal signal line to which the output of the amplifying means is connected via a horizontal selection switch, and the signal of the pixel element is the vertical signal line and amplifying means. In an amplification type solid-state imaging device that transmits to a horizontal signal line via a horizontal selection switch,
4. An amplification type solid-state imaging device, wherein the correlated double sampling circuit according to claim 1 is provided between the vertical signal line and the amplification means. The amplification type solid-state imaging device according to claim 4,
In the first period, the input selector switch is switched to the vertical signal line side, and one of the light reception signal or the reference signal of the pixel element is clamped by the first clamp means in the first half period of the first period. Then, in the latter half of the first period, the other of the light reception signal or the reference signal of the pixel element is sampled and held by the first sample-and-hold means via the clamp capacitor. After holding the signal representing the difference between the received light signal and the reference signal by the amount of displacement from the clamp potential in the sample and hold capacitor,
In the second period, the input changeover switch is switched to the fixed potential side, and the clamp potential is set to the fixed potential at the beginning of the second period, and the clamp capacitor outputs the clamp capacitor to the output side of the clamp capacitor. In the first half of the period during which the horizontal selection switch is turned on and the output signal of the amplification means is read out to the horizontal signal line, the difference between the light reception signal from the pixel element and the reference signal is calculated from the clamp potential. After the first output signal represented by the displacement amount is output to the horizontal signal line through the amplification means, the signal on the output side of the clamp capacitor is sampled and held by the first sample hold means, and after the sample hold The second output signal that becomes the clamp potential in the second half of the conduction period of the horizontal selection switch Amplifying solid-state imaging device and outputting to the horizontal signal line via a. The amplification type solid-state imaging device according to claim 5,
The first output signal of the set of the first output signal and the second output signal from the horizontal signal line is clamped, and the first output signal and the second output are output during the period of the second output signal. Second clamping means for outputting a difference signal from the signal;
An amplification type solid-state imaging device comprising: second sample hold means for sampling and holding the difference signal from the second clamp means and outputting the sampled and held difference signal. The amplification type solid-state imaging device according to claim 5,
Third sample and hold means for sampling and holding the first output signal of the set of the first output signal and the second output signal from the horizontal signal line;
A fourth sample and hold means for sampling and holding the second output signal of the set of the first output signal and the second output signal from the horizontal signal line;
An arithmetic means for obtaining a difference signal between the first output signal held by the third sample hold means and the second output signal held by the fourth sample hold means and outputting the difference signal; An amplification type solid-state imaging device comprising: The amplification type solid-state imaging device according to any one of claims 4 to 7,
The control means outputs a first control signal that is turned on in the second half of the first period, and a second control signal that is turned on while the horizontal selection switch in the second period is conductive. ,
The first control signal is input to one input terminal, the second control signal is input to the other input terminal, and an output terminal is connected to the control input terminal of the sample hold switch of the first sample hold means An amplification type solid-state imaging device comprising a sample hold changeover switch. The correlated double sampling circuit according to claim 1 or 2,
The clamp switch and the sample hold switch are each composed of a MOS transistor,
The correlated double sampling characterized in that the ratio of the junction area to the gate area of the MOS transistor of the clamp switch is substantially the same as the ratio of the junction area to the gate area of the MOS transistor of the sample and hold switch. circuit. The amplification type solid-state imaging device according to claim 5,
All the horizontal selection switches are in a conductive state in a period of sample holding by the first sample hold means within the first period,
The horizontal selection switch connected to the first sample hold means is in a conductive state during a period in which the signal on the output side of the clamp capacitor within the second period is sampled and held by the first sample hold means. A feature of the amplification type solid-state imaging device. The amplification type solid-state imaging device according to claim 10,
A constant current load connected to the horizontal signal line via a load connection switch,
An amplification type solid-state imaging device, wherein the load connection switch is in an OFF state during a period in which at least all the horizontal selection switches are in a conductive state. The amplification type solid-state imaging device according to claim 5,
All the horizontal selection switches are in a non-conducting state in at least a period of sample holding by the first sample hold means in the first period,
The horizontal selection switch connected to the first sample hold means is in a non-conductive state during a period in which the signal on the output side of the clamp capacitor within the second period is sampled and held by the first sample hold means. An amplification type solid-state imaging device characterized by the above.

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