JPH01112837A - Sub-signal synchronism detecting circuit - Google Patents

Abstract

PURPOSE:To remove influence due to the transmission error of a main signal, and to prevent an sub-signal from being disconnected prior to the main signal by separating an input signal into the main signal and a coding rule violation signal including the sub-signal, and extracting only a coding violation bit due to the sub-signal out of the coding rule violation signal, and establishing synchronism by a synchronism detecting means. CONSTITUTION:The coding rule violation signal inputted to an auxiliary signal extracting part 20a consists of the coding rule violation bit due to the sub-signal and the coding rule violation bit due to the transmission error. A through signal generated from a through signal generation circuit 23 has the same period as the coding rule violation bit due to the sub-signal. An AND circuit 22 takes the logical product of the coding rule violation signal and the through signal, and extracts only the coding rule violation bit due to the sub-signal, and makes it be the set signal of an F.F circuit 32. On the other hand, the timer signal of the same period as the through signal, which a timer circuit 31 generates, goes to the reset signal of the F.F circuit 32, and the set and the reset of the F.F circuit 32 are repeated. A synchronism protection circuit 33 performs the synchronizing processing of the sub-signal by using the signal to express the repeat of the set and the reset without being influenced by the coding rule violation bit due to the transmission error.

Description

[Detailed Description of the Invention] [Summary] Regarding a sub-signal synchronization detection circuit for extracting a sub-signal that transmits a predetermined bit in a main signal as a code violation bit, The purpose is to provide a sub-signal synchronization detection circuit that eliminates the effects of transmission errors and prevents the sub-signal from being cut off before the main signal. A signal that separates the main signal and the coding rule violation signal from the input signal in a transmission device that periodically superimposes sub-signals transmitted via a maintenance line and converts the superimposed bit position into a coding rule violation signal. Separation means, sub-signal extracting means for performing processing for extracting a sub-signal from the coding rule violation signal separated from the signal-separating means, and synchronization detection means for detecting synchronization of the sub-signals extracted from the sub-signal extracting means. and constituted.

[Industrial application field]

The present invention relates to a sub-signal synchronization detection circuit for extracting a sub-signal that transmits a predetermined bit in a main signal as a code violation bit.

Normally, the signals processed by the transmission equipment system include main signals, such as data signals and audio signals, which are transmitted via lines that mainly supply to users, and main signals, such as monitoring signals and control signals, which are transmitted via maintenance lines. There is a sub-signal that is transmitted.

One of the methods for transmitting these two signals is a method in which a sub-signal is superimposed on a main signal transmitted according to a predetermined coding rule, and the signal is transmitted as a signal in which a coding rule violation occurs at an n-bit period.

In such a system, it is necessary to establish synchronization of the sub-signal even if synchronization processing of the main signal becomes impossible due to frequent transmission errors, etc., and to prevent the sub-signal from being disconnected before the main signal.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, FIG. 5 is a diagram illustrating a sub-signal synchronization detection situation in the conventional example, and FIG. 6 is a diagram illustrating a sub-signal superimposition situation.

As shown in FIG.
The predetermined bit position (a) of the main signal (main signal transmitted according to the MI coding rule) is a bit position at which the sub signal is made into a coding rule violation signal and is superimposed on the sub signal.

When receiving and processing a signal in which a sub signal is superimposed on a main signal in this way, it is necessary to synchronize the receiving process, and FIG. 4 shows a conventional example of a circuit that performs synchronization detection of the sub signal.

That is, the decoder circuit 1 separates the main signal 0 and the sign rule violation signal ■ from the input signal [phase] obtained by superimposing the sub signal on the main signal, and connects them to the sub signal mask section 2. The sub-signal masking section 2 masks periodic bit positions (ie, positions corresponding to the sub-signal) in the code rule violation signal (2), and sends the signal (2) to the synchronization detection section 3.

Incidentally, the coding rule violation signal ``■'' in which the coding rule violation bit corresponding to the sub-signal is masked is, for example, an error signal generated during transmission, and is used to detect the synchronization of the sub-signal.

FIG. 4 shows the configuration of a conventional example of the sub-signal mask section 2 and the synchronization detection section 3, and FIG. 5 is a diagram explaining the time chart in FIG. 4.

That is, the sub signal masking section 2 includes an inhibit signal generating circuit 21 that generates a signal corresponding to the coding rule violation bit period due to the superposition of the sub signal in the coding rule violation signal ■ in response to the output of the synchronization detection section 3; Violation signal■ and inhibit signal■
It consists of an AND circuit (hereinafter referred to as an AND circuit) 22 that calculates the AND circuit.

In addition, the synchronization detection unit 3 is set by a timer circuit 31 that generates a timing signal ■ having a period corresponding to the coding rule violation bit period due to the superposition of the sub signal in the coding rule violation signal ■, and an output signal ■' of the AND circuit 22. A set-reset type 79717 that is reset by the timing signal ■
071 circuit (hereinafter referred to as F, F circuit) 32 and F, F
The synchronization protection circuit 33 establishes synchronization of the sub-signals depending on the state of the positive output signal (2) of the circuit 32.

Immediately before the timing signal ■ is input, the synchronization protection circuit 33
When the positive output signal ■ of the F, F circuit 32 is "I(", hunting processing is performed as out of synchronization, and when it is "L", it is recognized as being in a synchronized state. ゛The situation is shown in Fig. 5. .

In other words, in FIG. 5(A), there is no error occurring in the transmission path,
This is a case where the sign rule violation signal ■ is only caused by sub-signal superimposition, and in this case, the output signal ■ of the AND circuit 22
' is "L", so the positive output signal (2) of the F, F circuit 32 always maintains the "L" state.

Therefore, the signal ■ immediately before the timing signal ■ is generated from the timer circuit 31 is always "L", and the synchronization protection circuit 33
is recognized as being in sync.

That is, when the sub-signals are in a synchronous state, the AND circuit 22 completely masks the coding rule violation signal (2) with the inhibit signal (2) generated from the inhibit signal generating circuit 21. When the unmasked coding rule violation signal (■) is output, the synchronization protection circuit 33 recognizes it as an asynchronous state after a predetermined stage of protection processing, performs hunting processing, and sends a predetermined signal to the inhibit signal generation circuit 21 to inhibit the signal. The phase of the inhibit signal (2) from the signal generation circuit 21 is shifted by several bits and sent to the AND circuit 22 to establish synchronization.

On the other hand, FIG. 5(B) shows a synchronization establishment state when there is a code error in the transmission path. That is, the white bits (these are the bits that violate the coding rules due to the sub-signals) in the coding rule violation signal are masked by the AND circuit 22 in the same way as above, but the pulses in the shaded areas (which are the error pulses on the transmission path) are not masked. to F
, F circuit 32.

The signal ``■'' in the shaded area sets the F, F circuit 32, so the positive output signal ``■'' of the F, F circuit 32 is "H" before the timer pulse ``■'' is output from the timer circuit 31. The synchronization protection circuit 33 performs a predetermined level of protection processing and hunting processing regardless of whether or not the sub-signal is in a synchronous state.

In general, the error rate of the main signal is about 10-3, and the error rate of the sub-signal is about 10-1.

[Problem that the invention seeks to solve]

When detecting the synchronization of the sub signals using the above method, if a transmission error occurs in the main signal, the probability that the positive output signal ■ of the F, F circuit 32 is “■]” before the timer pulse ■ is output is becomes high, and the synchronization protection circuit 33 performs hunting processing even though the sub-signals are in a synchronous state, causing a problem in that the sub-signals are not transmitted during this period.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sub-signal synchronization detection circuit that eliminates the influence of main signal transmission errors when detecting sub-signal synchronization and prevents the sub-signal from being disconnected before the main signal.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 10 is a signal separation means for separating the main signal ■ and the sign rule violation signal ■ from the input signal [phase] having a predetermined sign rule, and 20 is a signal separation means 30 is a sub-signal extracting means that performs processing for extracting a sub-signal from the code rule violation signal 1 separated from the sub-signal extracting means 20, and 30 is a synchronization detecting means for detecting the synchronization of the sub-signal extracted from the sub-signal extracting means 20. Therefore, the present invention is a means for solving this problem by providing an engaging means.

[For production]

The input signal [phase] transmitted with a predetermined code rule is separated by the signal separation means 10 into a main signal (■) consisting of data, voice, etc.
The code rule violation signal ■, which includes the monitoring signal and the sub-signal passing through the maintenance line, is separated from the code rule violation signal ■ by the sub-signal extraction means 20.
By extracting only the code violation bit caused by the sub signal and sending it to the synchronization detection means 30 to establish synchronization, the influence of transmission errors of the main signal is eliminated, and the sub signal is detected before the main signal. is prevented from becoming disconnected.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating a time chart in an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 includes a decoder circuit l having the same function as that explained in FIG. 4 as the signal separating means 10 explained in FIG. A sub-signal extraction unit 20 consisting of an AND circuit 22 similar to that explained in the figure, and a through signal generation circuit 23 that generates a signal ■ that allows the bits violating the coding rule caused by the sub signal to pass through in the AND circuit 22.
a. As the synchronization detection means 30, a timer circuit 31 having the same function as that explained in FIG. Set-reset type F,
F circuit 32. This is an example in which a synchronization detection circuit 30a includes a synchronization protection circuit 33 that performs multi-stage synchronization protection processing to establish synchronization.

Note that the synchronization state is recognized by the synchronization protection circuit 33.
, the signal ■' output from the F circuit 32 is sent to the timer circuit 31.
This is a time chart that shows the processing status when the timer signal ■ that is generated is "L" just before input, and when it is "H", hunting processing is entered as out of synchronization, and the through signal is generated. The coding rule violation signal {circle around (2)} inputted to the extractor 20a consists of coding rule violation bits due to sub-signals (white areas in the figure) and coding rule violation bits due to transmission errors (hatched areas in the figure).

As shown in the figure, the through signal (2) generated by the through signal generating circuit 23 generates a signal having the same period as the code rule violation bit (the white part in the figure) caused by the sub signal.

The through signal generation circuit 23 is composed of, for example, a PLL circuit, and is configured to take in the output from the synchronization protection circuit 33 as a reference signal (■) and generate a free-running signal that follows the reference signal (■). shall be.

The AND circuit 22 performs a logical product of the coding rule violation signal (2) and the through signal (2), extracts only the coding rule violation bit caused by the sub-signal, and uses this as the set signal (2) of the F and F circuits 32.

On the other hand, the timer signal ■ generated by the timer circuit 31 is F, F
The reset signal for the circuit 32 becomes ■, and the set and reset of the F and F circuits 32 is repeated. It is assumed that the period of the reset signal (3) is also the same as the period of the code rule violation bit caused by the sub signal.

Next, the signal ■' representing the repetition of this set/reset is sent to the F, inverted output (having the opposite polarity of the positive output) of the F circuit 32.
The signal is then sent to the synchronization protection circuit 33. This allows the synchronization protection circuit 33 to perform synchronization processing on the sub-signals without being affected by bits violating the coding rules due to transmission errors.

[Effects of the Invention] According to the present invention as described above, synchronization processing of sub-signals can be performed without being affected by coding rule violation bits due to transmission errors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart in an embodiment of the present invention, and FIG. 4 is a conventional block diagram. FIG. 5 is a block diagram illustrating an example, FIG. 5 is a diagram illustrating a sub-signal synchronization detection situation in a conventional example, and FIG. 6 is a diagram illustrating a sub-signal superimposition situation. In the figure, l is a decoder circuit, 2 is a sub signal mask section, 3.30
a is a synchronization detection section, 10 is a signal separation means, 20 is a sub signal extraction means, 21 is an inhibit signal generation circuit, 22 is an AND circuit, 23 is a through signal generation circuit,
31 is a timer circuit, 32 is an F, F circuit, and 33 is a synchronization protection circuit, respectively.

Claims (1)

[Claims] A sub-signal ([3]) transmitted via a maintenance line is periodically superimposed on a predetermined bit position in a main signal ([11]) having a predetermined sign rule, In a transmission device that transmits the superimposed bit position as a coding rule violation signal ([1]), the main signal ([11]) and the coding rule violation signal ([1]) are selected from the input signal ([10]). a signal separation means (10) for separating the sub-signal ([3]) from the code rule violation signal ([1]) separated from the signal separation means (10); A sub-signal comprising an extracting means (20) and a synchronization detecting means (30) for detecting synchronization of the sub-signal ([3]) extracted from the sub-signal extracting means (20). Synchronous detection circuit.