JPH0323730A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To attain the detection of a second frame synchronizing code and the pull-in of frame synchronization by shifting the detecting position of a first frame synchronizing code by inserting a pseudo synchronizing code detecting pulse compulsorily, and detecting the first frame synchronizing code at a normal position. CONSTITUTION:When no first and second frame synchronizing codes F1 and F2 are detected extending over a prescribed frame period due to the change of the number of pseudo signals of a frame synchronizing signal in transmission data, a frame synchronizing code monitoring circuit 8 generates and inserts one digit of the pseudo synchronizing code pulse compulsorily. Therefore, since the detecting position of the first frame synchronizing code is shifted, the first frame synchronizing code F1 can be detected at the normal position by retrying the detection of the first frame synchronizing code. Also, the second frame synchronizing code F2 can be detected. Thereby, the pull-in of the synchronizing code can be surely performed even when the number of pseudo signals of the frame synchronizing code is changed.

Description

[Detailed description of the invention]

[Object of the Invention] (Industrial Application Field) The present invention relates to a frame synchronization circuit that performs frame synchronization in PCM multiplex communication using two types of synchronization codes. (Prior art) P. In CM multiplex communication, for example, PCM signals are multiplexed in a frame format as shown in FIG.
The frame synchronization code Fl. Communication is performed by inserting F2 respectively. That is, 63 5-digit G units each formed by multiplexing the digital signals of the lower group of the PCM signal bit by bit are combined, and a 5-digit G pulse is added thereto to form a G frame (320 digits). Then, six of these G frames are combined into one frame (1
920 digits), which is used as the unit of PCM multiplex communication. For example, the IG of one frame as shown in FIG.
A first frame synchronization code Fl and a second frame synchronization code F2 are inserted into the G pulse portion of the frame and the fourth G frame, respectively, and are used for PCM multiplex communication. However, on the receiving side of the signal PCM multiplexed and communicated in this way, the frame synchronization circuit is configured as shown in FIG. 4, and the above-mentioned first frame synchronization code F1 and second frame synchronization Each code F2 is detected and the frame synchronization is pulled in (establishment of frame synchronization), and the signal is received and reproduced. In FIG. 14, the Fl detection circuit 1 detects the first frame synchronization code Fl given as the aforementioned 5-digit code from the received signal sequence (transmission data) and outputs the Fl detection pulse signal. The control signal generation circuit 2 receives this Fl detection pulse signal and generates a search control signal. and a noting start signal, respectively. The F2 detection circuit 4 receives the search control signal and starts searching for the second frame synchronization code F2 in the transmission data, and determines whether the second frame synchronization code F2 indicated by the frame format is correct. It is searched whether or not the second frame synchronization code F2 exists at the insertion position, specifically, at the position of the first 5 digits of the 4th G frame. When the second frame synchronization code F2 is detected in this F2 detection circuit 4, an F2 detection pulse is given to the hunting circuit 5, and together with the hunting start signal described above, the first and second frame synchronization codes are detected from the transmitted data. frame synchronization code Fl
．． It is informed that each F2 has been correctly detected. The synchronization protection circuit 6 operates upon receiving the output of the hunting circuit 5, and operates to detect the first and second frame synchronization codes F.
l. The frame synchronization code Fl. It is determined whether each F2 is correctly detected, and frame synchronization is established when each of the frame synchronization codes Fl and F2 is correctly detected over n frames. In other words, frame synchronization is pulled in. By the way, when the F2 detection circuit 4 detects the second frame synchronization code F2 at the correct position and does not generate an F2 detection pulse, the F2 detection circuit 4 outputs a hunting signal. This hunting signal is applied to the frame counter circuit 3 and F2 detection circuit 4 via the OR circuit 7, and each of these circuits 3.4 is reset. Note that even if the synchronization protection circuit 6 does not correctly detect each of the frame synchronization codes F 1 and F 2 over n frames, the synchronization protection circuit 8 issues a hunting signal, and the hunting signal is transmitted via the OR circuit 7. The frame counter circuit 3 and F2 detection circuit 4 are each reset. When the first frame synchronization code Fl is detected again by the above-mentioned Fl detection circuit 1 in this reset state, the frame synchronization establishment (drawing) operation is restarted by the Fl detection pulse. The above synchronization code Fl. By repeatedly executing the F2 detection processing operation, the frame synchronization is pulled in. Furthermore, since the circuit shown in FIG. 4 constitutes a so-called 1-bit immediate shift type synchronization circuit, even in the worst case, the synchronization is always performed after 1920 frames. By the way, when performing this type of PCM multiplex communication, if all of the transmission data of the lower group is 11 L II, that is, if no data is transmitted, the transmission data is transmitted by the above-mentioned first and second synchronization codes Fl. F2, scramble pattern. and only service signals such as parity and game alerts. Therefore, in one frame of transmission data, the first and second synchronization codes F1. Pseudo code Fl' of F2
, F2' occurs. Therefore, these pseudocodes Fl'. The number of F2 degrees changes with changes in the service signal, and becomes an even number or an odd number. If the number of pseudocodes Fl' and F2° becomes an odd number, a problem arises in that frame synchronization cannot be achieved, as will be explained below. That is, as shown in FIG. 5(a), the pseudo code Fl' of the first synchronization code F1 is . Assuming an even number of occurrences as shown in ~■, the Fl detection circuit 1 is first detected at the position of ■.
Pseudocode Fl' is detected at . However, in this case, the F2 detection circuit 4
It is determined whether or not the second frame synchronization code F2 exists at the position (■) half a frame after. However ■
Since the second frame synchronization code F2 does not exist at the position , the detection of the first synchronization code F1 is restarted as described above, and the detection of the first frame synchronization code F1 is restarted at the position However, in this case as well, since the second frame synchronization code F2 does not exist at position fit (equivalently, the position of ■) half a frame after the above position ■, the first frame synchronization code is detected again. The detection of the synchronization code Fl is started.The operation of such processing is the detection of the synchronization code Fl of ml at the position ■.
Detection of (pseudo code Fl') and detection of first synchronization code Fl (.pseudo code F1゛) at position ■ are repeated until the first synchronization code Fl is detected at the normal position. . When the first synchronization code F1 is detected at the correct position, the correct synchronization pull-in operation is performed. However, as shown in FIG. 5(b), the first synchronization code F
When the pseudo code F1' occurring at the position ■ of l disappears due to the service signal, and the number becomes an odd number as shown in ■, ■, ~■, the Fl detection circuit l is first generated at the position ■. The pseudo code Fl' will be detected. And this■
It is determined whether or not the second frame synchronization code F2 is detected at the position ■ after half a frame from the position.
Its detection fails. As a result, by the re-detection operation of the first frame synchronization code Fl, the next pseudo code Fl' is detected at the position of ■. Then, in the same way, it is checked whether or not the second frame synchronization code F2 exists at the position half a frame later (equivalently, the position of Fl' is detected. In this case as well, since the second frame same-mei code F2 does not exist at the position half a frame later (equivalently at the position ■), the pseudo code Fl generated at the position ■ as the next first synchronization code Fl ' is detected, and the state returns to the above-mentioned state. Thereafter, such synchronization code detection processing is repeated semi-permanently. As a result, as described above, when the number of pseudo codes Fl' generated from the first frame synchronization code F1 is an odd number, the first frame synchronization code Fl is not detected at the positive position. , only the pseudo code Fl' is repeatedly detected, causing a problem such as semi-permanently not being able to pull in frame synchronization. (Problems to be Solved by the Invention) As described above, in the conventional frame synchronization circuit that performs frame synchronization in PCM multiplex communication by detecting two types of synchronization codes inserted into the frame,
If the number of synchronization pseudocodes included in the transmission data changes due to service signals, etc., specifically, if the number of pseudocodes becomes an odd number, a situation may occur where frame synchronization cannot be achieved. There was a problem. The present invention was made in consideration of these circumstances, and its purpose is to ensure frame synchronization even when the number of pseudo signals included in transmitted data changes. The object of the present invention is to provide a highly practical frame synchronization circuit. [Structure of the Invention] (Means for Solving:llm) A frame synchronization circuit according to the present invention inserts first and second synchronization codes at a predetermined interval every frame, and
In a communication system that performs CM multiplex communication and pulls in frame synchronization by detecting the first and second synchronization codes, the synchronization code detection circuit detects the first synchronization code; A synchronization code detection (search) circuit that detects the presence or absence of a second synchronization code that is supposed to exist at a predetermined position from the detection position when the first synchronization code is detected, and pulls in frame synchronization. In addition to this function, means is provided for forcibly generating a pseudo synchronization code detection pulse when the first and second synchronization codes are not detected by each of the synchronization code detection circuits for a predetermined frame period. It is characterized by this. (Function) According to the present invention, when the number of pseudo signals of frame synchronization signals in transmission data changes and a state is reached in which two types of synchronization codes cannot be detected semi-permanently, a predetermined number of frames are detected. The above-mentioned condition is detected by monitoring and a pseudo synchronization code detection pulse is forcibly generated. As a result, the detection position of the first frame synchronization code is shifted by this forced pseudo synchronization code detection pulse.
By retrying the detection of the first frame synchronization code, it becomes possible to detect the first frame synchronization code Fl at the correct position, which also makes it possible to detect the second frame synchronization code and to correct its frame synchronization. It is possible to reliably pull it in. Therefore, according to the circuit function of the present invention, even if the pseudo code of the frame synchronization code changes to a service signal etc. and the number thereof changes, synchronization can be ensured by inserting the pseudo synchronization code detection pulse. It becomes possible to have the (Embodiment) Hereinafter, a frame synchronization circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram of an embodiment circuit, in which parts that are basically the same as those of the conventional circuit shown in FIG. 4 are designated by the same reference numerals. The circuit of this embodiment is characterized in that it includes a frame synchronization code monitoring circuit 8 consisting of a frame counter 8a that counts transmission clocks and a NOR circuit 8b that controls the counting operation. This frame synchronization code monitoring circuit 8 inputs the code detection pulse b from the F1 detection circuit l and the synchronization code detection pulse output from the hunting circuit 5 via the NOR circuit 8b, and resets the frame counter 8a. The above-described first and second frame synchronization codes F1. If F2 is not detected, force the pseudo sync code pulse to 1 digit (1 pulse)
It is arranged so that it will occur. The control signal generation circuit 2 receives the code detection pulse b from the Fl detection circuit 1 or the pseudo synchronization code pulse l from the frame synchronization code monitoring circuit 8 via the OR circuit 9, and counts the transmission clock. The frame counter circuit 3 is configured to operate in synchronization with the output of the frame counter circuit 3. In other words, the frame synchronization code monitoring circuit 8 uses, for example, the frame ● format shown in FIGS.
Assuming that CM signal multiplex communication is performed, for example, 1920 frames (3.888.400 digits)
The frame synchronization code detection state (synchronization pull-in state) is monitored over the period. Then, when it is determined that synchronization will not be carried out as it is (specifically, when the frame counter 8b is not reset for 1920 frames), the rlJ-like code is set at an arbitrary position in the next frame (1921 frame). It is configured to forcibly generate the detection pulse i. Next, the specific operation of the circuit of this embodiment including the frame synchronization code monitoring circuit 8 will be explained. When the transmission data is input to the Fl detection circuit 1 and the first frame synchronization code Fl or its pseudo signal Fl' is detected, the Fl detection circuit 1 outputs the Fl code detection pulse signal b. Then, this Fl code detection pulse signal b is applied to the control signal generation circuit 2 via the OR circuit 9, and is also applied to the frame synchronization code monitoring circuit 8 at the same time. This F
In response to the l code detection pulse signal b, the frame counter 8a of the frame synchronization code monitoring circuit 8 is reset and starts counting the transmission clock from that point. Further, the control signal generation circuit 2 generates a hunting start signal h upon receiving the F1 code detection pulse signal b, and supplies this to the hunting circuit 5. The hunting circuit 5 that has received the hunting signal h outputs the hunting signal g since the second frame synchronization signal F2 is not detected by the F2 detection circuit 4 at that particular point, and sends this to the OR circuit 7. The signal is supplied to the frame counter circuit 3 and the F2 detection circuit 4 through the frame counter circuit 3 and the F2 detection circuit 4, respectively. The frame counter circuit 3 is reset by this hunting signal g, and the control signal generation circuit 2 generates the frame counter circuit 3 in synchronization with a predetermined timing that the frame counter circuit 3 counts from the reset point, for example, the above-mentioned frame
In the case of format, the search control signal f is outputted to the F2 detection circuit 4 at a timing of 1/2 frame. As mentioned above, the F2 detection circuit 4 to which the hunting signal g is applied detects the second frame synchronization signal F2 in the transmission data at the timing of receiving the search control signal f.
A search process is performed to determine whether or not it exists. Then, when the second frame synchronization signal F2 is detected at the same timing, F2
The detection circuit 4 provides an F2 code detection pulse signal to the hunting circuit 5. In this way, when the hunting circuit 5 receives the F2 code detection pulse signal from the F2 detection circuit 4, the second frame synchronization code F2 is detected at a predetermined timing position after the detection of the first frame synchronization code Fl. Information d
is output to the Domei protection circuit 6. Then, according to this information d, the synchronization protection circuit 6 transmits the first and second frame synchronization signals F1 . F2
is detected, establish its frame synchronization. When frame synchronization is established in this way, the information d output from the hunting circuit 5 is given to the frame synchronization code monitoring circuit 8, and the counting operation of the frame number by the frame counter 8a is reset. Here, if the F2 detection circuit 4 cannot confirm the presence of the second frame synchronization signal at the timing specified by the control signal generation circuit 2, the synchronization protection circuit 6 detects the second frame synchronization signal from the F2 detection circuit 4. Since the information d indicating that the code F2 has been detected is not obtained, the hunting signal g is output. Then, this hunting signal g is applied to the frame counter circuit 3 and the F2 detection circuit 4 described above through the OR circuit 7, and the frame counter circuit 3 is reset and its operation is temporarily stopped. In this state, when the F1 detection circuit l again detects the first frame synchronization code F1 or its pseudo signal Fl' from the transmission data, the Fl detection circuit l will output the Fl code detection pulse signal b again. The above-described operations are repeatedly performed. and first and second frame synchronization codes Fl. The above-described @ output processing operation of F2 is performed on the first and second frame synchronization codes F1. This is repeated until each F2 is detected in the correct position and its frame synchronization is established. Also in this case, as described above, the frame synchronization code monitoring circuit 8 is reset by the information d indicating the detection of the second frame synchronization code. By the way, the above-mentioned first and second frame synchronization codes F
1. The detection processing operation of F2 is repeatedly executed, and even after 1920 frames counted by the frame synchronization code monitoring circuit 8 have elapsed, the first and second frame synchronization codes F1. If F2 is not detected, the frame counter 8a will not be reset, so the next 192
A certain timing of the lth frame (for example, the position of the last time slot of the 1921st frame; 1920 frames x 1920 digits + 1919 digits -
At the 3,888, and 319th digit), a pulse signal is output from the frame counter 8a. This pulse signal is applied to the control signal generation circuit 2 via the OR circuit 9 independently and in parallel with the Fl code detection pulse signal b output from the Fl detection circuit 1 described above.
This becomes a pseudo signal for the code detection pulse signal b. The signal generated from the frame synchronization code monitoring circuit 8 energizes the control signal generation circuit 2 as a pseudo code detection pulse, and at that point, the detection process of the second frame synchronization code F2 described above is restarted. Ru. By restarting the frame synchronization code F2 detection process by inserting this pseudo code detection pulse, the timing of repeating the second frame synchronization code detection by detecting the pseudo signal Fl' described above is shifted. The above-mentioned first shift with this operating point shift
and a second frame synchronization code F1. By moving the detection position (timing) of F2, when the detection process is repeated, it becomes possible to capture the first frame synchronization code Fl at the regular timing position. To explain this effect with reference to FIG. 5(e), due to the disappearance of the pseudo signal Fl' at the position (■) due to the service signal, etc., the first and second Frame synchronization signal Fl. 1 when F2 is not detected and its frame synchronization is not established.
In the 921st frame, for example, a pseudo code detection pulse F'' is forcibly inserted at the position ■.Then, a second Detection is performed as to whether the frame synchronization code F2 is present. However, since the second frame synchronization code F2 does not exist at this position (2), the above-mentioned reset is applied and the detection operation of the first frame synchronization code Fl is restarted. As a result, the pseudo signal Fl' is detected at the position ■, and it is detected whether or not the second frame synchronization code F2 exists at the position ■ half a frame later. Then, the signal detection fails, and the detection process of the first frame synchronization code F1 is restarted again. When such processing is repeated, the frame synchronization code of '1s2 is detected at the position ■ based on the position ■, and if the detection process fails at the position ■, the frame synchronization code is not detected at the correct position. The first frame synchronization code F1 is detected, and the second frame synchronization signal F2 half a frame later is detected. That is, by inserting the pseudo code detection pulse F'', it becomes possible to make the number of pseudo signals Fl' in one frame an apparently even number, and by failing to detect the second frame synchronization code F2, the first frame synchronization It becomes possible to shift the detection position of the code F! by one pulse, and as a result, it becomes possible to accurately detect the first frame synchronization code F1 existing at a normal position without fail at a certain timing. When the first and second frame synchronization codes F 1 and F 2 are detected in this way, the frame counter 8a of the frame synchronization code monitoring circuit 8 is reset by the output from the hunting circuit 5 described above, and the pseudo code The output of the detection pulse F'' is stopped. In this way, according to the circuit of this embodiment, when performing PCM multiplex communication, all of the transmission data of the lower group is "L", and the transmission data is the synchronization code Fl, F2 of the first and je2, scrambled pattern. Also, when there are only service signals such as parity and game warning, the first and second synchronization codes Fl. A repeating pattern containing pseudo-codes Fl', F2° of F2 is generated, and these pseudo-codes Fl', F2
Even if the number of ゜ changes with a change in the service signal, the frame synchronization can be maintained because the frame synchronization code monitoring circuit 8 is provided which forcibly generates the pseudo code detection pulse F1 as described above. It is possible to reliably pull it in. In other words, the pseudo signal Fl' disappears due to the service signal,
Even if a situation occurs where the detection position of the frame synchronization code is repeatedly performed based on the same position because the number is odd, the frame synchronization code can be detected by forcibly inserting the pseudo code detection pulse F''. Since the detection position is shifted, it is possible to always detect the first frame synchronization code Fl at the correct position at a certain point in time.Therefore, if frame synchronization is not established over a predetermined number of frames, Even if it is e, it is possible to reliably pull in the frame synchronization in the subsequent frame.Moreover, the frame synchronization code 1 monitoring circuit 8 can forcibly generate the pseudo code detection pulse F''. Frame synchronization cannot be established semi-permanently just by doing this process! ! ! (Problems) can be effectively avoided. Note that the present invention is not limited to the embodiments described above. For example, the first and second frame synchronization codes Fl, F2
The insertion position, its code pattern, and the format of the signals constituting one frame may be determined according to the specifications of PCM multiplex communication. In addition, the number of frames over which the pseudo code detection pulse F'' is forcibly generated when frame synchronization is not established can be determined according to the specifications of the communication system. The invention can be implemented with various modifications without departing from the gist thereof.

【Effect of the invention】

As explained above, according to the present invention, the number of pseudo signals of the frame synchronization signal in the transmission data changes and becomes semi-permanent.
When a state occurs in which a certain type of synchronization code cannot be detected, the above-mentioned state is detected by monitoring a predetermined number of frames by the frame synchronization code monitoring circuit, and a pseudo synchronization code detection pulse is forcibly generated. Therefore, according to the present invention, the detection position of the first frame synchronization code is shifted by generating the above-mentioned forced pseudo synchronization code detection pulse,
It is possible to detect the first frame synchronization code Fl at a regular position. This brings about effects such as making it possible to reliably detect the second frame synchronization code and reliably pull in the frame synchronization. In addition, the control form and the configuration of the control circuit section are very simple, and the system is highly practical.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a frame synchronization circuit according to an embodiment of the present invention, and FIGS. 2 and 3 show PCM multiplexing while establishing frame synchronization using first and second frame synchronization codes, respectively. A diagram showing an example of the frame format of a transmission signal when performing communication, Figure 4 is a diagram showing an example of a general structure of a conventional frame synchronization circuit, and Figure 5 is a diagram showing an example of the frame format of a frame synchronization signal. FIG. 4 is a timing diagram for explaining changes in the pull-in effect of frame synchronization caused by the change in frame synchronization. l...Fl detection circuit (first frame synchronization code Fl)
, 2... Control signal generation circuit, 3... Frame counter circuit, 4... F2 detection circuit (second frame synchronization code F2), 5... Hunting circuit, B... Synchronization protection circuit, 7.9... OR circuit, 8... Frame synchronization code monitoring circuit, 8a... Frame counter, 8b...
・Noah circuit.

Claims (1)

[Claims] PCM multiplex communication is performed by inserting first and second synchronization codes at a predetermined interval in each frame, and frame synchronization is performed by detecting the first and second synchronization codes, respectively. 1. A frame synchronization circuit that performs synchronization pull-in, characterized in that the frame synchronization circuit is provided with means for forcibly inputting a pseudo synchronization code detection pulse when synchronization pull-in is not performed over a predetermined frame period.