JP2680993B2 - Frame synchronization detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame sync detecting circuit, and L (L is an integer) in which frame sync bits are multiplexed.
When an error of the frame synchronization bit is detected during N (N is an integer from 2 to a number smaller than M) frame periods in consecutive M (M is an integer of 3 or more) frame periods in the digital signal sequence of the column, a frame is detected. The present invention relates to a frame synchronization detection circuit that determines asynchronous.

[0002]

2. Description of the Related Art A conventional frame synchronization detecting circuit of this type is disclosed in Japanese Patent Laid-Open Publication No. 1-149542 (Title of Invention: Loss of Synchronization Detection Circuit). This frame synchronization detection circuit detects a bit error of n (N) bits or more in continuous m (M) bits of a frame synchronization pattern in a received digital signal string in which each bit of a frame synchronization pattern of 1 bit length is arranged at equal intervals. If detected, it is determined to be frame asynchronous. This frame sync detection circuit
This method is effective when there is a lot of noise in the received digital signal sequence, but when there is an abnormality in the supplied signal, etc., when it appears to be pseudo-synchronized even though it is not actually frame-synchronized ( In False Lock, it is determined that the frame synchronization is established because the error of the synchronization bit is less than n bits although the synchronization is not normal.

A technique for preventing this determination of pseudo synchronization is disclosed in Japanese Patent Laid-Open No. 3-183231 (title of the invention: pseudo synchronization prevention circuit). In order to prevent the detection of pseudo sync in this circuit, a monitoring bit is periodically inserted in a digital signal sequence, and a majority of the results obtained by extracting n bits of this monitoring bit is taken, and the result of this majority is determined by a predetermined number of frames. The frame is out of sync when there are consecutive errors.

[0004]

SUMMARY OF THE INVENTION In the conventional frame synchronization detection circuit which determines that a frame is out of sync when n or more bit errors are detected in m consecutive frame synchronization bits, the frame synchronization is actually not synchronized. In the case where it seems to be pseudo-synchronized, there is a drawback that it is determined that the frame error has been established because the bit error is less than n bits although it is not the normal synchronization.

In order to prevent this pseudo-synchronization, there is a technique of periodically inserting a monitoring bit into a digital signal.
The insertion of the monitoring bit has a drawback that the data transmission rate is lowered.

Therefore, an object of the present invention is to determine that the frame sync bit is asynchronous when an error of the frame sync bit is detected for N frame periods or more of consecutive M frame periods in an L column digital signal sequence in which frame sync bits are multiplexed. While maintaining the characteristics of the frame synchronization detection circuit such as noise resistance, without lowering the signal speed,
An object of the present invention is to provide a frame synchronization detection circuit that can make a normal frame synchronization determination even if there is pseudo synchronization or the like.

[0007]

The frame synchronization detection circuit of the present invention is a continuous M (M is an integer of 3 or more) frame in an L (L is an integer) digital signal sequence in which frame synchronization bits are multiplexed. A first asynchronous detection circuit section for generating a first asynchronous signal when an error of the frame synchronization bit is detected for N (N is an integer from 2 to a number smaller than M) frame periods in the period; and the M frame period. 1
Y in a continuous X (X is an integer of 3 or more) cycle
A second asynchronous detection circuit unit that generates a second asynchronous signal when an error of the frame synchronization bit is detected in a period (Y is an integer from 2 to a number smaller than X ) or more, the first asynchronous signal and the first asynchronous signal. A frame asynchronization determination unit that produces a frame asynchronous signal indicating that the digital signal sequence is not frame synchronized when receiving at least one of the two asynchronous signals.

In the frame synchronization detection circuit, the first asynchronous detection circuit section generates a reference frame synchronization bit in the L column of a pattern corresponding to each frame synchronization bit in the digital signal sequence in the L column. A pattern generation unit, a comparison unit that compares the frame synchronization bit and the reference frame synchronization bit for each digital signal sequence, and generates a frame bit error signal when a bit error of the frame synchronization bit is detected, and the frame bit error signal For each of the M frame periods, and a first counting unit that generates the first asynchronous signal when the count result is N or more, and the second asynchronous detection circuit unit includes the frame bit error signal. And the second counter in response to the period information of the M frame period generated by the first counting unit.
Can be configured to produce an asynchronous signal of.

Further, in the frame synchronization detection circuit, the first counting unit responds to a frame synchronization bit timing signal corresponding to the frame synchronization bit by counting M times for each cycle of the M frame synchronization bits. The second asynchronous detection includes: an M counting circuit that generates a pulse signal as the cycle information; and an N counting circuit that generates the first asynchronous signal in response to the frame bit error signal and the M counting pulse signal. A frame bit error signal determination circuit that determines whether or not the frame bit error signal is present in each cycle of the M frame synchronization bits and outputs the signal in response to the frame bit error signal and the M count pulse signal. A circuit for generating an X counting pulse signal at each end of the X period in response to the M counting pulse signal; Can be the output of the beam-bit error signal determination circuit in response to the X count pulse signal a configuration and a Y counter circuit for producing the second asynchronous signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a frame synchronization detection circuit according to an embodiment of the present invention. Further, FIG. 2 is a signal waveform diagram of a main signal of this embodiment.

This frame synchronization detection circuit includes an L-row digital signal train S1 (S1-1, S1-1) having the same signal structure.
1, 2, ..., S1-L) is received by the comparison unit 1. The digital signal sequence S1 is a signal or the like obtained by separating a signal having a multi-frame structure into L columns by a demultiplexing circuit. The digital signal sequence S1 has a 1-bit frame synchronization bit at the beginning of one frame. The frame synchronization bits are located at timings 1, 2, ..., M in the first digital signal sequence S1-1 shown in FIG. Further, the frame synchronization detection circuit is configured to compare the frame synchronization bit timing signal S2 synchronized with the frame synchronization bit of the digital signal sequence S1 from the device or the like which has transmitted the digital signal sequence S1 with the comparison unit 1, the pattern generation unit 2 and the counting unit 3 To receive.

The pattern generator 2 is responsive to the frame synchronization bit timing signal S2, and has a pattern reference corresponding to each frame synchronization bit of the L digital signal sequences S1-1, S1-2, ..., S1-L. The frame synchronization bit S3 (S3-1, S3-2, ..., S3-L) is generated with one frame length.

The comparator 1 receives the digital signal sequence S1, the timing signal S2, and the reference frame synchronization bit S3, and compares the frame synchronization bit of the digital signal sequence S1 and the reference frame synchronization bit S3 for each digital signal sequence. When a bit error of the frame sync bit is detected, a frame bit error signal S4 is generated.

That is, in the comparison unit 1, first, the exclusive OR circuit 11-1 outputs the digital signal sequence S1-1 and the reference frame synchronization bit S3-1, and the exclusive OR circuit 11-2 outputs the digital signal sequence. S1-2 and reference frame synchronization bit S
3-2 are compared by the exclusive OR circuit 11-L with the digital signal sequence S1-L and the reference frame synchronization bit S3-L, and the digital signal sequence S1 (S1-1, S1-1,
S1-2, ..., S1-L) All bit errors are detected. The bit error of the digital signal sequence S1 is the OR circuit 1
Aggregated by 2. The output of the logical sum circuit 12 is sent to the logical product circuit 13 . The logical product circuit 13 is the logical sum circuit 1
The output of 2 and the timing signal S2 are logically ANDed, and only the error of the frame synchronization bit among the bit errors of the digital signal sequence S1 is transmitted as the frame bit error signal S4. In the M frame period from the first frame to the Mth frame of the digital signal sequence S1 in FIG.
An error has occurred in the frame synchronization bids of the second frame and the fourth frame.

The first counting section 3 responds to the frame bit error signal S4 and the frame synchronization bit timing signal S2, and responds to the L digital signal sequences S1-1, S1-2.
.., S1-L, when a frame sync bit error, that is, a frame bit error signal S4 is detected for N frame periods or more in consecutive M frame periods (M time slots), it is determined that the digital signal sequence S1 is out of frame. A first asynchronous signal S6 for determining is generated.

That is, the M counting circuit 32 of the counting unit 3 counts N M counting pulses S5, which is period information indicating that the digital signal sequence S1 has passed M frame periods, every time M timing signals S2 are counted. It is sent to the circuit 32 as a reset pulse. The N counting circuit 31 responds to the frame bit error signal S4 and the M counting pulse S5, and receives the frame bit error signal during one cycle of the M frame period of the digital signal sequence S1 (the period in which the M frame synchronization bits appear). Count S4. The N counting circuit 31 sends an asynchronous signal S6 when the number of the frame bit error signals S4 to be counted reaches a predetermined N number without being reset by the M counting pulse S5. M shown in FIG.
During the frame period, there is no state in which the asynchronous signal S6 is transmitted.

The period for counting the frame bit error signal S4 of the M counting circuit 32 (the period in which M frame sync bits of the digital signal sequence S1 appear) is easy for the pattern generator 2 to generate the reference frame sync bit S4. Considering this, it is preferable to make it equal to the pattern period of the frame synchronization bits of the digital signal sequence S1.

Number of RS flip-flops of the second counting section 4
Road (RS-F / F)41Is the frame bit error signal
S4And M count pulse signal S5
M frame period of signal sequence S1 (M frame synchronization bits
Frame bit error signal S
4 is determined, and if the signal S4 is present, the frame error is detected.
Frame bit error signal S for outputting the error signal S41
4 is a discrimination circuit. RS flip-flop circuit41
Changes the output to "H" when the signal S4 is input to the terminal S.
When the signal S5 is input to the terminal R, the output is "L".
Return to This output "H" indicates that the first counting unit 3
During the M frame period for counting the bit error signal S4,
Error indicating that there is an error in the home sync bit
This is the signal S41. The frame error signal S41 of FIG.
Is an error in the frame sync bit during the M frame period shown in the figure.
It indicates that there is.

The X counting circuit 43 outputs an X counting pulse S43 every time a predetermined number of M counting pulses S5 sent from the M counting circuit 32 are counted. The Y counting circuit 42 uses X
The counting pulse S43 is used as a reset pulse, and counting is performed until the number of frame error signals S41 "with error" reaches a predetermined Y. In other words, the Y counting circuit 42 sets the cycle in which M frame sync bits appear as one cycle, and detects whether or not there are more than Y cycles of the frame sync bits in consecutive X cycles. The Y counting circuit 42 uses X
If Y number of "errored" frame error signals S41 are counted before being reset by the counting pulse S43, there is a frame synchronization bit error of the digital signal sequence S1 for more than Y periods during the X period, and therefore the digital signal sequence S
A second asynchronous signal S7 is generated which indicates that 1 is frame asynchronous. The asynchronous signal S7 in FIG. 2 indicates that the illustrated X cycle is frame asynchronous.

Counting unit 4 which is the second asynchronous detection circuit
Even when the first asynchronous detection circuit including the comparison unit 1, the pattern generation unit 2, and the counting unit 3 does not generate the first asynchronous signal S6 that determines that the digital signal sequence S1 is frame asynchronous, the above X Predetermined ratio Y in the cycle
If there is a frame synchronization bit error in a cycle of / X or more, the second frame asynchronous signal S7 is transmitted and it is determined that the digital signal sequence S1 is frame asynchronous. This has an effect of correctly detecting the frame asynchronization of the signal sequence S1 even when the signal sequence S1 is not in normal synchronization, but the error in the frame synchronization bit is small due to pseudo synchronization or the like.

Asynchronous signal S6 from counter 3 and counter 3
The asynchronous signal S7 from the above is logically ORed by the logical OR circuit 51 of the frame asynchronous determination section 5. When receiving at least one of the asynchronous signals S7 and S8, the OR circuit 51 generates the frame asynchronous signal S8 indicating that the digital signal sequence S1 is frame asynchronous.

In the present embodiment, the frame synchronization bit of the digital signal sequence S1 is described as an example in which only one bit is provided at the beginning of each frame, but this frame synchronization bit is patterned by a plurality of codes. May be. In this case, the pattern generator 2 generates the reference frame synchronization bit S3 corresponding to the timing of the patterned frame synchronization bit, and the frame synchronization timing signal S2 is also a signal of the timing corresponding to the pattern of the frame synchronization bit. Good.

[0024]

As described above, according to the present invention, a cycle in which M frame sync bits appear in a digital signal sequence is defined as one cycle, and an error of the frame sync bit occurs in Y cycles or more in consecutive X cycles. Upon detection, a second asynchronous signal that determines that the digital signal sequence is frame asynchronous is generated from the second asynchronous detection circuit unit, so that N frame periods in M consecutive frame periods in the L digital signal sequence are generated. As described above, when the error of the frame synchronization bit is detected, the first asynchronous signal determines that the digital signal sequence is frame asynchronous, and while maintaining the characteristics such as the noise resistance of the frame synchronization detection circuit, the signal speed is reduced. There is an effect that normal frame synchronization determination can be performed even if there is pseudo synchronization or the like without occurring.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frame synchronization detection circuit according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of a main signal of the present embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 comparison part 2 pattern generation part 3,4 counting part 5 frame asynchronous determination part 11 (11-1, 11-2, ..., 11-L) exclusive OR circuit 12,51 logical sum circuit 13 AND circuit 31 N Counting circuit 32 M counting circuit 41 RS flip-flop circuit (RS-F / F) 42 Y counting circuit 43 X counting circuit

Claims (3)

(57) [Claims] 1. L (L) in which frame synchronization bits are multiplexed
Is an integer) and there are consecutive M in the digital signal sequence.
(N is an integer greater than or equal to 3) N (N is an integer from 2 to a number smaller than M) frame periods during a frame period, and a first asynchronous signal is generated when an error in the frame synchronization bit is detected. The detection circuit unit and the error of the frame synchronization bit in Y (Y is an integer from 2 to a number smaller than X ) cycles in consecutive X (X is an integer of 3 or more) cycles with the M frame period as one cycle. A second asynchronous detection circuit unit that generates a second asynchronous signal when detecting
Frame asynchronous determination unit that generates a frame asynchronous signal indicating that the digital signal sequence is not frame synchronized when receiving at least one of the asynchronous signal and the second asynchronous signal. Detection circuit. 2. The first asynchronous detection circuit unit includes the L
A pattern generation unit for generating a reference frame synchronization bit of the L column of a pattern corresponding to each of the frame synchronization bits of the digital signal sequence of the column, and the frame synchronization bit and the reference frame synchronization bit for each digital signal sequence And a comparator for generating a frame bit error signal when a bit error of the frame synchronization bit is detected, and the frame bit error signal is counted every M frame periods, and the count result is N or more, the first
And a second counting circuit for generating the asynchronous signal of the M-frame period in response to the frame bit error signal and the period information of the M frame period generated by the first counting unit. The frame synchronization detection circuit according to claim 1, wherein the second asynchronous signal is generated as a result. 3. The first counting unit, in response to a frame sync bit timing signal corresponding to the frame sync bit, uses an M count pulse signal as the cycle information for each cycle of the M frame sync bits. A counter circuit for generating a frame bit error signal and an N counter circuit for generating the first asynchronous signal in response to the frame bit error signal and the M count pulse signal. A frame bit error signal discriminating circuit which discriminates and outputs the frame bit error signal for each cycle of the M frame synchronization bits in response to an error signal and the M counting pulse signal, and the M counting pulse X in response to the signal, producing an X counting pulse signal at the end of each of the X periods.
3. The frame synchronization according to claim 2, further comprising: a counting circuit; and a Y counting circuit that generates the second asynchronous signal in response to the output of the frame bit error signal determination circuit and the X counting pulse signal. Detection circuit.