JPH01112332A - 乗算及び算術論理演算機能を組合わせて使用する浮動小数点ユニット - Google Patents

乗算及び算術論理演算機能を組合わせて使用する浮動小数点ユニット

Info

Publication number
JPH01112332A
JPH01112332A JP63219605A JP21960588A JPH01112332A JP H01112332 A JPH01112332 A JP H01112332A JP 63219605 A JP63219605 A JP 63219605A JP 21960588 A JP21960588 A JP 21960588A JP H01112332 A JPH01112332 A JP H01112332A
Authority
JP
Japan
Prior art keywords
decimal
product
exponent
sum
carry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63219605A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0542013B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
George K Chu
ジョージ・カイ−ジン・チュウ
Jan Fandrianto
ジャン・ファンドリアント
Y W Sing
ワイ・ダブリュー・シング
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WEYTEC CORP
Weitek Corp
Original Assignee
WEYTEC CORP
Weitek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by WEYTEC CORP, Weitek Corp filed Critical WEYTEC CORP
Publication of JPH01112332A publication Critical patent/JPH01112332A/ja
Publication of JPH0542013B2 publication Critical patent/JPH0542013B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP63219605A 1987-09-01 1988-08-31 乗算及び算術論理演算機能を組合わせて使用する浮動小数点ユニット Granted JPH01112332A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US92,023 1987-09-01
US07/092,023 US4866652A (en) 1987-09-01 1987-09-01 Floating point unit using combined multiply and ALU functions

Publications (2)

Publication Number Publication Date
JPH01112332A true JPH01112332A (ja) 1989-05-01
JPH0542013B2 JPH0542013B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-06-25

Family

ID=22230920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63219605A Granted JPH01112332A (ja) 1987-09-01 1988-08-31 乗算及び算術論理演算機能を組合わせて使用する浮動小数点ユニット

Country Status (2)

Country Link
US (1) US4866652A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH01112332A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2695178B2 (ja) * 1988-03-11 1997-12-24 富士通株式会社 演算回路
US4969118A (en) * 1989-01-13 1990-11-06 International Business Machines Corporation Floating point unit for calculating A=XY+Z having simultaneous multiply and add
EP0537205B1 (de) * 1990-07-04 1994-08-31 Siemens Aktiengesellschaft Anordnung zur emulation neuronaler netze und verfahren zu ihrem betrieb
JPH04127364A (ja) * 1990-09-19 1992-04-28 Nec Corp 積和算器
JPH04165530A (ja) * 1990-10-30 1992-06-11 Nec Corp 浮動小数点乗算装置
US5245564A (en) * 1991-05-10 1993-09-14 Weitek Corporation Apparatus for multiplying operands
US6441842B1 (en) * 1992-02-19 2002-08-27 8×8, Inc. Video compression/decompression processing and processors
US5375078A (en) * 1992-12-15 1994-12-20 International Business Machines Corporation Arithmetic unit for performing XY+B operation
KR0152169B1 (ko) * 1994-06-07 1998-10-15 모리시다 요이치 프라이어리티, 인코더
US5687340A (en) * 1995-05-16 1997-11-11 Hewlett-Packard Company Reduced area floating point processor control logic utilizing a decoder between a control unit and the FPU
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
US7242414B1 (en) * 1999-07-30 2007-07-10 Mips Technologies, Inc. Processor having a compare extension of an instruction set architecture
US6732259B1 (en) 1999-07-30 2004-05-04 Mips Technologies, Inc. Processor having a conditional branch extension of an instruction set architecture
US6631392B1 (en) 1999-07-30 2003-10-07 Mips Technologies, Inc. Method and apparatus for predicting floating-point exceptions
US6912559B1 (en) 1999-07-30 2005-06-28 Mips Technologies, Inc. System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit
US7346643B1 (en) * 1999-07-30 2008-03-18 Mips Technologies, Inc. Processor with improved accuracy for multiply-add operations
US6714197B1 (en) 1999-07-30 2004-03-30 Mips Technologies, Inc. Processor having an arithmetic extension of an instruction set architecture
US6697832B1 (en) * 1999-07-30 2004-02-24 Mips Technologies, Inc. Floating-point processor with improved intermediate result handling
US6745318B1 (en) * 1999-08-18 2004-06-01 Sanjay Mansingh Method and apparatus of configurable processing
US6571266B1 (en) * 2000-02-21 2003-05-27 Hewlett-Packard Development Company, L.P. Method for acquiring FMAC rounding parameters
US6996596B1 (en) 2000-05-23 2006-02-07 Mips Technologies, Inc. Floating-point processor with operating mode having improved accuracy and high performance
US7543013B2 (en) * 2006-08-18 2009-06-02 Qualcomm Incorporated Multi-stage floating-point accumulator
US8161090B2 (en) * 2008-12-05 2012-04-17 Crossfield Technology LLC Floating-point fused add-subtract unit
US9329936B2 (en) 2012-12-31 2016-05-03 Intel Corporation Redundant execution for reliability in a super FMA ALU

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61141034A (ja) * 1984-12-14 1986-06-28 Hitachi Ltd 演算結果限界割出し装置

Also Published As

Publication number Publication date
US4866652A (en) 1989-09-12
JPH0542013B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-06-25

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