JPH01111343U - - Google Patents

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Publication number
JPH01111343U
JPH01111343U JP592288U JP592288U JPH01111343U JP H01111343 U JPH01111343 U JP H01111343U JP 592288 U JP592288 U JP 592288U JP 592288 U JP592288 U JP 592288U JP H01111343 U JPH01111343 U JP H01111343U
Authority
JP
Japan
Prior art keywords
supply voltage
clock
circuit
signal
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP592288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP592288U priority Critical patent/JPH01111343U/ja
Publication of JPH01111343U publication Critical patent/JPH01111343U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本案により基本構成図、第2図は従来
例の構成図、第3図は本案による一実施例を示す
構成図である。 1……論理回路部、2……電源部、3……クロ
ツク発生回路、4……クロツク切替回路、5……
ロジツク回路、6……出力回路、7……電圧制御
回路、8……安定化電源回路、9……表示器、1
1……スイツチング回路、12……トランス、1
3……パルストランス、14……誤差検出回路、
15……出力平滑回路。
FIG. 1 is a basic configuration diagram according to the present invention, FIG. 2 is a configuration diagram of a conventional example, and FIG. 3 is a configuration diagram showing an embodiment according to the present invention. DESCRIPTION OF SYMBOLS 1...Logic circuit section, 2...Power supply section, 3...Clock generation circuit, 4...Clock switching circuit, 5...
Logic circuit, 6... Output circuit, 7... Voltage control circuit, 8... Stabilized power supply circuit, 9... Display, 1
1... Switching circuit, 12... Transformer, 1
3...Pulse transformer, 14...Error detection circuit,
15...Output smoothing circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 繰返し周期の異る複数のクロツク発生回路とク
ロツク切替回路、さらに論理回路の供給電圧を変
化させるための電圧制御回路、およびそれらを制
御するための出力回路を有したマイクロプロセツ
サやデジタル機器において、クロツク切替指示信
号や供給電圧切替信号をプログラムにより出力し
て、装置内を制御しているクロツク信号および供
給電圧に変化を与え、該クロツク信号と供給電圧
のあらゆる組合せによる回路マージンを検査する
ことを特徴とした論理回路のマージン診断方式。
In microprocessors and digital devices that have multiple clock generation circuits and clock switching circuits with different repetition periods, a voltage control circuit for changing the supply voltage of logic circuits, and an output circuit for controlling them, It is possible to output a clock switching instruction signal and a supply voltage switching signal by a program to change the clock signal and supply voltage that control the inside of the device, and to inspect the circuit margin due to all combinations of the clock signal and supply voltage. Featured margin diagnosis method for logic circuits.
JP592288U 1988-01-22 1988-01-22 Pending JPH01111343U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP592288U JPH01111343U (en) 1988-01-22 1988-01-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP592288U JPH01111343U (en) 1988-01-22 1988-01-22

Publications (1)

Publication Number Publication Date
JPH01111343U true JPH01111343U (en) 1989-07-27

Family

ID=31209718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP592288U Pending JPH01111343U (en) 1988-01-22 1988-01-22

Country Status (1)

Country Link
JP (1) JPH01111343U (en)

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