JPS59115541U - AC load switchgear - Google Patents

AC load switchgear

Info

Publication number
JPS59115541U
JPS59115541U JP974083U JP974083U JPS59115541U JP S59115541 U JPS59115541 U JP S59115541U JP 974083 U JP974083 U JP 974083U JP 974083 U JP974083 U JP 974083U JP S59115541 U JPS59115541 U JP S59115541U
Authority
JP
Japan
Prior art keywords
relay
load
reference clock
switching device
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP974083U
Other languages
Japanese (ja)
Inventor
雅信 繁田
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP974083U priority Critical patent/JPS59115541U/en
Publication of JPS59115541U publication Critical patent/JPS59115541U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来装置の回路図、第2図は第1図に示した装
置の動作を示すタイムチャート、第3図は本考案による
実施例の回路図、第4図は第3図に示した装置の動作を
示すタイムチャートである。 1・・・演算制御装置、P・・・交流電源、D・・・ダ
イオード、PC・・・フォトカプラ、X・・・リレー、
Xリレー接点、L・・・交流負荷、DB・・・ダイオー
ドブリッジ、FF□、 FF2・・・Dフリップフロッ
プ、NDl。 ND2・・・NANDゲート回路、DR・・・リレード
ライバー、R□〜R8・・・抵抗。
FIG. 1 is a circuit diagram of a conventional device, FIG. 2 is a time chart showing the operation of the device shown in FIG. 1, FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the device. 1... Arithmetic control device, P... AC power supply, D... diode, PC... photocoupler, X... relay,
X relay contact, L...AC load, DB...diode bridge, FF□, FF2...D flip-flop, NDl. ND2...NAND gate circuit, DR...relay driver, R□~R8...resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 交流電源に同期した基準クロックパルスを計数してリレ
ーの動作時間を決定するためのタイマを備え、前記リレ
ーの接点により前記交流電源の負荷を開閉する交流負荷
開閉装置において、前記交流電源の全波整流波形に同期
したパルスを2分周したパルスを前記基準クロックパル
スとして発生する回路と、前記タイマによる基準クロッ
クパルスの計数時点の前記交流電源に対する位相が前記
リレーの動作毎に180度異なるように切換える切換回
路とを設けたことを特徴とする交流負荷開閉装置・  
               ?1 閃
In an AC load switching device that includes a timer for counting reference clock pulses synchronized with an AC power source to determine the operating time of a relay, the AC load switching device switches a load of the AC power source using a contact point of the relay. A circuit that generates a pulse obtained by dividing a pulse synchronized with a rectified waveform by two as the reference clock pulse, and a phase with respect to the AC power supply at the time when the reference clock pulse is counted by the timer differs by 180 degrees for each operation of the relay. An AC load switching device characterized by being equipped with a switching circuit for switching.
? 1 flash
JP974083U 1983-01-25 1983-01-25 AC load switchgear Pending JPS59115541U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP974083U JPS59115541U (en) 1983-01-25 1983-01-25 AC load switchgear

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP974083U JPS59115541U (en) 1983-01-25 1983-01-25 AC load switchgear

Publications (1)

Publication Number Publication Date
JPS59115541U true JPS59115541U (en) 1984-08-04

Family

ID=30141193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP974083U Pending JPS59115541U (en) 1983-01-25 1983-01-25 AC load switchgear

Country Status (1)

Country Link
JP (1) JPS59115541U (en)

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